clk domain with rvoclkhdr
This commit is contained in:
Laraib Khan
parent
b8b042faa8
commit
e1ce51fdd4
|
|
@ -344,69 +344,69 @@ circuit lsu_clkdomain :
|
||||||
reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
|
reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
|
||||||
_T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
|
_T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
|
||||||
lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
|
lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
|
||||||
node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59]
|
node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:60]
|
||||||
inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
|
inst rvclkhdr of rvclkhdr @[lib.scala 352:22]
|
||||||
rvclkhdr.clock <= clock
|
rvclkhdr.clock <= clock
|
||||||
rvclkhdr.reset <= reset
|
rvclkhdr.reset <= reset
|
||||||
rvclkhdr.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr.io.en <= _T_29 @[lib.scala 345:16]
|
rvclkhdr.io.en <= _T_29 @[lib.scala 354:16]
|
||||||
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
|
io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
|
||||||
node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59]
|
node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:60]
|
||||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
|
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 352:22]
|
||||||
rvclkhdr_1.clock <= clock
|
rvclkhdr_1.clock <= clock
|
||||||
rvclkhdr_1.reset <= reset
|
rvclkhdr_1.reset <= reset
|
||||||
rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_1.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_1.io.en <= _T_30 @[lib.scala 345:16]
|
rvclkhdr_1.io.en <= _T_30 @[lib.scala 354:16]
|
||||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
|
io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
|
||||||
node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:59]
|
node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:60]
|
||||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22]
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:22]
|
||||||
rvclkhdr_2.clock <= clock
|
rvclkhdr_2.clock <= clock
|
||||||
rvclkhdr_2.reset <= reset
|
rvclkhdr_2.reset <= reset
|
||||||
rvclkhdr_2.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_2.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_2.io.en <= _T_31 @[lib.scala 345:16]
|
rvclkhdr_2.io.en <= _T_31 @[lib.scala 354:16]
|
||||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
|
io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
|
||||||
node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:59]
|
node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:60]
|
||||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 343:22]
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:22]
|
||||||
rvclkhdr_3.clock <= clock
|
rvclkhdr_3.clock <= clock
|
||||||
rvclkhdr_3.reset <= reset
|
rvclkhdr_3.reset <= reset
|
||||||
rvclkhdr_3.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_3.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_3.io.en <= _T_32 @[lib.scala 345:16]
|
rvclkhdr_3.io.en <= _T_32 @[lib.scala 354:16]
|
||||||
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
|
io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
|
||||||
node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:65]
|
node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:66]
|
||||||
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 343:22]
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:22]
|
||||||
rvclkhdr_4.clock <= clock
|
rvclkhdr_4.clock <= clock
|
||||||
rvclkhdr_4.reset <= reset
|
rvclkhdr_4.reset <= reset
|
||||||
rvclkhdr_4.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_4.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_4.io.en <= _T_33 @[lib.scala 345:16]
|
rvclkhdr_4.io.en <= _T_33 @[lib.scala 354:16]
|
||||||
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
|
io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
|
||||||
node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:65]
|
node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:66]
|
||||||
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22]
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:22]
|
||||||
rvclkhdr_5.clock <= clock
|
rvclkhdr_5.clock <= clock
|
||||||
rvclkhdr_5.reset <= reset
|
rvclkhdr_5.reset <= reset
|
||||||
rvclkhdr_5.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_5.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_5.io.en <= _T_34 @[lib.scala 345:16]
|
rvclkhdr_5.io.en <= _T_34 @[lib.scala 354:16]
|
||||||
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
|
io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
|
||||||
node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:63]
|
node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:64]
|
||||||
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22]
|
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:22]
|
||||||
rvclkhdr_6.clock <= clock
|
rvclkhdr_6.clock <= clock
|
||||||
rvclkhdr_6.reset <= reset
|
rvclkhdr_6.reset <= reset
|
||||||
rvclkhdr_6.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_6.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_6.io.en <= _T_35 @[lib.scala 345:16]
|
rvclkhdr_6.io.en <= _T_35 @[lib.scala 354:16]
|
||||||
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
|
io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
|
||||||
node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:66]
|
node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67]
|
||||||
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22]
|
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:22]
|
||||||
rvclkhdr_7.clock <= clock
|
rvclkhdr_7.clock <= clock
|
||||||
rvclkhdr_7.reset <= reset
|
rvclkhdr_7.reset <= reset
|
||||||
rvclkhdr_7.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_7.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_7.io.en <= _T_36 @[lib.scala 345:16]
|
rvclkhdr_7.io.en <= _T_36 @[lib.scala 354:16]
|
||||||
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
|
io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
|
||||||
node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
|
node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
|
||||||
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22]
|
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22]
|
||||||
|
|
@ -416,13 +416,13 @@ circuit lsu_clkdomain :
|
||||||
rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
|
rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
|
||||||
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||||
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
|
io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
|
||||||
node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:65]
|
node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66]
|
||||||
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22]
|
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 352:22]
|
||||||
rvclkhdr_9.clock <= clock
|
rvclkhdr_9.clock <= clock
|
||||||
rvclkhdr_9.reset <= reset
|
rvclkhdr_9.reset <= reset
|
||||||
rvclkhdr_9.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_9.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_9.io.en <= _T_38 @[lib.scala 345:16]
|
rvclkhdr_9.io.en <= _T_38 @[lib.scala 354:16]
|
||||||
rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
|
io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
|
||||||
node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
|
node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
|
||||||
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 343:22]
|
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 343:22]
|
||||||
|
|
@ -432,12 +432,12 @@ circuit lsu_clkdomain :
|
||||||
rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
|
rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
|
||||||
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||||
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
|
io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
|
||||||
node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:62]
|
node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63]
|
||||||
inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 343:22]
|
inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 352:22]
|
||||||
rvclkhdr_11.clock <= clock
|
rvclkhdr_11.clock <= clock
|
||||||
rvclkhdr_11.reset <= reset
|
rvclkhdr_11.reset <= reset
|
||||||
rvclkhdr_11.io.clk <= clock @[lib.scala 344:17]
|
rvclkhdr_11.io.clk <= clock @[lib.scala 353:17]
|
||||||
rvclkhdr_11.io.en <= _T_40 @[lib.scala 345:16]
|
rvclkhdr_11.io.en <= _T_40 @[lib.scala 354:16]
|
||||||
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
|
||||||
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]
|
io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]
|
||||||
|
|
||||||
|
|
|
||||||
160
lsu_clkdomain.v
160
lsu_clkdomain.v
|
|
@ -107,54 +107,54 @@ module lsu_clkdomain(
|
||||||
reg [31:0] _RAND_1;
|
reg [31:0] _RAND_1;
|
||||||
reg [31:0] _RAND_2;
|
reg [31:0] _RAND_2;
|
||||||
`endif // RANDOMIZE_REG_INIT
|
`endif // RANDOMIZE_REG_INIT
|
||||||
wire rvclkhdr_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_1_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_1_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_1_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_1_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_1_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_2_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_2_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_2_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_2_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_2_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_3_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_3_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_3_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_3_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_3_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_4_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_4_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_4_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_4_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_4_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_5_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_5_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_5_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_5_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_6_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_6_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_6_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_6_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_7_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_7_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_7_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_7_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_7_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_8_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_8_io_clk; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_8_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_8_io_en; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_9_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_9_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_9_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_9_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_9_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_10_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_10_io_clk; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_10_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_10_io_en; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22]
|
||||||
wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22]
|
wire rvclkhdr_11_io_l1clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_11_io_clk; // @[lib.scala 343:22]
|
wire rvclkhdr_11_io_clk; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_11_io_en; // @[lib.scala 343:22]
|
wire rvclkhdr_11_io_en; // @[lib.scala 352:22]
|
||||||
wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22]
|
wire rvclkhdr_11_io_scan_mode; // @[lib.scala 352:22]
|
||||||
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 64:47]
|
wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 64:47]
|
||||||
wire lsu_c1_m_clken = _T | io_clk_override; // @[lsu_clkdomain.scala 64:65]
|
wire lsu_c1_m_clken = _T | io_clk_override; // @[lsu_clkdomain.scala 64:65]
|
||||||
reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 84:67]
|
reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 84:67]
|
||||||
|
|
@ -182,49 +182,49 @@ module lsu_clkdomain(
|
||||||
reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 82:62]
|
reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 82:62]
|
||||||
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
|
wire _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
|
||||||
wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
|
wire _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
|
||||||
rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_io_l1clk),
|
.io_l1clk(rvclkhdr_io_l1clk),
|
||||||
.io_clk(rvclkhdr_io_clk),
|
.io_clk(rvclkhdr_io_clk),
|
||||||
.io_en(rvclkhdr_io_en),
|
.io_en(rvclkhdr_io_en),
|
||||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_1 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||||
.io_clk(rvclkhdr_1_io_clk),
|
.io_clk(rvclkhdr_1_io_clk),
|
||||||
.io_en(rvclkhdr_1_io_en),
|
.io_en(rvclkhdr_1_io_en),
|
||||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_2 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||||
.io_clk(rvclkhdr_2_io_clk),
|
.io_clk(rvclkhdr_2_io_clk),
|
||||||
.io_en(rvclkhdr_2_io_en),
|
.io_en(rvclkhdr_2_io_en),
|
||||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_3 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_3_io_l1clk),
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
||||||
.io_clk(rvclkhdr_3_io_clk),
|
.io_clk(rvclkhdr_3_io_clk),
|
||||||
.io_en(rvclkhdr_3_io_en),
|
.io_en(rvclkhdr_3_io_en),
|
||||||
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_4 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_4_io_l1clk),
|
.io_l1clk(rvclkhdr_4_io_l1clk),
|
||||||
.io_clk(rvclkhdr_4_io_clk),
|
.io_clk(rvclkhdr_4_io_clk),
|
||||||
.io_en(rvclkhdr_4_io_en),
|
.io_en(rvclkhdr_4_io_en),
|
||||||
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
.io_scan_mode(rvclkhdr_4_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_5 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_5_io_l1clk),
|
.io_l1clk(rvclkhdr_5_io_l1clk),
|
||||||
.io_clk(rvclkhdr_5_io_clk),
|
.io_clk(rvclkhdr_5_io_clk),
|
||||||
.io_en(rvclkhdr_5_io_en),
|
.io_en(rvclkhdr_5_io_en),
|
||||||
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
.io_scan_mode(rvclkhdr_5_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_6_io_l1clk),
|
.io_l1clk(rvclkhdr_6_io_l1clk),
|
||||||
.io_clk(rvclkhdr_6_io_clk),
|
.io_clk(rvclkhdr_6_io_clk),
|
||||||
.io_en(rvclkhdr_6_io_en),
|
.io_en(rvclkhdr_6_io_en),
|
||||||
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
.io_scan_mode(rvclkhdr_6_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_7_io_l1clk),
|
.io_l1clk(rvclkhdr_7_io_l1clk),
|
||||||
.io_clk(rvclkhdr_7_io_clk),
|
.io_clk(rvclkhdr_7_io_clk),
|
||||||
.io_en(rvclkhdr_7_io_en),
|
.io_en(rvclkhdr_7_io_en),
|
||||||
|
|
@ -236,7 +236,7 @@ module lsu_clkdomain(
|
||||||
.io_en(rvclkhdr_8_io_en),
|
.io_en(rvclkhdr_8_io_en),
|
||||||
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
.io_scan_mode(rvclkhdr_8_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_9 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_9_io_l1clk),
|
.io_l1clk(rvclkhdr_9_io_l1clk),
|
||||||
.io_clk(rvclkhdr_9_io_clk),
|
.io_clk(rvclkhdr_9_io_clk),
|
||||||
.io_en(rvclkhdr_9_io_en),
|
.io_en(rvclkhdr_9_io_en),
|
||||||
|
|
@ -248,7 +248,7 @@ module lsu_clkdomain(
|
||||||
.io_en(rvclkhdr_10_io_en),
|
.io_en(rvclkhdr_10_io_en),
|
||||||
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
||||||
);
|
);
|
||||||
rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22]
|
rvclkhdr rvclkhdr_11 ( // @[lib.scala 352:22]
|
||||||
.io_l1clk(rvclkhdr_11_io_l1clk),
|
.io_l1clk(rvclkhdr_11_io_l1clk),
|
||||||
.io_clk(rvclkhdr_11_io_clk),
|
.io_clk(rvclkhdr_11_io_clk),
|
||||||
.io_en(rvclkhdr_11_io_en),
|
.io_en(rvclkhdr_11_io_en),
|
||||||
|
|
@ -268,42 +268,42 @@ module lsu_clkdomain(
|
||||||
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 96:26]
|
assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 96:26]
|
||||||
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 97:26]
|
assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 97:26]
|
||||||
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 98:26]
|
assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 98:26]
|
||||||
assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_1_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_2_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_3_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_4_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_5_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_6_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_7_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
|
||||||
assign rvclkhdr_8_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16]
|
assign rvclkhdr_8_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16]
|
||||||
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||||
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_9_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
|
||||||
assign rvclkhdr_10_io_en = io_lsu_busm_clken; // @[lib.scala 345:16]
|
assign rvclkhdr_10_io_en = io_lsu_busm_clken; // @[lib.scala 345:16]
|
||||||
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||||
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
|
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 353:17]
|
||||||
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 345:16]
|
assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 354:16]
|
||||||
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
assign rvclkhdr_11_io_scan_mode = 1'h0; // @[lib.scala 355:23]
|
||||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
`define RANDOMIZE
|
`define RANDOMIZE
|
||||||
`endif
|
`endif
|
||||||
|
|
|
||||||
|
|
@ -347,6 +347,15 @@ trait lib extends param{
|
||||||
cg.io.l1clk
|
cg.io.l1clk
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
object rvoclkhdr {
|
||||||
|
def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
|
||||||
|
val cg = Module(new rvclkhdr)
|
||||||
|
cg.io.clk := clk
|
||||||
|
cg.io.en := en
|
||||||
|
cg.io.scan_mode := 0.U
|
||||||
|
cg.io.l1clk
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
|
def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
|
||||||
val REGION_BITS = 4
|
val REGION_BITS = 4
|
||||||
|
|
|
||||||
|
|
@ -84,19 +84,21 @@ class lsu_clkdomain extends Module with RequireAsyncReset with lib{
|
||||||
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
|
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
|
||||||
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
|
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
|
||||||
|
|
||||||
io.lsu_c1_m_clk := rvclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode)
|
io.lsu_c1_m_clk := rvoclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode)
|
||||||
io.lsu_c1_r_clk := rvclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode)
|
io.lsu_c1_r_clk := rvoclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode)
|
||||||
io.lsu_c2_m_clk := rvclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode)
|
io.lsu_c2_m_clk := rvoclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode)
|
||||||
io.lsu_c2_r_clk := rvclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode)
|
io.lsu_c2_r_clk := rvoclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode)
|
||||||
io.lsu_store_c1_m_clk := rvclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode)
|
io.lsu_store_c1_m_clk := rvoclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode)
|
||||||
io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode)
|
io.lsu_store_c1_r_clk := rvoclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode)
|
||||||
io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode)
|
io.lsu_stbuf_c1_clk := rvoclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode)
|
||||||
io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode)
|
io.lsu_bus_ibuf_c1_clk := rvoclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode)
|
||||||
io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,io.lsu_bus_obuf_c1_clken.asBool,io.scan_mode)
|
io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,io.lsu_bus_obuf_c1_clken.asBool,io.scan_mode)
|
||||||
io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode)
|
io.lsu_bus_buf_c1_clk := rvoclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode)
|
||||||
io.lsu_busm_clk := rvclkhdr(clock,io.lsu_busm_clken.asBool,io.scan_mode)
|
io.lsu_busm_clk := rvclkhdr(clock,io.lsu_busm_clken.asBool,io.scan_mode)
|
||||||
io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode)
|
io.lsu_free_c2_clk := rvoclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode)
|
||||||
|
}
|
||||||
|
object clkdomain extends App {
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_clkdomain()))
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,290 +1,290 @@
|
||||||
import chisel3._
|
//import chisel3._
|
||||||
import chisel3.util._
|
//import chisel3.util._
|
||||||
import ifu._
|
//import ifu._
|
||||||
import dec._
|
//import dec._
|
||||||
import exu._
|
//import exu._
|
||||||
import lsu._
|
//import lsu._
|
||||||
import lib._
|
//import lib._
|
||||||
import include._
|
//import include._
|
||||||
import dbg._
|
//import dbg._
|
||||||
import mem.mem_lsu
|
//import mem.mem_lsu
|
||||||
class quasar_bundle extends Bundle with lib{
|
//class quasar_bundle extends Bundle with lib{
|
||||||
val lsu_axi = new axi_channels(LSU_BUS_TAG)
|
// val lsu_axi = new axi_channels(LSU_BUS_TAG)
|
||||||
val ifu_axi = new axi_channels(IFU_BUS_TAG)
|
// val ifu_axi = new axi_channels(IFU_BUS_TAG)
|
||||||
val sb_axi = new axi_channels(SB_BUS_TAG)
|
// val sb_axi = new axi_channels(SB_BUS_TAG)
|
||||||
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
// val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||||
|
//
|
||||||
val lsu_ahb = new ahb_channel
|
// val lsu_ahb = new ahb_channel
|
||||||
val ifu_ahb = new ahb_channel
|
// val ifu_ahb = new ahb_channel
|
||||||
val sb_ahb = new ahb_channel
|
// val sb_ahb = new ahb_channel
|
||||||
val dma_ahb = new Bundle{
|
// val dma_ahb = new Bundle{
|
||||||
val sig = Flipped(new ahb_channel())
|
// val sig = Flipped(new ahb_channel())
|
||||||
val hsel = Input(Bool())
|
// val hsel = Input(Bool())
|
||||||
val hreadyin = Input(Bool())}
|
// val hreadyin = Input(Bool())}
|
||||||
|
//
|
||||||
val dbg_rst_l = Input(AsyncReset())
|
// val dbg_rst_l = Input(AsyncReset())
|
||||||
val rst_vec = Input(UInt(31.W))
|
// val rst_vec = Input(UInt(31.W))
|
||||||
val nmi_int = Input(Bool())
|
// val nmi_int = Input(Bool())
|
||||||
val nmi_vec = Input(UInt(31.W))
|
// val nmi_vec = Input(UInt(31.W))
|
||||||
val core_rst_l = Output(AsyncReset())
|
// val core_rst_l = Output(AsyncReset())
|
||||||
val rv_trace_pkt = new trace_pkt_t()
|
// val rv_trace_pkt = new trace_pkt_t()
|
||||||
val dccm_clk_override = Output(Bool())
|
// val dccm_clk_override = Output(Bool())
|
||||||
val icm_clk_override = Output(Bool())
|
// val icm_clk_override = Output(Bool())
|
||||||
val dec_tlu_core_ecc_disable = Output(Bool())
|
// val dec_tlu_core_ecc_disable = Output(Bool())
|
||||||
val i_cpu_halt_req = Input(Bool())
|
// val i_cpu_halt_req = Input(Bool())
|
||||||
val i_cpu_run_req = Input(Bool())
|
// val i_cpu_run_req = Input(Bool())
|
||||||
val o_cpu_halt_ack = Output(Bool())
|
// val o_cpu_halt_ack = Output(Bool())
|
||||||
val o_cpu_halt_status = Output(Bool())
|
// val o_cpu_halt_status = Output(Bool())
|
||||||
val o_cpu_run_ack = Output(Bool())
|
// val o_cpu_run_ack = Output(Bool())
|
||||||
val o_debug_mode_status = Output(Bool())
|
// val o_debug_mode_status = Output(Bool())
|
||||||
val core_id = Input(UInt(28.W))
|
// val core_id = Input(UInt(28.W))
|
||||||
val mpc_debug_halt_req = Input(Bool())
|
// val mpc_debug_halt_req = Input(Bool())
|
||||||
val mpc_debug_run_req = Input(Bool())
|
// val mpc_debug_run_req = Input(Bool())
|
||||||
val mpc_reset_run_req = Input(Bool())
|
// val mpc_reset_run_req = Input(Bool())
|
||||||
val mpc_debug_halt_ack = Output(Bool())
|
// val mpc_debug_halt_ack = Output(Bool())
|
||||||
val mpc_debug_run_ack = Output(Bool())
|
// val mpc_debug_run_ack = Output(Bool())
|
||||||
val debug_brkpt_status = Output(Bool())
|
// val debug_brkpt_status = Output(Bool())
|
||||||
val dec_tlu_perfcnt0 = Output(Bool())
|
// val dec_tlu_perfcnt0 = Output(Bool())
|
||||||
val dec_tlu_perfcnt1 = Output(Bool())
|
// val dec_tlu_perfcnt1 = Output(Bool())
|
||||||
val dec_tlu_perfcnt2 = Output(Bool())
|
// val dec_tlu_perfcnt2 = Output(Bool())
|
||||||
val dec_tlu_perfcnt3 = Output(Bool())
|
// val dec_tlu_perfcnt3 = Output(Bool())
|
||||||
val dccm = Flipped(new mem_lsu)
|
// val dccm = Flipped(new mem_lsu)
|
||||||
val ic = new ic_mem()
|
// val ic = new ic_mem()
|
||||||
val iccm = new iccm_mem()
|
// val iccm = new iccm_mem()
|
||||||
|
//
|
||||||
val lsu_bus_clk_en = Input(Bool())
|
// val lsu_bus_clk_en = Input(Bool())
|
||||||
val ifu_bus_clk_en = Input(Bool())
|
// val ifu_bus_clk_en = Input(Bool())
|
||||||
val dbg_bus_clk_en = Input(Bool())
|
// val dbg_bus_clk_en = Input(Bool())
|
||||||
val dma_bus_clk_en = Input(Bool())
|
// val dma_bus_clk_en = Input(Bool())
|
||||||
val dmi_reg_en = Input(Bool())
|
// val dmi_reg_en = Input(Bool())
|
||||||
val dmi_reg_addr = Input(UInt(7.W))
|
// val dmi_reg_addr = Input(UInt(7.W))
|
||||||
val dmi_reg_wr_en = Input(Bool())
|
// val dmi_reg_wr_en = Input(Bool())
|
||||||
val dmi_reg_wdata = Input(UInt(32.W))
|
// val dmi_reg_wdata = Input(UInt(32.W))
|
||||||
val dmi_reg_rdata = Output(UInt(32.W))
|
// val dmi_reg_rdata = Output(UInt(32.W))
|
||||||
val dmi_hard_reset = Input(Bool())
|
// val dmi_hard_reset = Input(Bool())
|
||||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
// val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||||
val timer_int = Input(Bool())
|
// val timer_int = Input(Bool())
|
||||||
val soft_int = Input(Bool())
|
// val soft_int = Input(Bool())
|
||||||
val scan_mode = Input(Bool())
|
// val scan_mode = Input(Bool())
|
||||||
}
|
//}
|
||||||
|
//
|
||||||
class quasar extends Module with RequireAsyncReset with lib {
|
//class quasar extends Module with RequireAsyncReset with lib {
|
||||||
val io = IO (new quasar_bundle)
|
// val io = IO (new quasar_bundle)
|
||||||
|
//
|
||||||
val ifu = Module(new ifu)
|
// val ifu = Module(new ifu)
|
||||||
val dec = Module(new dec)
|
// val dec = Module(new dec)
|
||||||
val dbg = Module(new dbg)
|
// val dbg = Module(new dbg)
|
||||||
val exu = Module(new exu)
|
// val exu = Module(new exu)
|
||||||
val lsu = Module(new lsu)
|
// val lsu = Module(new lsu)
|
||||||
val pic_ctrl_inst = Module(new pic_ctrl)
|
// val pic_ctrl_inst = Module(new pic_ctrl)
|
||||||
val dma_ctrl = Module(new dma_ctrl)
|
// val dma_ctrl = Module(new dma_ctrl)
|
||||||
|
//
|
||||||
io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
|
// io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
|
||||||
val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
// val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
||||||
val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
// val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
||||||
val active_clk = rvclkhdr(clock, active_state.asBool, io.scan_mode)
|
// val active_clk = rvclkhdr(clock, active_state.asBool, io.scan_mode)
|
||||||
|
//
|
||||||
// Lets start with IFU
|
// // Lets start with IFU
|
||||||
ifu.io.ifu_dec <> dec.io.ifu_dec
|
// ifu.io.ifu_dec <> dec.io.ifu_dec
|
||||||
|
//
|
||||||
ifu.reset := io.core_rst_l
|
// ifu.reset := io.core_rst_l
|
||||||
ifu.io.scan_mode := io.scan_mode
|
// ifu.io.scan_mode := io.scan_mode
|
||||||
ifu.io.free_clk := free_clk
|
// ifu.io.free_clk := free_clk
|
||||||
ifu.io.active_clk := active_clk
|
// ifu.io.active_clk := active_clk
|
||||||
|
//
|
||||||
ifu.io.exu_flush_final := dec.io.exu_flush_final
|
// ifu.io.exu_flush_final := dec.io.exu_flush_final
|
||||||
ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
|
// ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
|
||||||
|
//
|
||||||
ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
// ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||||
ifu.io.ifu_dma <> dma_ctrl.io.ifu_dma
|
// ifu.io.ifu_dma <> dma_ctrl.io.ifu_dma
|
||||||
ifu.io.ic <> io.ic
|
// ifu.io.ic <> io.ic
|
||||||
ifu.io.iccm <> io.iccm
|
// ifu.io.iccm <> io.iccm
|
||||||
ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
|
// ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
|
||||||
ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
|
// ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
|
||||||
ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
|
// ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
|
||||||
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
// ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||||
ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
// ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
||||||
|
//
|
||||||
// Lets start with Dec
|
// // Lets start with Dec
|
||||||
dec.reset := io.core_rst_l
|
// dec.reset := io.core_rst_l
|
||||||
dec.io.free_clk := free_clk
|
// dec.io.free_clk := free_clk
|
||||||
dec.io.active_clk := active_clk
|
// dec.io.active_clk := active_clk
|
||||||
dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
|
// dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
|
||||||
dec.io.rst_vec := io.rst_vec
|
// dec.io.rst_vec := io.rst_vec
|
||||||
dec.io.nmi_int := io.nmi_int
|
// dec.io.nmi_int := io.nmi_int
|
||||||
dec.io.nmi_vec := io.nmi_vec
|
// dec.io.nmi_vec := io.nmi_vec
|
||||||
dec.io.i_cpu_halt_req := io.i_cpu_halt_req
|
// dec.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||||
dec.io.i_cpu_run_req := io.i_cpu_run_req
|
// dec.io.i_cpu_run_req := io.i_cpu_run_req
|
||||||
dec.io.core_id := io.core_id
|
// dec.io.core_id := io.core_id
|
||||||
dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
// dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||||
dec.io.mpc_debug_run_req := io.mpc_debug_run_req
|
// dec.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||||
dec.io.mpc_reset_run_req := io.mpc_reset_run_req
|
// dec.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||||
dec.io.lsu_dec <> lsu.io.lsu_dec
|
// dec.io.lsu_dec <> lsu.io.lsu_dec
|
||||||
dec.io.lsu_tlu <> lsu.io.lsu_tlu
|
// dec.io.lsu_tlu <> lsu.io.lsu_tlu
|
||||||
dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
|
// dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
|
||||||
dec.io.dec_dma <> dma_ctrl.io.dec_dma
|
// dec.io.dec_dma <> dma_ctrl.io.dec_dma
|
||||||
|
//
|
||||||
dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
|
// dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
|
||||||
dec.io.lsu_fir_error := lsu.io.lsu_fir_error
|
// dec.io.lsu_fir_error := lsu.io.lsu_fir_error
|
||||||
dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
|
// dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
|
||||||
dec.io.dec_dbg <> dbg.io.dbg_dec
|
// dec.io.dec_dbg <> dbg.io.dbg_dec
|
||||||
dec.io.lsu_idle_any := lsu.io.lsu_idle_any
|
// dec.io.lsu_idle_any := lsu.io.lsu_idle_any
|
||||||
dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
|
// dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
|
||||||
dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
|
// dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
|
||||||
dec.io.exu_div_result := exu.io.exu_div_result
|
// dec.io.exu_div_result := exu.io.exu_div_result
|
||||||
dec.io.exu_div_wren := exu.io.exu_div_wren
|
// dec.io.exu_div_wren := exu.io.exu_div_wren
|
||||||
dec.io.lsu_result_m := lsu.io.lsu_result_m
|
// dec.io.lsu_result_m := lsu.io.lsu_result_m
|
||||||
dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
|
// dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
|
||||||
dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
|
// dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
|
||||||
dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
|
// dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
|
||||||
dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
|
// dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
|
||||||
dec.io.exu_flush_final := exu.io.exu_flush_final
|
// dec.io.exu_flush_final := exu.io.exu_flush_final
|
||||||
|
//
|
||||||
dec.io.soft_int := io.soft_int
|
// dec.io.soft_int := io.soft_int
|
||||||
dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
// dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
||||||
dec.io.dbg_resume_req := dbg.io.dbg_resume_req
|
// dec.io.dbg_resume_req := dbg.io.dbg_resume_req
|
||||||
dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r
|
// dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r
|
||||||
dec.io.timer_int := io.timer_int
|
// dec.io.timer_int := io.timer_int
|
||||||
dec.io.scan_mode := io.scan_mode
|
// dec.io.scan_mode := io.scan_mode
|
||||||
|
//
|
||||||
// EXU lets go
|
// // EXU lets go
|
||||||
dec.io.dec_exu <> exu.io.dec_exu
|
// dec.io.dec_exu <> exu.io.dec_exu
|
||||||
exu.reset := io.core_rst_l
|
// exu.reset := io.core_rst_l
|
||||||
exu.io.scan_mode := io.scan_mode
|
// exu.io.scan_mode := io.scan_mode
|
||||||
exu.io.dbg_cmd_wrdata := dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata
|
// exu.io.dbg_cmd_wrdata := dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata
|
||||||
|
//
|
||||||
// LSU Lets go
|
// // LSU Lets go
|
||||||
lsu.reset := io.core_rst_l
|
// lsu.reset := io.core_rst_l
|
||||||
lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
|
// lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
|
||||||
lsu.io.dec_tlu_flush_lower_r := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
// lsu.io.dec_tlu_flush_lower_r := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||||
lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
|
// lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
|
||||||
lsu.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
// lsu.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
||||||
lsu.io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
// lsu.io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||||
lsu.io.lsu_exu <> exu.io.lsu_exu
|
// lsu.io.lsu_exu <> exu.io.lsu_exu
|
||||||
lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
|
// lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
|
||||||
lsu.io.lsu_p <> dec.io.lsu_p
|
// lsu.io.lsu_p <> dec.io.lsu_p
|
||||||
lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
|
// lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
|
||||||
lsu.io.dec_tlu_mrac_ff := dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff
|
// lsu.io.dec_tlu_mrac_ff := dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff
|
||||||
lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
|
// lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
|
||||||
|
//
|
||||||
lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
// lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
lsu.io.lsu_dma <> dma_ctrl.io.lsu_dma
|
// lsu.io.lsu_dma <> dma_ctrl.io.lsu_dma
|
||||||
lsu.io.scan_mode := io.scan_mode
|
// lsu.io.scan_mode := io.scan_mode
|
||||||
lsu.io.free_clk := free_clk
|
// lsu.io.free_clk := free_clk
|
||||||
|
//
|
||||||
// Debug lets go
|
// // Debug lets go
|
||||||
dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
// dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
||||||
dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
// dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
||||||
dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
// dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
||||||
dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
|
// dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
|
||||||
dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
|
// dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
|
||||||
dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
|
// dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
|
||||||
dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
|
// dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
|
||||||
dbg.io.dmi_reg_en := io.dmi_reg_en
|
// dbg.io.dmi_reg_en := io.dmi_reg_en
|
||||||
dbg.io.dmi_reg_addr := io.dmi_reg_addr
|
// dbg.io.dmi_reg_addr := io.dmi_reg_addr
|
||||||
dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
|
// dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
|
||||||
dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
|
// dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
|
||||||
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
// dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||||
dbg.io.dbg_rst_l := io.dbg_rst_l.asBool()
|
// dbg.io.dbg_rst_l := io.dbg_rst_l.asBool()
|
||||||
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
// dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||||
dbg.io.scan_mode := io.scan_mode
|
// dbg.io.scan_mode := io.scan_mode
|
||||||
|
//
|
||||||
|
//
|
||||||
// DMA Lets go
|
// // DMA Lets go
|
||||||
dma_ctrl.reset := io.core_rst_l
|
// dma_ctrl.reset := io.core_rst_l
|
||||||
dma_ctrl.io.free_clk := free_clk
|
// dma_ctrl.io.free_clk := free_clk
|
||||||
dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
|
// dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||||
dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
// dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||||
dma_ctrl.io.scan_mode := io.scan_mode
|
// dma_ctrl.io.scan_mode := io.scan_mode
|
||||||
dma_ctrl.io.dbg_dma <> dbg.io.dbg_dma
|
// dma_ctrl.io.dbg_dma <> dbg.io.dbg_dma
|
||||||
dma_ctrl.io.dbg_dma_io <> dbg.io.dbg_dma_io
|
// dma_ctrl.io.dbg_dma_io <> dbg.io.dbg_dma_io
|
||||||
dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
|
// dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
|
||||||
dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
|
// dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
|
||||||
dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
|
// dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
|
||||||
dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
|
// dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
|
||||||
dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
|
// dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
|
||||||
dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
|
// dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
|
||||||
|
//
|
||||||
// PIC lets go
|
// // PIC lets go
|
||||||
pic_ctrl_inst.io.scan_mode := io.scan_mode
|
// pic_ctrl_inst.io.scan_mode := io.scan_mode
|
||||||
pic_ctrl_inst.reset := io.core_rst_l
|
// pic_ctrl_inst.reset := io.core_rst_l
|
||||||
pic_ctrl_inst.io.free_clk := free_clk
|
// pic_ctrl_inst.io.free_clk := free_clk
|
||||||
pic_ctrl_inst.io.active_clk := active_clk
|
// pic_ctrl_inst.io.active_clk := active_clk
|
||||||
pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
// pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
||||||
pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
|
// pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
|
||||||
pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
|
// pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
|
||||||
pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
|
// pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
|
||||||
// Trace Packet
|
// // Trace Packet
|
||||||
io.rv_trace_pkt := dec.io.rv_trace_pkt
|
// io.rv_trace_pkt := dec.io.rv_trace_pkt
|
||||||
|
//
|
||||||
// Outputs
|
// // Outputs
|
||||||
io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
|
// io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
|
||||||
io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
|
// io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
|
||||||
io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
// io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||||
io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
|
// io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
|
||||||
io.o_cpu_halt_status := dec.io.o_cpu_halt_status
|
// io.o_cpu_halt_status := dec.io.o_cpu_halt_status
|
||||||
io.o_cpu_run_ack := dec.io.o_cpu_run_ack
|
// io.o_cpu_run_ack := dec.io.o_cpu_run_ack
|
||||||
io.o_debug_mode_status := dec.io.o_debug_mode_status
|
// io.o_debug_mode_status := dec.io.o_debug_mode_status
|
||||||
io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
|
// io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
|
||||||
io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
|
// io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
|
||||||
io.debug_brkpt_status := dec.io.debug_brkpt_status
|
// io.debug_brkpt_status := dec.io.debug_brkpt_status
|
||||||
io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
|
// io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
|
||||||
io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
|
// io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
|
||||||
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
|
// io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
|
||||||
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
|
// io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
|
||||||
io.dmi_reg_rdata := dbg.io.dmi_reg_rdata
|
// io.dmi_reg_rdata := dbg.io.dmi_reg_rdata
|
||||||
|
//
|
||||||
// LSU Outputs
|
// // LSU Outputs
|
||||||
io.dccm <> lsu.io.dccm
|
// io.dccm <> lsu.io.dccm
|
||||||
|
//
|
||||||
if(BUILD_AHB_LITE) {
|
// if(BUILD_AHB_LITE) {
|
||||||
val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG))
|
// val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG))
|
||||||
val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG))
|
// val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG))
|
||||||
val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG))
|
// val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG))
|
||||||
val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG))
|
// val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG))
|
||||||
|
//
|
||||||
lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
// lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||||
lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en
|
// lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en
|
||||||
lsu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
// lsu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||||
lsu_axi4_to_ahb.io.axi <> lsu.io.axi
|
// lsu_axi4_to_ahb.io.axi <> lsu.io.axi
|
||||||
lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb
|
// lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb
|
||||||
|
//
|
||||||
ifu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
// ifu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||||
ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en
|
// ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en
|
||||||
ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
// ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||||
ifu_axi4_to_ahb.io.axi <> ifu.io.ifu
|
// ifu_axi4_to_ahb.io.axi <> ifu.io.ifu
|
||||||
ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb
|
// ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb
|
||||||
ifu_axi4_to_ahb.io.axi.b.ready := true.B
|
// ifu_axi4_to_ahb.io.axi.b.ready := true.B
|
||||||
|
//
|
||||||
sb_axi4_to_ahb.io.scan_mode := io.scan_mode
|
// sb_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||||
sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en
|
// sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en
|
||||||
sb_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
// sb_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||||
sb_axi4_to_ahb.io.axi <> dbg.io.sb_axi
|
// sb_axi4_to_ahb.io.axi <> dbg.io.sb_axi
|
||||||
sb_axi4_to_ahb.io.ahb <> io.sb_ahb
|
// sb_axi4_to_ahb.io.ahb <> io.sb_ahb
|
||||||
|
//
|
||||||
dma_ahb_to_axi4.io.scan_mode := io.scan_mode
|
// dma_ahb_to_axi4.io.scan_mode := io.scan_mode
|
||||||
dma_ahb_to_axi4.io.bus_clk_en := io.dma_bus_clk_en
|
// dma_ahb_to_axi4.io.bus_clk_en := io.dma_bus_clk_en
|
||||||
dma_ahb_to_axi4.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
// dma_ahb_to_axi4.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||||
dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi
|
// dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi
|
||||||
dma_ahb_to_axi4.io.ahb <> io.dma_ahb
|
// dma_ahb_to_axi4.io.ahb <> io.dma_ahb
|
||||||
|
//
|
||||||
io.dma_axi <> 0.U.asTypeOf(io.dma_axi)
|
// io.dma_axi <> 0.U.asTypeOf(io.dma_axi)
|
||||||
io.sb_axi <> 0.U.asTypeOf(io.sb_axi)
|
// io.sb_axi <> 0.U.asTypeOf(io.sb_axi)
|
||||||
io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi)
|
// io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi)
|
||||||
io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi)
|
// io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi)
|
||||||
}
|
// }
|
||||||
else{
|
// else{
|
||||||
io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb)
|
// io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb)
|
||||||
io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb)
|
// io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb)
|
||||||
io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb)
|
// io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb)
|
||||||
io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb)
|
// io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb)
|
||||||
dma_ctrl.io.dma_axi <> io.dma_axi
|
// dma_ctrl.io.dma_axi <> io.dma_axi
|
||||||
dbg.io.sb_axi <> io.sb_axi
|
// dbg.io.sb_axi <> io.sb_axi
|
||||||
ifu.io.ifu <> io.ifu_axi
|
// ifu.io.ifu <> io.ifu_axi
|
||||||
lsu.io.axi <> io.lsu_axi
|
// lsu.io.axi <> io.lsu_axi
|
||||||
}
|
// }
|
||||||
|
//
|
||||||
}
|
//}
|
||||||
//object QUASAR extends App {
|
////object QUASAR extends App {
|
||||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
// // println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||||
//}
|
////}
|
||||||
|
|
@ -1,165 +1,165 @@
|
||||||
import chisel3._
|
//import chisel3._
|
||||||
import mem._
|
//import mem._
|
||||||
import chisel3.util._
|
//import chisel3.util._
|
||||||
import dmi._
|
//import dmi._
|
||||||
import include._
|
//import include._
|
||||||
import lib._
|
//import lib._
|
||||||
class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
//class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
||||||
val io = IO(new Bundle{
|
// val io = IO(new Bundle{
|
||||||
val dbg_rst_l = Input(AsyncReset())
|
// val dbg_rst_l = Input(AsyncReset())
|
||||||
val rst_vec = Input(UInt(31.W))
|
// val rst_vec = Input(UInt(31.W))
|
||||||
val nmi_int = Input(Bool())
|
// val nmi_int = Input(Bool())
|
||||||
val nmi_vec = Input(UInt(31.W))
|
// val nmi_vec = Input(UInt(31.W))
|
||||||
val jtag_id = Input(UInt(31.W))
|
// val jtag_id = Input(UInt(31.W))
|
||||||
|
//
|
||||||
// AXI Signals
|
// // AXI Signals
|
||||||
val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
|
// val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
|
||||||
val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
|
// val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
|
||||||
val sb_brg = bridge_gen(SB_BUS_TAG , false)
|
// val sb_brg = bridge_gen(SB_BUS_TAG , false)
|
||||||
val dma_brg = bridge_gen(DMA_BUS_TAG, true)
|
// val dma_brg = bridge_gen(DMA_BUS_TAG, true)
|
||||||
|
//
|
||||||
val lsu_bus_clk_en = Input(Bool())
|
// val lsu_bus_clk_en = Input(Bool())
|
||||||
val ifu_bus_clk_en = Input(Bool())
|
// val ifu_bus_clk_en = Input(Bool())
|
||||||
val dbg_bus_clk_en = Input(Bool())
|
// val dbg_bus_clk_en = Input(Bool())
|
||||||
val dma_bus_clk_en = Input(Bool())
|
// val dma_bus_clk_en = Input(Bool())
|
||||||
|
//
|
||||||
val timer_int = Input(Bool())
|
// val timer_int = Input(Bool())
|
||||||
val soft_int = Input(Bool())
|
// val soft_int = Input(Bool())
|
||||||
|
//
|
||||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
// val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||||
|
//
|
||||||
val dec_tlu_perfcnt0 = Output(Bool())
|
// val dec_tlu_perfcnt0 = Output(Bool())
|
||||||
val dec_tlu_perfcnt1 = Output(Bool())
|
// val dec_tlu_perfcnt1 = Output(Bool())
|
||||||
val dec_tlu_perfcnt2 = Output(Bool())
|
// val dec_tlu_perfcnt2 = Output(Bool())
|
||||||
val dec_tlu_perfcnt3 = Output(Bool())
|
// val dec_tlu_perfcnt3 = Output(Bool())
|
||||||
|
//
|
||||||
val jtag_tck = Input(Clock())
|
// val jtag_tck = Input(Clock())
|
||||||
val jtag_tms = Input(Bool())
|
// val jtag_tms = Input(Bool())
|
||||||
val jtag_tdi = Input(Bool())
|
// val jtag_tdi = Input(Bool())
|
||||||
val jtag_trst_n = Input(Bool())
|
// val jtag_trst_n = Input(Bool())
|
||||||
val jtag_tdo = Output(Bool())
|
// val jtag_tdo = Output(Bool())
|
||||||
|
//
|
||||||
val core_id = Input(UInt(28.W))
|
// val core_id = Input(UInt(28.W))
|
||||||
|
//
|
||||||
val mpc_debug_halt_req = Input(Bool())
|
// val mpc_debug_halt_req = Input(Bool())
|
||||||
val mpc_debug_run_req = Input(Bool())
|
// val mpc_debug_run_req = Input(Bool())
|
||||||
val mpc_reset_run_req = Input(Bool())
|
// val mpc_reset_run_req = Input(Bool())
|
||||||
val mpc_debug_halt_ack = Output(Bool())
|
// val mpc_debug_halt_ack = Output(Bool())
|
||||||
val mpc_debug_run_ack = Output(Bool())
|
// val mpc_debug_run_ack = Output(Bool())
|
||||||
val debug_brkpt_status = Output(Bool())
|
// val debug_brkpt_status = Output(Bool())
|
||||||
|
//
|
||||||
val i_cpu_halt_req = Input(Bool())
|
// val i_cpu_halt_req = Input(Bool())
|
||||||
val i_cpu_run_req = Input(Bool())
|
// val i_cpu_run_req = Input(Bool())
|
||||||
val o_cpu_halt_ack = Output(Bool())
|
// val o_cpu_halt_ack = Output(Bool())
|
||||||
val o_cpu_halt_status = Output(Bool())
|
// val o_cpu_halt_status = Output(Bool())
|
||||||
val o_debug_mode_status = Output(Bool())
|
// val o_debug_mode_status = Output(Bool())
|
||||||
val o_cpu_run_ack = Output(Bool())
|
// val o_cpu_run_ack = Output(Bool())
|
||||||
val mbist_mode = Input(Bool())
|
// val mbist_mode = Input(Bool())
|
||||||
|
//
|
||||||
val rv_trace_pkt = new trace_pkt_t()
|
// val rv_trace_pkt = new trace_pkt_t()
|
||||||
val scan_mode = Input(Bool())
|
// val scan_mode = Input(Bool())
|
||||||
|
//
|
||||||
})
|
// })
|
||||||
val mem = Module(new quasar.mem())
|
// val mem = Module(new quasar.mem())
|
||||||
val dmi_wrapper = Module(new dmi_wrapper())
|
// val dmi_wrapper = Module(new dmi_wrapper())
|
||||||
val core = Module(new quasar())
|
// val core = Module(new quasar())
|
||||||
core.io.scan_mode := io.scan_mode
|
// core.io.scan_mode := io.scan_mode
|
||||||
dmi_wrapper.io.trst_n := io.jtag_trst_n
|
// dmi_wrapper.io.trst_n := io.jtag_trst_n
|
||||||
dmi_wrapper.io.tck := io.jtag_tck
|
// dmi_wrapper.io.tck := io.jtag_tck
|
||||||
dmi_wrapper.io.tms := io.jtag_tms
|
// dmi_wrapper.io.tms := io.jtag_tms
|
||||||
dmi_wrapper.io.tdi := io.jtag_tdi
|
// dmi_wrapper.io.tdi := io.jtag_tdi
|
||||||
dmi_wrapper.io.core_clk := clock
|
// dmi_wrapper.io.core_clk := clock
|
||||||
dmi_wrapper.io.jtag_id := io.jtag_id
|
// dmi_wrapper.io.jtag_id := io.jtag_id
|
||||||
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
|
// dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
|
||||||
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
|
// dmi_wrapper.io.core_rst_n := io.dbg_rst_l
|
||||||
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
|
// core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
|
||||||
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
|
// core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
|
||||||
core.io.dmi_reg_en := dmi_wrapper.io.reg_en
|
// core.io.dmi_reg_en := dmi_wrapper.io.reg_en
|
||||||
core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
|
// core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
|
||||||
core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
|
// core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
|
||||||
io.jtag_tdo := dmi_wrapper.io.tdo
|
// io.jtag_tdo := dmi_wrapper.io.tdo
|
||||||
|
//
|
||||||
// Memory signals
|
// // Memory signals
|
||||||
mem.io.dccm_clk_override := core.io.dccm_clk_override
|
// mem.io.dccm_clk_override := core.io.dccm_clk_override
|
||||||
mem.io.icm_clk_override := core.io.icm_clk_override
|
// mem.io.icm_clk_override := core.io.icm_clk_override
|
||||||
mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
|
// mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
|
||||||
mem.io.dccm <> core.io.dccm
|
// mem.io.dccm <> core.io.dccm
|
||||||
mem.io.rst_l := reset
|
// mem.io.rst_l := reset
|
||||||
mem.io.clk := clock
|
// mem.io.clk := clock
|
||||||
mem.io.scan_mode := io.scan_mode
|
// mem.io.scan_mode := io.scan_mode
|
||||||
// Memory outputs
|
// // Memory outputs
|
||||||
core.io.dbg_rst_l := io.dbg_rst_l
|
// core.io.dbg_rst_l := io.dbg_rst_l
|
||||||
core.io.ic <> mem.io.ic
|
// core.io.ic <> mem.io.ic
|
||||||
core.io.iccm <> mem.io.iccm
|
// core.io.iccm <> mem.io.iccm
|
||||||
|
//
|
||||||
|
//
|
||||||
if(BUILD_AXI4) {
|
// if(BUILD_AXI4) {
|
||||||
core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb)
|
// core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb)
|
||||||
core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
|
// core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
|
||||||
core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
|
// core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
|
||||||
core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb)
|
// core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb)
|
||||||
|
//
|
||||||
core.io.lsu_axi <> io.lsu_brg
|
// core.io.lsu_axi <> io.lsu_brg
|
||||||
core.io.ifu_axi <> io.ifu_brg
|
// core.io.ifu_axi <> io.ifu_brg
|
||||||
core.io.sb_axi <> io.sb_brg
|
// core.io.sb_axi <> io.sb_brg
|
||||||
core.io.dma_axi <> io.dma_brg
|
// core.io.dma_axi <> io.dma_brg
|
||||||
}
|
// }
|
||||||
else {
|
// else {
|
||||||
core.io.ifu_ahb <> io.ifu_brg
|
// core.io.ifu_ahb <> io.ifu_brg
|
||||||
core.io.lsu_ahb <> io.lsu_brg
|
// core.io.lsu_ahb <> io.lsu_brg
|
||||||
core.io.sb_ahb <> io.sb_brg
|
// core.io.sb_ahb <> io.sb_brg
|
||||||
core.io.dma_ahb <> io.dma_brg
|
// core.io.dma_ahb <> io.dma_brg
|
||||||
|
//
|
||||||
core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
|
// core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
|
||||||
core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
|
// core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
|
||||||
core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
|
// core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
|
||||||
core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
|
// core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
|
||||||
}
|
// }
|
||||||
// core Inputs
|
// // core Inputs
|
||||||
core.io.dbg_rst_l := io.dbg_rst_l
|
// core.io.dbg_rst_l := io.dbg_rst_l
|
||||||
core.io.rst_vec := io.rst_vec
|
// core.io.rst_vec := io.rst_vec
|
||||||
core.io.nmi_int := io.nmi_int
|
// core.io.nmi_int := io.nmi_int
|
||||||
core.io.nmi_vec := io.nmi_vec
|
// core.io.nmi_vec := io.nmi_vec
|
||||||
|
//
|
||||||
// external halt/run interface
|
// // external halt/run interface
|
||||||
core.io.i_cpu_halt_req := io.i_cpu_halt_req
|
// core.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||||
core.io.i_cpu_run_req := io.i_cpu_run_req
|
// core.io.i_cpu_run_req := io.i_cpu_run_req
|
||||||
core.io.core_id := io.core_id
|
// core.io.core_id := io.core_id
|
||||||
|
//
|
||||||
// external MPC halt/run interface
|
// // external MPC halt/run interface
|
||||||
core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
// core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||||
core.io.mpc_debug_run_req := io.mpc_debug_run_req
|
// core.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||||
core.io.mpc_reset_run_req := io.mpc_reset_run_req
|
// core.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||||
|
//
|
||||||
core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
// core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
// core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||||
core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
// core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||||
core.io.dma_bus_clk_en := io.dma_bus_clk_en
|
// core.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||||
|
//
|
||||||
core.io.timer_int := io.timer_int
|
// core.io.timer_int := io.timer_int
|
||||||
core.io.soft_int := io.soft_int
|
// core.io.soft_int := io.soft_int
|
||||||
core.io.extintsrc_req := io.extintsrc_req
|
// core.io.extintsrc_req := io.extintsrc_req
|
||||||
|
//
|
||||||
// Outputs
|
// // Outputs
|
||||||
val core_rst_l = core.io.core_rst_l
|
// val core_rst_l = core.io.core_rst_l
|
||||||
io.rv_trace_pkt <> core.io.rv_trace_pkt
|
// io.rv_trace_pkt <> core.io.rv_trace_pkt
|
||||||
|
//
|
||||||
// external halt/run interface
|
// // external halt/run interface
|
||||||
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
|
// io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
|
||||||
io.o_cpu_halt_status := core.io.o_cpu_halt_status
|
// io.o_cpu_halt_status := core.io.o_cpu_halt_status
|
||||||
io.o_cpu_run_ack := core.io.o_cpu_run_ack
|
// io.o_cpu_run_ack := core.io.o_cpu_run_ack
|
||||||
io.o_debug_mode_status := core.io.o_debug_mode_status
|
// io.o_debug_mode_status := core.io.o_debug_mode_status
|
||||||
|
//
|
||||||
io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
|
// io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
|
||||||
io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
|
// io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
|
||||||
io.debug_brkpt_status := core.io.debug_brkpt_status
|
// io.debug_brkpt_status := core.io.debug_brkpt_status
|
||||||
|
//
|
||||||
io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
|
// io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
|
||||||
io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
|
// io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
|
||||||
io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
|
// io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
|
||||||
io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
|
// io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
|
||||||
|
//
|
||||||
}
|
//}
|
||||||
object QUASAR_Wrp extends App {
|
//object QUASAR_Wrp extends App {
|
||||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
|
// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
|
||||||
}
|
//}
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue