ICCM Flop done
This commit is contained in:
waleed-lm
parent
7ba865dcba
commit
e55b14d62a
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@ -1,30 +1,38 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_1",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_2",
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"sources":[
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_0",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_3",
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"sources":[
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_2",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_1",
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"sources":[
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_3",
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"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_0",
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"sources":[
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
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"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
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]
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},
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{
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@ -3,7 +3,7 @@ circuit el2_ifu_iccm_mem :
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module el2_ifu_iccm_mem :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_wr_data : UInt<39>[4]}
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_addr : UInt[4]}
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io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
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io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
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@ -47,10 +47,6 @@ circuit el2_ifu_iccm_mem :
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node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64]
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io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 35:24]
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node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:99]
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node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 36:64]
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@ -192,423 +188,446 @@ circuit el2_ifu_iccm_mem :
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when write_vec[3] :
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_T_96[3] <= iccm_bank_wr_data[3]
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skip
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read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:25]
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inter[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 49:9]
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inter[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 49:9]
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inter[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 49:9]
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inter[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 49:9]
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reg _T_98 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_98 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[0] <= _T_98 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_99 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_99 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[1] <= _T_99 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_100 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_100 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[2] <= _T_100 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_101 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_101 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[3] <= _T_101 @[el2_ifu_iccm_mem.scala 50:52]
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node _T_97 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15]
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node _T_98 = mux(_T_97, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_99 = iccm_mem[UInt<1>("h00")], clock @[el2_ifu_iccm_mem.scala 49:77]
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node _T_100 = bits(addr_bank_0, 1, 0)
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node _T_101 = and(_T_98, _T_99[_T_100]) @[el2_ifu_iccm_mem.scala 49:67]
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node _T_102 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15]
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node _T_103 = mux(_T_102, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_104 = iccm_mem[UInt<1>("h01")], clock @[el2_ifu_iccm_mem.scala 49:77]
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node _T_105 = bits(addr_bank_1, 1, 0)
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node _T_106 = and(_T_103, _T_104[_T_105]) @[el2_ifu_iccm_mem.scala 49:67]
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node _T_107 = bits(read_enable[2], 0, 0) @[Bitwise.scala 72:15]
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node _T_108 = mux(_T_107, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_109 = iccm_mem[UInt<2>("h02")], clock @[el2_ifu_iccm_mem.scala 49:77]
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node _T_110 = bits(addr_bank_2, 1, 0)
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node _T_111 = and(_T_108, _T_109[_T_110]) @[el2_ifu_iccm_mem.scala 49:67]
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node _T_112 = bits(read_enable[3], 0, 0) @[Bitwise.scala 72:15]
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node _T_113 = mux(_T_112, UInt<39>("h07fffffffff"), UInt<39>("h00")) @[Bitwise.scala 72:12]
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infer mport _T_114 = iccm_mem[UInt<2>("h03")], clock @[el2_ifu_iccm_mem.scala 49:77]
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node _T_115 = bits(addr_bank_3, 1, 0)
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node _T_116 = and(_T_113, _T_114[_T_115]) @[el2_ifu_iccm_mem.scala 49:67]
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inter[0] <= _T_101 @[el2_ifu_iccm_mem.scala 49:9]
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inter[1] <= _T_106 @[el2_ifu_iccm_mem.scala 49:9]
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inter[2] <= _T_111 @[el2_ifu_iccm_mem.scala 49:9]
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inter[3] <= _T_116 @[el2_ifu_iccm_mem.scala 49:9]
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reg _T_117 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_117 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[0] <= _T_117 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_118 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_118 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[1] <= _T_118 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_119 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_119 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[2] <= _T_119 @[el2_ifu_iccm_mem.scala 50:52]
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reg _T_120 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
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_T_120 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62]
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iccm_bank_dout[3] <= _T_120 @[el2_ifu_iccm_mem.scala 50:52]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 52:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 52:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 52:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 52:21]
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wire redundant_valid : UInt<2>
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redundant_valid <= UInt<1>("h00")
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 53:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
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node _T_102 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
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node _T_103 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
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node _T_104 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
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node _T_105 = eq(_T_103, _T_104) @[el2_ifu_iccm_mem.scala 56:105]
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node _T_106 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
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node _T_107 = eq(_T_106, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:169]
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node _T_108 = and(_T_105, _T_107) @[el2_ifu_iccm_mem.scala 56:145]
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node _T_109 = and(_T_102, _T_108) @[el2_ifu_iccm_mem.scala 56:71]
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node _T_110 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
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node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
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node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 57:37]
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node _T_113 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
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node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 57:99]
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node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 57:77]
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node _T_116 = or(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 56:179]
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node _T_117 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
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node _T_118 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
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node _T_119 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
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node _T_120 = eq(_T_118, _T_119) @[el2_ifu_iccm_mem.scala 56:105]
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node _T_121 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
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node _T_122 = eq(_T_121, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:169]
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node _T_123 = and(_T_120, _T_122) @[el2_ifu_iccm_mem.scala 56:145]
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node _T_124 = and(_T_117, _T_123) @[el2_ifu_iccm_mem.scala 56:71]
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node _T_125 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
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node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
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node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 57:37]
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node _T_128 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
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node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 57:99]
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node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 57:77]
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node _T_131 = or(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 56:179]
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node _T_132 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
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node _T_133 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
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node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
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node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 56:105]
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node _T_136 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
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node _T_137 = eq(_T_136, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:169]
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node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 56:145]
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node _T_139 = and(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 56:71]
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node _T_140 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
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node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
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node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 57:37]
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node _T_143 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
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node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 57:99]
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node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 57:77]
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node _T_146 = or(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 56:179]
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node _T_147 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
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node _T_148 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
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node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
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node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 56:105]
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node _T_151 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
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node _T_152 = eq(_T_151, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:169]
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node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 56:145]
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node _T_154 = and(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 56:71]
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node _T_155 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
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node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
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node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 57:37]
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node _T_158 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
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node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 57:99]
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node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 57:77]
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node _T_161 = or(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 56:179]
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node _T_162 = cat(_T_161, _T_146) @[Cat.scala 29:58]
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node _T_163 = cat(_T_162, _T_131) @[Cat.scala 29:58]
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node sel_red1 = cat(_T_163, _T_116) @[Cat.scala 29:58]
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node _T_164 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
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node _T_165 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
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node _T_166 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
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node _T_167 = eq(_T_165, _T_166) @[el2_ifu_iccm_mem.scala 58:105]
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node _T_168 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
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node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 58:169]
|
||||
node _T_170 = and(_T_167, _T_169) @[el2_ifu_iccm_mem.scala 58:145]
|
||||
node _T_171 = and(_T_164, _T_170) @[el2_ifu_iccm_mem.scala 58:71]
|
||||
node _T_172 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
||||
node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
||||
node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 59:37]
|
||||
node _T_175 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
||||
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 59:99]
|
||||
node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 59:77]
|
||||
node _T_178 = or(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 58:179]
|
||||
node _T_179 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
||||
node _T_180 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
||||
node _T_181 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
||||
node _T_182 = eq(_T_180, _T_181) @[el2_ifu_iccm_mem.scala 58:105]
|
||||
node _T_183 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
||||
node _T_184 = eq(_T_183, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 58:169]
|
||||
node _T_185 = and(_T_182, _T_184) @[el2_ifu_iccm_mem.scala 58:145]
|
||||
node _T_186 = and(_T_179, _T_185) @[el2_ifu_iccm_mem.scala 58:71]
|
||||
node _T_187 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
||||
node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
||||
node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 59:37]
|
||||
node _T_190 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
||||
node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 59:99]
|
||||
node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 59:77]
|
||||
node _T_193 = or(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 58:179]
|
||||
node _T_194 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
||||
node _T_195 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
||||
node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
||||
node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 58:105]
|
||||
node _T_198 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
||||
node _T_199 = eq(_T_198, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 58:169]
|
||||
node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 58:145]
|
||||
node _T_201 = and(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 58:71]
|
||||
node _T_202 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
||||
node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
||||
node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 59:37]
|
||||
node _T_205 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
||||
node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 59:99]
|
||||
node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 59:77]
|
||||
node _T_208 = or(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 58:179]
|
||||
node _T_209 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
||||
node _T_210 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
||||
node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
||||
node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 58:105]
|
||||
node _T_213 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
||||
node _T_214 = eq(_T_213, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 58:169]
|
||||
node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 58:145]
|
||||
node _T_216 = and(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 58:71]
|
||||
node _T_217 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
||||
node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
||||
node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 59:37]
|
||||
node _T_220 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
||||
node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 59:99]
|
||||
node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 59:77]
|
||||
node _T_223 = or(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 58:179]
|
||||
node _T_224 = cat(_T_223, _T_208) @[Cat.scala 29:58]
|
||||
node _T_225 = cat(_T_224, _T_193) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_225, _T_178) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 61:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 61:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 62:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 62:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 63:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
|
||||
node _T_226 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 66:47]
|
||||
node _T_227 = bits(_T_226, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
||||
node _T_228 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 67:47]
|
||||
node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
||||
node _T_230 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:47]
|
||||
node _T_231 = not(_T_230) @[el2_ifu_iccm_mem.scala 68:36]
|
||||
node _T_232 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:64]
|
||||
node _T_233 = not(_T_232) @[el2_ifu_iccm_mem.scala 68:53]
|
||||
node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 68:51]
|
||||
node _T_235 = bits(_T_234, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
||||
node _T_236 = mux(_T_227, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_237 = mux(_T_229, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_238 = mux(_T_235, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_239 = or(_T_236, _T_237) @[Mux.scala 27:72]
|
||||
node _T_240 = or(_T_239, _T_238) @[Mux.scala 27:72]
|
||||
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 58:31]
|
||||
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 59:21]
|
||||
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 59:21]
|
||||
node _T_121 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67]
|
||||
node _T_122 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90]
|
||||
node _T_123 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128]
|
||||
node _T_124 = eq(_T_122, _T_123) @[el2_ifu_iccm_mem.scala 61:105]
|
||||
node _T_125 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163]
|
||||
node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 61:169]
|
||||
node _T_127 = and(_T_124, _T_126) @[el2_ifu_iccm_mem.scala 61:145]
|
||||
node _T_128 = and(_T_121, _T_127) @[el2_ifu_iccm_mem.scala 61:71]
|
||||
node _T_129 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22]
|
||||
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60]
|
||||
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 62:37]
|
||||
node _T_132 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93]
|
||||
node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 62:99]
|
||||
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 62:77]
|
||||
node _T_135 = or(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 61:179]
|
||||
node _T_136 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67]
|
||||
node _T_137 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90]
|
||||
node _T_138 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128]
|
||||
node _T_139 = eq(_T_137, _T_138) @[el2_ifu_iccm_mem.scala 61:105]
|
||||
node _T_140 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163]
|
||||
node _T_141 = eq(_T_140, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 61:169]
|
||||
node _T_142 = and(_T_139, _T_141) @[el2_ifu_iccm_mem.scala 61:145]
|
||||
node _T_143 = and(_T_136, _T_142) @[el2_ifu_iccm_mem.scala 61:71]
|
||||
node _T_144 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22]
|
||||
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60]
|
||||
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 62:37]
|
||||
node _T_147 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93]
|
||||
node _T_148 = eq(_T_147, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 62:99]
|
||||
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 62:77]
|
||||
node _T_150 = or(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 61:179]
|
||||
node _T_151 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67]
|
||||
node _T_152 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90]
|
||||
node _T_153 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128]
|
||||
node _T_154 = eq(_T_152, _T_153) @[el2_ifu_iccm_mem.scala 61:105]
|
||||
node _T_155 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163]
|
||||
node _T_156 = eq(_T_155, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 61:169]
|
||||
node _T_157 = and(_T_154, _T_156) @[el2_ifu_iccm_mem.scala 61:145]
|
||||
node _T_158 = and(_T_151, _T_157) @[el2_ifu_iccm_mem.scala 61:71]
|
||||
node _T_159 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22]
|
||||
node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60]
|
||||
node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 62:37]
|
||||
node _T_162 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93]
|
||||
node _T_163 = eq(_T_162, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 62:99]
|
||||
node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 62:77]
|
||||
node _T_165 = or(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 61:179]
|
||||
node _T_166 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 61:67]
|
||||
node _T_167 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 61:90]
|
||||
node _T_168 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 61:128]
|
||||
node _T_169 = eq(_T_167, _T_168) @[el2_ifu_iccm_mem.scala 61:105]
|
||||
node _T_170 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 61:163]
|
||||
node _T_171 = eq(_T_170, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 61:169]
|
||||
node _T_172 = and(_T_169, _T_171) @[el2_ifu_iccm_mem.scala 61:145]
|
||||
node _T_173 = and(_T_166, _T_172) @[el2_ifu_iccm_mem.scala 61:71]
|
||||
node _T_174 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 62:22]
|
||||
node _T_175 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 62:60]
|
||||
node _T_176 = eq(_T_174, _T_175) @[el2_ifu_iccm_mem.scala 62:37]
|
||||
node _T_177 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 62:93]
|
||||
node _T_178 = eq(_T_177, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 62:99]
|
||||
node _T_179 = and(_T_176, _T_178) @[el2_ifu_iccm_mem.scala 62:77]
|
||||
node _T_180 = or(_T_173, _T_179) @[el2_ifu_iccm_mem.scala 61:179]
|
||||
node _T_181 = cat(_T_180, _T_165) @[Cat.scala 29:58]
|
||||
node _T_182 = cat(_T_181, _T_150) @[Cat.scala 29:58]
|
||||
node sel_red1 = cat(_T_182, _T_135) @[Cat.scala 29:58]
|
||||
node _T_183 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67]
|
||||
node _T_184 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
|
||||
node _T_185 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
|
||||
node _T_186 = eq(_T_184, _T_185) @[el2_ifu_iccm_mem.scala 63:105]
|
||||
node _T_187 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
|
||||
node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 63:169]
|
||||
node _T_189 = and(_T_186, _T_188) @[el2_ifu_iccm_mem.scala 63:145]
|
||||
node _T_190 = and(_T_183, _T_189) @[el2_ifu_iccm_mem.scala 63:71]
|
||||
node _T_191 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
|
||||
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
|
||||
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 64:37]
|
||||
node _T_194 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
|
||||
node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 64:99]
|
||||
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 64:77]
|
||||
node _T_197 = or(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 63:179]
|
||||
node _T_198 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67]
|
||||
node _T_199 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
|
||||
node _T_200 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
|
||||
node _T_201 = eq(_T_199, _T_200) @[el2_ifu_iccm_mem.scala 63:105]
|
||||
node _T_202 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
|
||||
node _T_203 = eq(_T_202, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 63:169]
|
||||
node _T_204 = and(_T_201, _T_203) @[el2_ifu_iccm_mem.scala 63:145]
|
||||
node _T_205 = and(_T_198, _T_204) @[el2_ifu_iccm_mem.scala 63:71]
|
||||
node _T_206 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
|
||||
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
|
||||
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 64:37]
|
||||
node _T_209 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
|
||||
node _T_210 = eq(_T_209, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 64:99]
|
||||
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 64:77]
|
||||
node _T_212 = or(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 63:179]
|
||||
node _T_213 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67]
|
||||
node _T_214 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
|
||||
node _T_215 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
|
||||
node _T_216 = eq(_T_214, _T_215) @[el2_ifu_iccm_mem.scala 63:105]
|
||||
node _T_217 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
|
||||
node _T_218 = eq(_T_217, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 63:169]
|
||||
node _T_219 = and(_T_216, _T_218) @[el2_ifu_iccm_mem.scala 63:145]
|
||||
node _T_220 = and(_T_213, _T_219) @[el2_ifu_iccm_mem.scala 63:71]
|
||||
node _T_221 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
|
||||
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
|
||||
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 64:37]
|
||||
node _T_224 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
|
||||
node _T_225 = eq(_T_224, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 64:99]
|
||||
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 64:77]
|
||||
node _T_227 = or(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 63:179]
|
||||
node _T_228 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 63:67]
|
||||
node _T_229 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 63:90]
|
||||
node _T_230 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 63:128]
|
||||
node _T_231 = eq(_T_229, _T_230) @[el2_ifu_iccm_mem.scala 63:105]
|
||||
node _T_232 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 63:163]
|
||||
node _T_233 = eq(_T_232, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 63:169]
|
||||
node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 63:145]
|
||||
node _T_235 = and(_T_228, _T_234) @[el2_ifu_iccm_mem.scala 63:71]
|
||||
node _T_236 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 64:22]
|
||||
node _T_237 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 64:60]
|
||||
node _T_238 = eq(_T_236, _T_237) @[el2_ifu_iccm_mem.scala 64:37]
|
||||
node _T_239 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 64:93]
|
||||
node _T_240 = eq(_T_239, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 64:99]
|
||||
node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 64:77]
|
||||
node _T_242 = or(_T_235, _T_241) @[el2_ifu_iccm_mem.scala 63:179]
|
||||
node _T_243 = cat(_T_242, _T_227) @[Cat.scala 29:58]
|
||||
node _T_244 = cat(_T_243, _T_212) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_244, _T_197) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 66:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 66:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 67:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 67:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 68:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 69:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 69:18]
|
||||
node _T_245 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 71:47]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 71:51]
|
||||
node _T_247 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 72:47]
|
||||
node _T_248 = bits(_T_247, 0, 0) @[el2_ifu_iccm_mem.scala 72:51]
|
||||
node _T_249 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_250 = not(_T_249) @[el2_ifu_iccm_mem.scala 73:36]
|
||||
node _T_251 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 73:64]
|
||||
node _T_252 = not(_T_251) @[el2_ifu_iccm_mem.scala 73:53]
|
||||
node _T_253 = and(_T_250, _T_252) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_iccm_mem.scala 73:69]
|
||||
node _T_255 = mux(_T_246, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_256 = mux(_T_248, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_257 = mux(_T_254, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72]
|
||||
node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_240 @[Mux.scala 27:72]
|
||||
node _T_241 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 66:47]
|
||||
node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
||||
node _T_243 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 67:47]
|
||||
node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
||||
node _T_245 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:47]
|
||||
node _T_246 = not(_T_245) @[el2_ifu_iccm_mem.scala 68:36]
|
||||
node _T_247 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:64]
|
||||
node _T_248 = not(_T_247) @[el2_ifu_iccm_mem.scala 68:53]
|
||||
node _T_249 = and(_T_246, _T_248) @[el2_ifu_iccm_mem.scala 68:51]
|
||||
node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
||||
node _T_251 = mux(_T_242, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_252 = mux(_T_244, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_253 = mux(_T_250, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_254 = or(_T_251, _T_252) @[Mux.scala 27:72]
|
||||
node _T_255 = or(_T_254, _T_253) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_259 @[Mux.scala 27:72]
|
||||
node _T_260 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 71:47]
|
||||
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 71:51]
|
||||
node _T_262 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 72:47]
|
||||
node _T_263 = bits(_T_262, 0, 0) @[el2_ifu_iccm_mem.scala 72:51]
|
||||
node _T_264 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_265 = not(_T_264) @[el2_ifu_iccm_mem.scala 73:36]
|
||||
node _T_266 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 73:64]
|
||||
node _T_267 = not(_T_266) @[el2_ifu_iccm_mem.scala 73:53]
|
||||
node _T_268 = and(_T_265, _T_267) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_iccm_mem.scala 73:69]
|
||||
node _T_270 = mux(_T_261, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_271 = mux(_T_263, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_272 = mux(_T_269, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_273 = or(_T_270, _T_271) @[Mux.scala 27:72]
|
||||
node _T_274 = or(_T_273, _T_272) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_255 @[Mux.scala 27:72]
|
||||
node _T_256 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 66:47]
|
||||
node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
||||
node _T_258 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 67:47]
|
||||
node _T_259 = bits(_T_258, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
||||
node _T_260 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:47]
|
||||
node _T_261 = not(_T_260) @[el2_ifu_iccm_mem.scala 68:36]
|
||||
node _T_262 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:64]
|
||||
node _T_263 = not(_T_262) @[el2_ifu_iccm_mem.scala 68:53]
|
||||
node _T_264 = and(_T_261, _T_263) @[el2_ifu_iccm_mem.scala 68:51]
|
||||
node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
||||
node _T_266 = mux(_T_257, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_267 = mux(_T_259, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_268 = mux(_T_265, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_269 = or(_T_266, _T_267) @[Mux.scala 27:72]
|
||||
node _T_270 = or(_T_269, _T_268) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_274 @[Mux.scala 27:72]
|
||||
node _T_275 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 71:47]
|
||||
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 71:51]
|
||||
node _T_277 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 72:47]
|
||||
node _T_278 = bits(_T_277, 0, 0) @[el2_ifu_iccm_mem.scala 72:51]
|
||||
node _T_279 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_280 = not(_T_279) @[el2_ifu_iccm_mem.scala 73:36]
|
||||
node _T_281 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 73:64]
|
||||
node _T_282 = not(_T_281) @[el2_ifu_iccm_mem.scala 73:53]
|
||||
node _T_283 = and(_T_280, _T_282) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_284 = bits(_T_283, 0, 0) @[el2_ifu_iccm_mem.scala 73:69]
|
||||
node _T_285 = mux(_T_276, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_286 = mux(_T_278, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_287 = mux(_T_284, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_288 = or(_T_285, _T_286) @[Mux.scala 27:72]
|
||||
node _T_289 = or(_T_288, _T_287) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_270 @[Mux.scala 27:72]
|
||||
node _T_271 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 66:47]
|
||||
node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
||||
node _T_273 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 67:47]
|
||||
node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
||||
node _T_275 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:47]
|
||||
node _T_276 = not(_T_275) @[el2_ifu_iccm_mem.scala 68:36]
|
||||
node _T_277 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:64]
|
||||
node _T_278 = not(_T_277) @[el2_ifu_iccm_mem.scala 68:53]
|
||||
node _T_279 = and(_T_276, _T_278) @[el2_ifu_iccm_mem.scala 68:51]
|
||||
node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
||||
node _T_281 = mux(_T_272, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_282 = mux(_T_274, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_283 = mux(_T_280, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_284 = or(_T_281, _T_282) @[Mux.scala 27:72]
|
||||
node _T_285 = or(_T_284, _T_283) @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_289 @[Mux.scala 27:72]
|
||||
node _T_290 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 71:47]
|
||||
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 71:51]
|
||||
node _T_292 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 72:47]
|
||||
node _T_293 = bits(_T_292, 0, 0) @[el2_ifu_iccm_mem.scala 72:51]
|
||||
node _T_294 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:47]
|
||||
node _T_295 = not(_T_294) @[el2_ifu_iccm_mem.scala 73:36]
|
||||
node _T_296 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 73:64]
|
||||
node _T_297 = not(_T_296) @[el2_ifu_iccm_mem.scala 73:53]
|
||||
node _T_298 = and(_T_295, _T_297) @[el2_ifu_iccm_mem.scala 73:51]
|
||||
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_iccm_mem.scala 73:69]
|
||||
node _T_300 = mux(_T_291, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_301 = mux(_T_293, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_302 = mux(_T_299, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_303 = or(_T_300, _T_301) @[Mux.scala 27:72]
|
||||
node _T_304 = or(_T_303, _T_302) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_285 @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_3 <= _T_304 @[Mux.scala 27:72]
|
||||
wire redundant_lru : UInt<1>
|
||||
redundant_lru <= UInt<1>("h00")
|
||||
node _T_286 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:20]
|
||||
node r0_addr_en = and(_T_286, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 70:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 71:35]
|
||||
node _T_287 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 72:63]
|
||||
node _T_288 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 72:78]
|
||||
node _T_289 = or(_T_287, _T_288) @[el2_ifu_iccm_mem.scala 72:67]
|
||||
node _T_290 = and(_T_289, io.iccm_rden) @[el2_ifu_iccm_mem.scala 72:83]
|
||||
node _T_291 = and(_T_290, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 72:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_291) @[el2_ifu_iccm_mem.scala 72:50]
|
||||
node _T_292 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:55]
|
||||
node _T_293 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 73:84]
|
||||
node _T_294 = mux(_T_293, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_292, _T_294) @[el2_ifu_iccm_mem.scala 73:29]
|
||||
reg _T_295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
node _T_305 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 75:20]
|
||||
node r0_addr_en = and(_T_305, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 75:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 76:35]
|
||||
node _T_306 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 77:63]
|
||||
node _T_307 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 77:78]
|
||||
node _T_308 = or(_T_306, _T_307) @[el2_ifu_iccm_mem.scala 77:67]
|
||||
node _T_309 = and(_T_308, io.iccm_rden) @[el2_ifu_iccm_mem.scala 77:83]
|
||||
node _T_310 = and(_T_309, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 77:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_310) @[el2_ifu_iccm_mem.scala 77:50]
|
||||
node _T_311 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:55]
|
||||
node _T_312 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 78:84]
|
||||
node _T_313 = mux(_T_312, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_311, _T_313) @[el2_ifu_iccm_mem.scala 78:29]
|
||||
reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when redundant_lru_en : @[Reg.scala 28:19]
|
||||
_T_295 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
_T_314 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_lru <= _T_295 @[el2_ifu_iccm_mem.scala 74:17]
|
||||
node _T_296 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 75:52]
|
||||
reg _T_297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
redundant_lru <= _T_314 @[el2_ifu_iccm_mem.scala 79:17]
|
||||
node _T_315 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 80:52]
|
||||
reg _T_316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_297 <= _T_296 @[Reg.scala 28:23]
|
||||
_T_316 <= _T_315 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[0] <= _T_297 @[el2_ifu_iccm_mem.scala 75:24]
|
||||
node _T_298 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 76:52]
|
||||
node _T_299 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 76:85]
|
||||
reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_299 : @[Reg.scala 28:19]
|
||||
_T_300 <= _T_298 @[Reg.scala 28:23]
|
||||
redundant_address[0] <= _T_316 @[el2_ifu_iccm_mem.scala 80:24]
|
||||
node _T_317 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 81:52]
|
||||
node _T_318 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 81:85]
|
||||
reg _T_319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_318 : @[Reg.scala 28:19]
|
||||
_T_319 <= _T_317 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[1] <= _T_300 @[el2_ifu_iccm_mem.scala 76:24]
|
||||
node _T_301 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 77:57]
|
||||
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_301 : @[Reg.scala 28:19]
|
||||
_T_302 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
redundant_address[1] <= _T_319 @[el2_ifu_iccm_mem.scala 81:24]
|
||||
node _T_320 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 82:57]
|
||||
reg _T_321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_320 : @[Reg.scala 28:19]
|
||||
_T_321 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
reg _T_303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
reg _T_322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_303 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
_T_322 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_304 = cat(_T_302, _T_303) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_304 @[el2_ifu_iccm_mem.scala 77:19]
|
||||
node _T_305 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 79:45]
|
||||
node _T_306 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 79:85]
|
||||
node _T_307 = eq(_T_305, _T_306) @[el2_ifu_iccm_mem.scala 79:61]
|
||||
node _T_308 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 80:22]
|
||||
node _T_309 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 80:48]
|
||||
node _T_310 = and(_T_308, _T_309) @[el2_ifu_iccm_mem.scala 80:26]
|
||||
node _T_311 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 80:70]
|
||||
node _T_312 = eq(_T_311, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 80:75]
|
||||
node _T_313 = or(_T_310, _T_312) @[el2_ifu_iccm_mem.scala 80:52]
|
||||
node _T_314 = and(_T_307, _T_313) @[el2_ifu_iccm_mem.scala 79:102]
|
||||
node _T_315 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 80:101]
|
||||
node _T_316 = and(_T_314, _T_315) @[el2_ifu_iccm_mem.scala 80:84]
|
||||
node _T_317 = and(_T_316, io.iccm_wren) @[el2_ifu_iccm_mem.scala 80:105]
|
||||
node _T_318 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 81:6]
|
||||
node _T_319 = and(_T_318, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 81:21]
|
||||
node redundant_data0_en = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 80:121]
|
||||
node _T_320 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 82:49]
|
||||
node _T_321 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:73]
|
||||
node _T_322 = and(_T_320, _T_321) @[el2_ifu_iccm_mem.scala 82:52]
|
||||
node _T_323 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:100]
|
||||
node _T_324 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 82:122]
|
||||
node _T_325 = eq(_T_324, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 82:127]
|
||||
node _T_326 = and(_T_323, _T_325) @[el2_ifu_iccm_mem.scala 82:104]
|
||||
node _T_327 = or(_T_322, _T_326) @[el2_ifu_iccm_mem.scala 82:78]
|
||||
node _T_328 = bits(_T_327, 0, 0) @[el2_ifu_iccm_mem.scala 82:137]
|
||||
node _T_329 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 83:20]
|
||||
node _T_330 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 83:44]
|
||||
node redundant_data0_in = mux(_T_328, _T_329, _T_330) @[el2_ifu_iccm_mem.scala 82:31]
|
||||
node _T_331 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:78]
|
||||
reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_331 : @[Reg.scala 28:19]
|
||||
_T_332 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
node _T_323 = cat(_T_321, _T_322) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_323 @[el2_ifu_iccm_mem.scala 82:19]
|
||||
node _T_324 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 84:45]
|
||||
node _T_325 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 84:85]
|
||||
node _T_326 = eq(_T_324, _T_325) @[el2_ifu_iccm_mem.scala 84:61]
|
||||
node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 85:22]
|
||||
node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 85:48]
|
||||
node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 85:26]
|
||||
node _T_330 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 85:70]
|
||||
node _T_331 = eq(_T_330, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 85:75]
|
||||
node _T_332 = or(_T_329, _T_331) @[el2_ifu_iccm_mem.scala 85:52]
|
||||
node _T_333 = and(_T_326, _T_332) @[el2_ifu_iccm_mem.scala 84:102]
|
||||
node _T_334 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 85:101]
|
||||
node _T_335 = and(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 85:84]
|
||||
node _T_336 = and(_T_335, io.iccm_wren) @[el2_ifu_iccm_mem.scala 85:105]
|
||||
node _T_337 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 86:6]
|
||||
node _T_338 = and(_T_337, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 86:21]
|
||||
node redundant_data0_en = or(_T_336, _T_338) @[el2_ifu_iccm_mem.scala 85:121]
|
||||
node _T_339 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:49]
|
||||
node _T_340 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:73]
|
||||
node _T_341 = and(_T_339, _T_340) @[el2_ifu_iccm_mem.scala 87:52]
|
||||
node _T_342 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 87:100]
|
||||
node _T_343 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:122]
|
||||
node _T_344 = eq(_T_343, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:127]
|
||||
node _T_345 = and(_T_342, _T_344) @[el2_ifu_iccm_mem.scala 87:104]
|
||||
node _T_346 = or(_T_341, _T_345) @[el2_ifu_iccm_mem.scala 87:78]
|
||||
node _T_347 = bits(_T_346, 0, 0) @[el2_ifu_iccm_mem.scala 87:137]
|
||||
node _T_348 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 88:20]
|
||||
node _T_349 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 88:44]
|
||||
node redundant_data0_in = mux(_T_347, _T_348, _T_349) @[el2_ifu_iccm_mem.scala 87:31]
|
||||
node _T_350 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 89:78]
|
||||
reg _T_351 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_350 : @[Reg.scala 28:19]
|
||||
_T_351 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[0] <= _T_332 @[el2_ifu_iccm_mem.scala 84:21]
|
||||
node _T_333 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45]
|
||||
node _T_334 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 86:85]
|
||||
node _T_335 = eq(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 86:61]
|
||||
node _T_336 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22]
|
||||
node _T_337 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 87:48]
|
||||
node _T_338 = and(_T_336, _T_337) @[el2_ifu_iccm_mem.scala 87:26]
|
||||
node _T_339 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70]
|
||||
node _T_340 = eq(_T_339, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75]
|
||||
node _T_341 = or(_T_338, _T_340) @[el2_ifu_iccm_mem.scala 87:52]
|
||||
node _T_342 = and(_T_335, _T_341) @[el2_ifu_iccm_mem.scala 86:102]
|
||||
node _T_343 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 87:101]
|
||||
node _T_344 = and(_T_342, _T_343) @[el2_ifu_iccm_mem.scala 87:84]
|
||||
node _T_345 = and(_T_344, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105]
|
||||
node _T_346 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6]
|
||||
node _T_347 = and(_T_346, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21]
|
||||
node redundant_data1_en = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 87:121]
|
||||
node _T_348 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49]
|
||||
node _T_349 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:73]
|
||||
node _T_350 = and(_T_348, _T_349) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
node _T_351 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:100]
|
||||
node _T_352 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122]
|
||||
node _T_353 = eq(_T_352, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127]
|
||||
node _T_354 = and(_T_351, _T_353) @[el2_ifu_iccm_mem.scala 89:104]
|
||||
node _T_355 = or(_T_350, _T_354) @[el2_ifu_iccm_mem.scala 89:78]
|
||||
node _T_356 = bits(_T_355, 0, 0) @[el2_ifu_iccm_mem.scala 89:137]
|
||||
node _T_357 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20]
|
||||
node _T_358 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44]
|
||||
node redundant_data1_in = mux(_T_356, _T_357, _T_358) @[el2_ifu_iccm_mem.scala 89:31]
|
||||
node _T_359 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78]
|
||||
reg _T_360 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_359 : @[Reg.scala 28:19]
|
||||
_T_360 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
redundant_data[0] <= _T_351 @[el2_ifu_iccm_mem.scala 89:21]
|
||||
node _T_352 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 91:45]
|
||||
node _T_353 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 91:85]
|
||||
node _T_354 = eq(_T_352, _T_353) @[el2_ifu_iccm_mem.scala 91:61]
|
||||
node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 92:22]
|
||||
node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 92:48]
|
||||
node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 92:26]
|
||||
node _T_358 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 92:70]
|
||||
node _T_359 = eq(_T_358, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 92:75]
|
||||
node _T_360 = or(_T_357, _T_359) @[el2_ifu_iccm_mem.scala 92:52]
|
||||
node _T_361 = and(_T_354, _T_360) @[el2_ifu_iccm_mem.scala 91:102]
|
||||
node _T_362 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 92:101]
|
||||
node _T_363 = and(_T_361, _T_362) @[el2_ifu_iccm_mem.scala 92:84]
|
||||
node _T_364 = and(_T_363, io.iccm_wren) @[el2_ifu_iccm_mem.scala 92:105]
|
||||
node _T_365 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 93:6]
|
||||
node _T_366 = and(_T_365, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 93:21]
|
||||
node redundant_data1_en = or(_T_364, _T_366) @[el2_ifu_iccm_mem.scala 92:121]
|
||||
node _T_367 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:49]
|
||||
node _T_368 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:73]
|
||||
node _T_369 = and(_T_367, _T_368) @[el2_ifu_iccm_mem.scala 94:52]
|
||||
node _T_370 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 94:100]
|
||||
node _T_371 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:122]
|
||||
node _T_372 = eq(_T_371, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:127]
|
||||
node _T_373 = and(_T_370, _T_372) @[el2_ifu_iccm_mem.scala 94:104]
|
||||
node _T_374 = or(_T_369, _T_373) @[el2_ifu_iccm_mem.scala 94:78]
|
||||
node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_iccm_mem.scala 94:137]
|
||||
node _T_376 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 95:20]
|
||||
node _T_377 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 95:44]
|
||||
node redundant_data1_in = mux(_T_375, _T_376, _T_377) @[el2_ifu_iccm_mem.scala 94:31]
|
||||
node _T_378 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 96:78]
|
||||
reg _T_379 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_378 : @[Reg.scala 28:19]
|
||||
_T_379 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[1] <= _T_360 @[el2_ifu_iccm_mem.scala 91:21]
|
||||
node _T_361 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 93:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 93:34]
|
||||
iccm_rd_addr_lo_q <= _T_361 @[el2_ifu_iccm_mem.scala 93:34]
|
||||
node _T_362 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 94:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 94:34]
|
||||
iccm_rd_addr_hi_q <= _T_362 @[el2_ifu_iccm_mem.scala 94:34]
|
||||
node _T_363 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:86]
|
||||
node _T_364 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
|
||||
node _T_365 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:86]
|
||||
node _T_366 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
|
||||
node _T_367 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:86]
|
||||
node _T_368 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
|
||||
node _T_369 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:86]
|
||||
node _T_370 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
|
||||
node _T_371 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_372 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_373 = mux(_T_367, _T_368, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_374 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_375 = or(_T_371, _T_372) @[Mux.scala 27:72]
|
||||
node _T_376 = or(_T_375, _T_373) @[Mux.scala 27:72]
|
||||
node _T_377 = or(_T_376, _T_374) @[Mux.scala 27:72]
|
||||
wire _T_378 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_378 <= _T_377 @[Mux.scala 27:72]
|
||||
node _T_379 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
|
||||
node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:77]
|
||||
node _T_381 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
|
||||
node _T_382 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
|
||||
node _T_383 = eq(_T_382, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:77]
|
||||
node _T_384 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
|
||||
node _T_385 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
|
||||
node _T_386 = eq(_T_385, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:77]
|
||||
node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
|
||||
node _T_388 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
|
||||
node _T_389 = eq(_T_388, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:77]
|
||||
node _T_390 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
|
||||
node _T_391 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_392 = mux(_T_383, _T_384, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_393 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_394 = mux(_T_389, _T_390, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_395 = or(_T_391, _T_392) @[Mux.scala 27:72]
|
||||
redundant_data[1] <= _T_379 @[el2_ifu_iccm_mem.scala 96:21]
|
||||
node _T_380 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 98:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 98:34]
|
||||
iccm_rd_addr_lo_q <= _T_380 @[el2_ifu_iccm_mem.scala 98:34]
|
||||
node _T_381 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 99:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 99:34]
|
||||
iccm_rd_addr_hi_q <= _T_381 @[el2_ifu_iccm_mem.scala 99:34]
|
||||
node _T_382 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 101:86]
|
||||
node _T_383 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 101:115]
|
||||
node _T_384 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 101:86]
|
||||
node _T_385 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 101:115]
|
||||
node _T_386 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 101:86]
|
||||
node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 101:115]
|
||||
node _T_388 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:86]
|
||||
node _T_389 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 101:115]
|
||||
node _T_390 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_391 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_392 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_393 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72]
|
||||
node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72]
|
||||
node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
|
||||
node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72]
|
||||
wire _T_398 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_398 <= _T_397 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_378, _T_398) @[Cat.scala 29:58]
|
||||
node _T_399 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 98:43]
|
||||
node _T_400 = bits(_T_399, 0, 0) @[el2_ifu_iccm_mem.scala 98:53]
|
||||
node _T_401 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_402 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 98:89]
|
||||
node _T_403 = cat(_T_401, _T_402) @[Cat.scala 29:58]
|
||||
node _T_404 = mux(_T_400, _T_403, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 98:25]
|
||||
io.iccm_rd_data <= _T_404 @[el2_ifu_iccm_mem.scala 98:19]
|
||||
node _T_405 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 99:85]
|
||||
node _T_406 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 99:85]
|
||||
node _T_407 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 99:85]
|
||||
node _T_408 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 99:85]
|
||||
node _T_409 = mux(_T_405, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_410 = mux(_T_406, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_411 = mux(_T_407, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_412 = mux(_T_408, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_413 = or(_T_409, _T_410) @[Mux.scala 27:72]
|
||||
node _T_414 = or(_T_413, _T_411) @[Mux.scala 27:72]
|
||||
wire _T_397 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_397 <= _T_396 @[Mux.scala 27:72]
|
||||
node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59]
|
||||
node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:77]
|
||||
node _T_400 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 102:106]
|
||||
node _T_401 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59]
|
||||
node _T_402 = eq(_T_401, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 102:77]
|
||||
node _T_403 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 102:106]
|
||||
node _T_404 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59]
|
||||
node _T_405 = eq(_T_404, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 102:77]
|
||||
node _T_406 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 102:106]
|
||||
node _T_407 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 102:59]
|
||||
node _T_408 = eq(_T_407, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 102:77]
|
||||
node _T_409 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 102:106]
|
||||
node _T_410 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_411 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_412 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_413 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_414 = or(_T_410, _T_411) @[Mux.scala 27:72]
|
||||
node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72]
|
||||
wire _T_416 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_416 <= _T_415 @[Mux.scala 27:72]
|
||||
node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 100:79]
|
||||
node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_420 = eq(_T_419, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 100:79]
|
||||
node _T_421 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_422 = eq(_T_421, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 100:79]
|
||||
node _T_423 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
|
||||
node _T_424 = eq(_T_423, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 100:79]
|
||||
node _T_425 = mux(_T_418, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_426 = mux(_T_420, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_427 = mux(_T_422, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72]
|
||||
node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72]
|
||||
node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72]
|
||||
wire _T_432 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_432 <= _T_431 @[Mux.scala 27:72]
|
||||
node _T_433 = cat(_T_416, _T_432) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_433 @[el2_ifu_iccm_mem.scala 99:23]
|
||||
node _T_416 = or(_T_415, _T_413) @[Mux.scala 27:72]
|
||||
wire _T_417 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_417 <= _T_416 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_397, _T_417) @[Cat.scala 29:58]
|
||||
node _T_418 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 103:43]
|
||||
node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_iccm_mem.scala 103:53]
|
||||
node _T_420 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_421 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 103:89]
|
||||
node _T_422 = cat(_T_420, _T_421) @[Cat.scala 29:58]
|
||||
node _T_423 = mux(_T_419, _T_422, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 103:25]
|
||||
io.iccm_rd_data <= _T_423 @[el2_ifu_iccm_mem.scala 103:19]
|
||||
node _T_424 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 104:85]
|
||||
node _T_425 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 104:85]
|
||||
node _T_426 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 104:85]
|
||||
node _T_427 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 104:85]
|
||||
node _T_428 = mux(_T_424, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_429 = mux(_T_425, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_430 = mux(_T_426, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_431 = mux(_T_427, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_432 = or(_T_428, _T_429) @[Mux.scala 27:72]
|
||||
node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72]
|
||||
node _T_434 = or(_T_433, _T_431) @[Mux.scala 27:72]
|
||||
wire _T_435 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_435 <= _T_434 @[Mux.scala 27:72]
|
||||
node _T_436 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61]
|
||||
node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:79]
|
||||
node _T_438 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61]
|
||||
node _T_439 = eq(_T_438, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:79]
|
||||
node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61]
|
||||
node _T_441 = eq(_T_440, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:79]
|
||||
node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 105:61]
|
||||
node _T_443 = eq(_T_442, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:79]
|
||||
node _T_444 = mux(_T_437, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_445 = mux(_T_439, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_446 = mux(_T_441, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_447 = mux(_T_443, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_448 = or(_T_444, _T_445) @[Mux.scala 27:72]
|
||||
node _T_449 = or(_T_448, _T_446) @[Mux.scala 27:72]
|
||||
node _T_450 = or(_T_449, _T_447) @[Mux.scala 27:72]
|
||||
wire _T_451 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_451 <= _T_450 @[Mux.scala 27:72]
|
||||
node _T_452 = cat(_T_435, _T_451) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_452 @[el2_ifu_iccm_mem.scala 104:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@ module el2_ifu_iccm_mem(
|
|||
output [63:0] io_iccm_rd_data,
|
||||
output [77:0] io_iccm_rd_data_ecc,
|
||||
input io_scan_mode,
|
||||
output [38:0] io_iccm_bank_wr_data_0,
|
||||
output [38:0] io_iccm_bank_wr_data_1,
|
||||
output [38:0] io_iccm_bank_wr_data_2,
|
||||
output [38:0] io_iccm_bank_wr_data_3
|
||||
output [11:0] io_iccm_bank_addr_0,
|
||||
output [11:0] io_iccm_bank_addr_1,
|
||||
output [11:0] io_iccm_bank_addr_2,
|
||||
output [11:0] io_iccm_bank_addr_3
|
||||
);
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
reg [63:0] _RAND_0;
|
||||
|
|
@ -41,8 +41,14 @@ module el2_ifu_iccm_mem(
|
|||
reg [31:0] _RAND_18;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -60,8 +66,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -79,8 +91,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -98,8 +116,14 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_99_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_99_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_104_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_104_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_109_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_109_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_114_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_114_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
|
|
@ -118,8 +142,8 @@ module el2_ifu_iccm_mem(
|
|||
wire iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
|
||||
wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
|
||||
wire [14:0] _GEN_15 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_15; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
|
||||
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
|
||||
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
|
||||
|
|
@ -155,164 +179,202 @@ module el2_ifu_iccm_mem(
|
|||
wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72]
|
||||
wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
|
||||
wire [11:0] _T_59 = _T_12 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_66 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_73 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire [11:0] _T_80 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] addr_bank_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 38:55]
|
||||
wire _T_85 = ~wren_bank_0; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_0 = iccm_clken_0 & _T_85; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_87 = ~wren_bank_1; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_1 = iccm_clken_1 & _T_87; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_89 = ~wren_bank_2; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_2 = iccm_clken_2 & _T_89; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire _T_91 = ~wren_bank_3; // @[el2_ifu_iccm_mem.scala 44:72]
|
||||
wire read_enable_3 = iccm_clken_3 & _T_91; // @[el2_ifu_iccm_mem.scala 44:70]
|
||||
wire [38:0] _T_98 = read_enable_0 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_8 = iccm_mem_0__T_99_data; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_9 = 2'h1 == addr_bank_0[1:0] ? iccm_mem_1__T_99_data : _GEN_8; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_10 = 2'h2 == addr_bank_0[1:0] ? iccm_mem_2__T_99_data : _GEN_9; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_11 = 2'h3 == addr_bank_0[1:0] ? iccm_mem_3__T_99_data : _GEN_10; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _T_103 = read_enable_1 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_12 = iccm_mem_0__T_104_data; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_13 = 2'h1 == addr_bank_1[1:0] ? iccm_mem_1__T_104_data : _GEN_12; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_14 = 2'h2 == addr_bank_1[1:0] ? iccm_mem_2__T_104_data : _GEN_13; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_15 = 2'h3 == addr_bank_1[1:0] ? iccm_mem_3__T_104_data : _GEN_14; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _T_108 = read_enable_2 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_16 = iccm_mem_0__T_109_data; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_17 = 2'h1 == addr_bank_2[1:0] ? iccm_mem_1__T_109_data : _GEN_16; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_18 = 2'h2 == addr_bank_2[1:0] ? iccm_mem_2__T_109_data : _GEN_17; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_19 = 2'h3 == addr_bank_2[1:0] ? iccm_mem_3__T_109_data : _GEN_18; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _T_113 = read_enable_3 ? 39'h7fffffffff : 39'h0; // @[Bitwise.scala 72:12]
|
||||
wire [38:0] _GEN_20 = iccm_mem_0__T_114_data; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_21 = 2'h1 == addr_bank_3[1:0] ? iccm_mem_1__T_114_data : _GEN_20; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_22 = 2'h2 == addr_bank_3[1:0] ? iccm_mem_2__T_114_data : _GEN_21; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
wire [38:0] _GEN_23 = 2'h3 == addr_bank_3[1:0] ? iccm_mem_3__T_114_data : _GEN_22; // @[el2_ifu_iccm_mem.scala 49:67]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 50:62]
|
||||
reg _T_302; // @[Reg.scala 27:20]
|
||||
reg _T_303; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_302,_T_303}; // @[Cat.scala 29:58]
|
||||
reg _T_321; // @[Reg.scala 27:20]
|
||||
reg _T_322; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_321,_T_322}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
|
||||
wire _T_105 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 56:105]
|
||||
wire _T_108 = _T_105 & _T_10; // @[el2_ifu_iccm_mem.scala 56:145]
|
||||
wire _T_109 = redundant_valid[1] & _T_108; // @[el2_ifu_iccm_mem.scala 56:71]
|
||||
wire _T_112 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 57:37]
|
||||
wire _T_115 = _T_112 & _T_12; // @[el2_ifu_iccm_mem.scala 57:77]
|
||||
wire _T_116 = _T_109 | _T_115; // @[el2_ifu_iccm_mem.scala 56:179]
|
||||
wire _T_123 = _T_105 & _T_15; // @[el2_ifu_iccm_mem.scala 56:145]
|
||||
wire _T_124 = redundant_valid[1] & _T_123; // @[el2_ifu_iccm_mem.scala 56:71]
|
||||
wire _T_130 = _T_112 & _T_17; // @[el2_ifu_iccm_mem.scala 57:77]
|
||||
wire _T_131 = _T_124 | _T_130; // @[el2_ifu_iccm_mem.scala 56:179]
|
||||
wire _T_138 = _T_105 & _T_20; // @[el2_ifu_iccm_mem.scala 56:145]
|
||||
wire _T_139 = redundant_valid[1] & _T_138; // @[el2_ifu_iccm_mem.scala 56:71]
|
||||
wire _T_145 = _T_112 & _T_22; // @[el2_ifu_iccm_mem.scala 57:77]
|
||||
wire _T_146 = _T_139 | _T_145; // @[el2_ifu_iccm_mem.scala 56:179]
|
||||
wire _T_153 = _T_105 & _T_25; // @[el2_ifu_iccm_mem.scala 56:145]
|
||||
wire _T_154 = redundant_valid[1] & _T_153; // @[el2_ifu_iccm_mem.scala 56:71]
|
||||
wire _T_160 = _T_112 & _T_27; // @[el2_ifu_iccm_mem.scala 57:77]
|
||||
wire _T_161 = _T_154 | _T_160; // @[el2_ifu_iccm_mem.scala 56:179]
|
||||
wire [3:0] sel_red1 = {_T_161,_T_146,_T_131,_T_116}; // @[Cat.scala 29:58]
|
||||
wire _T_124 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 61:105]
|
||||
wire _T_127 = _T_124 & _T_10; // @[el2_ifu_iccm_mem.scala 61:145]
|
||||
wire _T_128 = redundant_valid[1] & _T_127; // @[el2_ifu_iccm_mem.scala 61:71]
|
||||
wire _T_131 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 62:37]
|
||||
wire _T_134 = _T_131 & _T_12; // @[el2_ifu_iccm_mem.scala 62:77]
|
||||
wire _T_135 = _T_128 | _T_134; // @[el2_ifu_iccm_mem.scala 61:179]
|
||||
wire _T_142 = _T_124 & _T_15; // @[el2_ifu_iccm_mem.scala 61:145]
|
||||
wire _T_143 = redundant_valid[1] & _T_142; // @[el2_ifu_iccm_mem.scala 61:71]
|
||||
wire _T_149 = _T_131 & _T_17; // @[el2_ifu_iccm_mem.scala 62:77]
|
||||
wire _T_150 = _T_143 | _T_149; // @[el2_ifu_iccm_mem.scala 61:179]
|
||||
wire _T_157 = _T_124 & _T_20; // @[el2_ifu_iccm_mem.scala 61:145]
|
||||
wire _T_158 = redundant_valid[1] & _T_157; // @[el2_ifu_iccm_mem.scala 61:71]
|
||||
wire _T_164 = _T_131 & _T_22; // @[el2_ifu_iccm_mem.scala 62:77]
|
||||
wire _T_165 = _T_158 | _T_164; // @[el2_ifu_iccm_mem.scala 61:179]
|
||||
wire _T_172 = _T_124 & _T_25; // @[el2_ifu_iccm_mem.scala 61:145]
|
||||
wire _T_173 = redundant_valid[1] & _T_172; // @[el2_ifu_iccm_mem.scala 61:71]
|
||||
wire _T_179 = _T_131 & _T_27; // @[el2_ifu_iccm_mem.scala 62:77]
|
||||
wire _T_180 = _T_173 | _T_179; // @[el2_ifu_iccm_mem.scala 61:179]
|
||||
wire [3:0] sel_red1 = {_T_180,_T_165,_T_150,_T_135}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
|
||||
wire _T_167 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 58:105]
|
||||
wire _T_170 = _T_167 & _T_10; // @[el2_ifu_iccm_mem.scala 58:145]
|
||||
wire _T_171 = redundant_valid[0] & _T_170; // @[el2_ifu_iccm_mem.scala 58:71]
|
||||
wire _T_174 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 59:37]
|
||||
wire _T_177 = _T_174 & _T_12; // @[el2_ifu_iccm_mem.scala 59:77]
|
||||
wire _T_178 = _T_171 | _T_177; // @[el2_ifu_iccm_mem.scala 58:179]
|
||||
wire _T_185 = _T_167 & _T_15; // @[el2_ifu_iccm_mem.scala 58:145]
|
||||
wire _T_186 = redundant_valid[0] & _T_185; // @[el2_ifu_iccm_mem.scala 58:71]
|
||||
wire _T_192 = _T_174 & _T_17; // @[el2_ifu_iccm_mem.scala 59:77]
|
||||
wire _T_193 = _T_186 | _T_192; // @[el2_ifu_iccm_mem.scala 58:179]
|
||||
wire _T_200 = _T_167 & _T_20; // @[el2_ifu_iccm_mem.scala 58:145]
|
||||
wire _T_201 = redundant_valid[0] & _T_200; // @[el2_ifu_iccm_mem.scala 58:71]
|
||||
wire _T_207 = _T_174 & _T_22; // @[el2_ifu_iccm_mem.scala 59:77]
|
||||
wire _T_208 = _T_201 | _T_207; // @[el2_ifu_iccm_mem.scala 58:179]
|
||||
wire _T_215 = _T_167 & _T_25; // @[el2_ifu_iccm_mem.scala 58:145]
|
||||
wire _T_216 = redundant_valid[0] & _T_215; // @[el2_ifu_iccm_mem.scala 58:71]
|
||||
wire _T_222 = _T_174 & _T_27; // @[el2_ifu_iccm_mem.scala 59:77]
|
||||
wire _T_223 = _T_216 | _T_222; // @[el2_ifu_iccm_mem.scala 58:179]
|
||||
wire [3:0] sel_red0 = {_T_223,_T_208,_T_193,_T_178}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 61:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 62:27]
|
||||
wire _T_231 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 68:36]
|
||||
wire _T_233 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 68:53]
|
||||
wire _T_234 = _T_231 & _T_233; // @[el2_ifu_iccm_mem.scala 68:51]
|
||||
wire _T_186 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 63:105]
|
||||
wire _T_189 = _T_186 & _T_10; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_190 = redundant_valid[0] & _T_189; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_193 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 64:37]
|
||||
wire _T_196 = _T_193 & _T_12; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_197 = _T_190 | _T_196; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_204 = _T_186 & _T_15; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_205 = redundant_valid[0] & _T_204; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_211 = _T_193 & _T_17; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_212 = _T_205 | _T_211; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_219 = _T_186 & _T_20; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_220 = redundant_valid[0] & _T_219; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_226 = _T_193 & _T_22; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_227 = _T_220 | _T_226; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire _T_234 = _T_186 & _T_25; // @[el2_ifu_iccm_mem.scala 63:145]
|
||||
wire _T_235 = redundant_valid[0] & _T_234; // @[el2_ifu_iccm_mem.scala 63:71]
|
||||
wire _T_241 = _T_193 & _T_27; // @[el2_ifu_iccm_mem.scala 64:77]
|
||||
wire _T_242 = _T_235 | _T_241; // @[el2_ifu_iccm_mem.scala 63:179]
|
||||
wire [3:0] sel_red0 = {_T_242,_T_227,_T_212,_T_197}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 66:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 67:27]
|
||||
wire _T_250 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 73:36]
|
||||
wire _T_252 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 73:53]
|
||||
wire _T_253 = _T_250 & _T_252; // @[el2_ifu_iccm_mem.scala 73:51]
|
||||
reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_236 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_255 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_237 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_238 = _T_234 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_239 = _T_236 | _T_237; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_239 | _T_238; // @[Mux.scala 27:72]
|
||||
wire _T_246 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 68:36]
|
||||
wire _T_248 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 68:53]
|
||||
wire _T_249 = _T_246 & _T_248; // @[el2_ifu_iccm_mem.scala 68:51]
|
||||
wire [38:0] _T_251 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_252 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_253 = _T_249 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_254 = _T_251 | _T_252; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_254 | _T_253; // @[Mux.scala 27:72]
|
||||
wire _T_261 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 68:36]
|
||||
wire _T_263 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 68:53]
|
||||
wire _T_264 = _T_261 & _T_263; // @[el2_ifu_iccm_mem.scala 68:51]
|
||||
wire [38:0] _T_266 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_267 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_268 = _T_264 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_269 = _T_266 | _T_267; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_269 | _T_268; // @[Mux.scala 27:72]
|
||||
wire _T_276 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 68:36]
|
||||
wire _T_278 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 68:53]
|
||||
wire _T_279 = _T_276 & _T_278; // @[el2_ifu_iccm_mem.scala 68:51]
|
||||
wire [38:0] _T_281 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_282 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_283 = _T_279 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_284 = _T_281 | _T_282; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_284 | _T_283; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_256 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_257 = _T_253 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_258 | _T_257; // @[Mux.scala 27:72]
|
||||
wire _T_265 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 73:36]
|
||||
wire _T_267 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 73:53]
|
||||
wire _T_268 = _T_265 & _T_267; // @[el2_ifu_iccm_mem.scala 73:51]
|
||||
wire [38:0] _T_270 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_271 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_272 = _T_268 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_273 = _T_270 | _T_271; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_273 | _T_272; // @[Mux.scala 27:72]
|
||||
wire _T_280 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 73:36]
|
||||
wire _T_282 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 73:53]
|
||||
wire _T_283 = _T_280 & _T_282; // @[el2_ifu_iccm_mem.scala 73:51]
|
||||
wire [38:0] _T_285 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_286 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_287 = _T_283 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_288 = _T_285 | _T_286; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_288 | _T_287; // @[Mux.scala 27:72]
|
||||
wire _T_295 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 73:36]
|
||||
wire _T_297 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 73:53]
|
||||
wire _T_298 = _T_295 & _T_297; // @[el2_ifu_iccm_mem.scala 73:51]
|
||||
wire [38:0] _T_300 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_301 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_302 = _T_298 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_303 = _T_300 | _T_301; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_303 | _T_302; // @[Mux.scala 27:72]
|
||||
reg redundant_lru; // @[Reg.scala 27:20]
|
||||
wire _T_286 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 70:20]
|
||||
wire r0_addr_en = _T_286 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 70:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 71:35]
|
||||
wire _T_287 = |sel_red0; // @[el2_ifu_iccm_mem.scala 72:63]
|
||||
wire _T_288 = |sel_red1; // @[el2_ifu_iccm_mem.scala 72:78]
|
||||
wire _T_289 = _T_287 | _T_288; // @[el2_ifu_iccm_mem.scala 72:67]
|
||||
wire _T_290 = _T_289 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 72:83]
|
||||
wire _T_291 = _T_290 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 72:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_291; // @[el2_ifu_iccm_mem.scala 72:50]
|
||||
wire _GEN_11 = r1_addr_en | _T_302; // @[Reg.scala 28:19]
|
||||
wire _GEN_12 = r0_addr_en | _T_303; // @[Reg.scala 28:19]
|
||||
wire _T_307 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 79:61]
|
||||
wire _T_310 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 80:26]
|
||||
wire _T_313 = _T_310 | _T_1; // @[el2_ifu_iccm_mem.scala 80:52]
|
||||
wire _T_314 = _T_307 & _T_313; // @[el2_ifu_iccm_mem.scala 79:102]
|
||||
wire _T_316 = _T_314 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 80:84]
|
||||
wire _T_317 = _T_316 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 80:105]
|
||||
wire redundant_data0_en = _T_317 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 80:121]
|
||||
wire _T_326 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 82:104]
|
||||
wire _T_327 = _T_310 | _T_326; // @[el2_ifu_iccm_mem.scala 82:78]
|
||||
wire _T_335 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 86:61]
|
||||
wire _T_338 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 87:26]
|
||||
wire _T_341 = _T_338 | _T_1; // @[el2_ifu_iccm_mem.scala 87:52]
|
||||
wire _T_342 = _T_335 & _T_341; // @[el2_ifu_iccm_mem.scala 86:102]
|
||||
wire _T_344 = _T_342 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 87:84]
|
||||
wire _T_345 = _T_344 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 87:105]
|
||||
wire redundant_data1_en = _T_345 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 87:121]
|
||||
wire _T_354 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 89:104]
|
||||
wire _T_355 = _T_338 | _T_354; // @[el2_ifu_iccm_mem.scala 89:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 93:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 94:34]
|
||||
wire _T_363 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 96:86]
|
||||
wire _T_365 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 96:86]
|
||||
wire _T_367 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 96:86]
|
||||
wire _T_369 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 96:86]
|
||||
wire [31:0] _T_371 = _T_363 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_372 = _T_365 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_373 = _T_367 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_374 = _T_369 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_375 = _T_371 | _T_372; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_376 = _T_375 | _T_373; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_377 = _T_376 | _T_374; // @[Mux.scala 27:72]
|
||||
wire _T_380 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 97:77]
|
||||
wire _T_383 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 97:77]
|
||||
wire _T_386 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 97:77]
|
||||
wire _T_389 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 97:77]
|
||||
wire [31:0] _T_391 = _T_380 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_392 = _T_383 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_393 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_394 = _T_389 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72]
|
||||
wire _T_305 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 75:20]
|
||||
wire r0_addr_en = _T_305 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 75:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 76:35]
|
||||
wire _T_306 = |sel_red0; // @[el2_ifu_iccm_mem.scala 77:63]
|
||||
wire _T_307 = |sel_red1; // @[el2_ifu_iccm_mem.scala 77:78]
|
||||
wire _T_308 = _T_306 | _T_307; // @[el2_ifu_iccm_mem.scala 77:67]
|
||||
wire _T_309 = _T_308 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 77:83]
|
||||
wire _T_310 = _T_309 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 77:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_310; // @[el2_ifu_iccm_mem.scala 77:50]
|
||||
wire _GEN_27 = r1_addr_en | _T_321; // @[Reg.scala 28:19]
|
||||
wire _GEN_28 = r0_addr_en | _T_322; // @[Reg.scala 28:19]
|
||||
wire _T_326 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 84:61]
|
||||
wire _T_329 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 85:26]
|
||||
wire _T_332 = _T_329 | _T_1; // @[el2_ifu_iccm_mem.scala 85:52]
|
||||
wire _T_333 = _T_326 & _T_332; // @[el2_ifu_iccm_mem.scala 84:102]
|
||||
wire _T_335 = _T_333 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 85:84]
|
||||
wire _T_336 = _T_335 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 85:105]
|
||||
wire redundant_data0_en = _T_336 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 85:121]
|
||||
wire _T_345 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 87:104]
|
||||
wire _T_346 = _T_329 | _T_345; // @[el2_ifu_iccm_mem.scala 87:78]
|
||||
wire _T_354 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 91:61]
|
||||
wire _T_357 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 92:26]
|
||||
wire _T_360 = _T_357 | _T_1; // @[el2_ifu_iccm_mem.scala 92:52]
|
||||
wire _T_361 = _T_354 & _T_360; // @[el2_ifu_iccm_mem.scala 91:102]
|
||||
wire _T_363 = _T_361 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 92:84]
|
||||
wire _T_364 = _T_363 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 92:105]
|
||||
wire redundant_data1_en = _T_364 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 92:121]
|
||||
wire _T_373 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 94:104]
|
||||
wire _T_374 = _T_357 | _T_373; // @[el2_ifu_iccm_mem.scala 94:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 98:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 99:34]
|
||||
wire _T_382 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 101:86]
|
||||
wire _T_384 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 101:86]
|
||||
wire _T_386 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 101:86]
|
||||
wire _T_388 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 101:86]
|
||||
wire [31:0] _T_390 = _T_382 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_391 = _T_384 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_392 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_393 = _T_388 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_397 = _T_396 | _T_394; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_377,_T_397}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_403 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_409 = _T_363 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_410 = _T_365 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_411 = _T_367 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_412 = _T_369 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_413 = _T_409 | _T_410; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_414 = _T_413 | _T_411; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_425 = _T_380 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_426 = _T_383 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_427 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_428 = _T_389 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_429 = _T_425 | _T_426; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_430 = _T_429 | _T_427; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_431 = _T_430 | _T_428; // @[Mux.scala 27:72]
|
||||
assign iccm_mem_0__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_97_data = iccm_mem_0[iccm_mem_0__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire _T_399 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 102:77]
|
||||
wire _T_402 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 102:77]
|
||||
wire _T_405 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 102:77]
|
||||
wire _T_408 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 102:77]
|
||||
wire [31:0] _T_410 = _T_399 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_411 = _T_402 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_412 = _T_405 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_413 = _T_408 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_414 = _T_410 | _T_411; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_416 = _T_415 | _T_413; // @[Mux.scala 27:72]
|
||||
wire [63:0] iccm_rd_data_pre = {_T_396,_T_416}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_422 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_428 = _T_382 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_429 = _T_384 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_430 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_431 = _T_388 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_432 = _T_428 | _T_429; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_433 = _T_432 | _T_430; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_434 = _T_433 | _T_431; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_444 = _T_399 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_445 = _T_402 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_446 = _T_405 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_447 = _T_408 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_448 = _T_444 | _T_445; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_449 = _T_448 | _T_446; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_450 = _T_449 | _T_447; // @[Mux.scala 27:72]
|
||||
assign iccm_mem_0__T_99_addr = 12'h0;
|
||||
assign iccm_mem_0__T_99_data = iccm_mem_0[iccm_mem_0__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_104_addr = 12'h1;
|
||||
assign iccm_mem_0__T_104_data = iccm_mem_0[iccm_mem_0__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_109_addr = 12'h2;
|
||||
assign iccm_mem_0__T_109_data = iccm_mem_0[iccm_mem_0__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_114_addr = 12'h3;
|
||||
assign iccm_mem_0__T_114_data = iccm_mem_0[iccm_mem_0__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_93_data = io_iccm_wr_data[38:0];
|
||||
assign iccm_mem_0__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_93_mask = iccm_clken_0 & wren_bank_0;
|
||||
|
|
@ -329,8 +391,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_0__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_0__T_96_mask = iccm_clken_0 & wren_bank_0;
|
||||
assign iccm_mem_0__T_96_en = 1'h1;
|
||||
assign iccm_mem_1__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_97_data = iccm_mem_1[iccm_mem_1__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_99_addr = 12'h0;
|
||||
assign iccm_mem_1__T_99_data = iccm_mem_1[iccm_mem_1__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_104_addr = 12'h1;
|
||||
assign iccm_mem_1__T_104_data = iccm_mem_1[iccm_mem_1__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_109_addr = 12'h2;
|
||||
assign iccm_mem_1__T_109_data = iccm_mem_1[iccm_mem_1__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_114_addr = 12'h3;
|
||||
assign iccm_mem_1__T_114_data = iccm_mem_1[iccm_mem_1__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_93_data = io_iccm_wr_data[77:39];
|
||||
assign iccm_mem_1__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_93_mask = iccm_clken_1 & wren_bank_1;
|
||||
|
|
@ -347,8 +415,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_1__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_1__T_96_mask = iccm_clken_1 & wren_bank_1;
|
||||
assign iccm_mem_1__T_96_en = 1'h1;
|
||||
assign iccm_mem_2__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_97_data = iccm_mem_2[iccm_mem_2__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_99_addr = 12'h0;
|
||||
assign iccm_mem_2__T_99_data = iccm_mem_2[iccm_mem_2__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_104_addr = 12'h1;
|
||||
assign iccm_mem_2__T_104_data = iccm_mem_2[iccm_mem_2__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_109_addr = 12'h2;
|
||||
assign iccm_mem_2__T_109_data = iccm_mem_2[iccm_mem_2__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_114_addr = 12'h3;
|
||||
assign iccm_mem_2__T_114_data = iccm_mem_2[iccm_mem_2__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_93_data = io_iccm_wr_data[38:0];
|
||||
assign iccm_mem_2__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_93_mask = iccm_clken_2 & wren_bank_2;
|
||||
|
|
@ -365,8 +439,14 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_2__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_2__T_96_mask = iccm_clken_2 & wren_bank_2;
|
||||
assign iccm_mem_2__T_96_en = 1'h1;
|
||||
assign iccm_mem_3__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_97_data = iccm_mem_3[iccm_mem_3__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_99_addr = 12'h0;
|
||||
assign iccm_mem_3__T_99_data = iccm_mem_3[iccm_mem_3__T_99_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_104_addr = 12'h1;
|
||||
assign iccm_mem_3__T_104_data = iccm_mem_3[iccm_mem_3__T_104_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_109_addr = 12'h2;
|
||||
assign iccm_mem_3__T_109_data = iccm_mem_3[iccm_mem_3__T_109_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_114_addr = 12'h3;
|
||||
assign iccm_mem_3__T_114_data = iccm_mem_3[iccm_mem_3__T_114_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_93_data = io_iccm_wr_data[77:39];
|
||||
assign iccm_mem_3__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_93_mask = iccm_clken_3 & wren_bank_3;
|
||||
|
|
@ -383,12 +463,12 @@ module el2_ifu_iccm_mem(
|
|||
assign iccm_mem_3__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_3__T_96_mask = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_3__T_96_en = 1'h1;
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_403 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 98:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_415,_T_431}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 99:23]
|
||||
assign io_iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24]
|
||||
assign io_iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24]
|
||||
assign io_iccm_bank_wr_data_2 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24]
|
||||
assign io_iccm_bank_wr_data_3 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24]
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_422 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 103:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_434,_T_450}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 104:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 52:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 52:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 52:21]
|
||||
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 52:21]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -447,9 +527,9 @@ initial begin
|
|||
_RAND_7 = {2{`RANDOM}};
|
||||
iccm_bank_dout_3 = _RAND_7[38:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
_T_302 = _RAND_8[0:0];
|
||||
_T_321 = _RAND_8[0:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
_T_303 = _RAND_9[0:0];
|
||||
_T_322 = _RAND_9[0:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
redundant_address_1 = _RAND_10[13:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
|
|
@ -524,19 +604,19 @@ end // initial
|
|||
if(iccm_mem_3__T_96_en & iccm_mem_3__T_96_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
iccm_bank_dout_0 <= iccm_mem_0__T_97_data;
|
||||
iccm_bank_dout_1 <= iccm_mem_1__T_97_data;
|
||||
iccm_bank_dout_2 <= iccm_mem_2__T_97_data;
|
||||
iccm_bank_dout_3 <= iccm_mem_3__T_97_data;
|
||||
iccm_bank_dout_0 <= _T_98 & _GEN_11;
|
||||
iccm_bank_dout_1 <= _T_103 & _GEN_15;
|
||||
iccm_bank_dout_2 <= _T_108 & _GEN_19;
|
||||
iccm_bank_dout_3 <= _T_113 & _GEN_23;
|
||||
if (reset) begin
|
||||
_T_302 <= 1'h0;
|
||||
_T_321 <= 1'h0;
|
||||
end else begin
|
||||
_T_302 <= _GEN_11;
|
||||
_T_321 <= _GEN_27;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_303 <= 1'h0;
|
||||
_T_322 <= 1'h0;
|
||||
end else begin
|
||||
_T_303 <= _GEN_12;
|
||||
_T_322 <= _GEN_28;
|
||||
end
|
||||
if (reset) begin
|
||||
redundant_address_1 <= 14'h0;
|
||||
|
|
@ -561,7 +641,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_1 <= 39'h0;
|
||||
end else if (redundant_data1_en) begin
|
||||
if (_T_355) begin
|
||||
if (_T_374) begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_1 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -570,7 +650,7 @@ end // initial
|
|||
if (reset) begin
|
||||
redundant_data_0 <= 39'h0;
|
||||
end else if (redundant_data0_en) begin
|
||||
if (_T_327) begin
|
||||
if (_T_346) begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_1;
|
||||
end else begin
|
||||
redundant_data_0 <= iccm_bank_wr_data_0;
|
||||
|
|
@ -580,9 +660,9 @@ end // initial
|
|||
redundant_lru <= 1'h0;
|
||||
end else if (redundant_lru_en) begin
|
||||
if (io_iccm_buf_correct_ecc) begin
|
||||
redundant_lru <= _T_286;
|
||||
redundant_lru <= _T_305;
|
||||
end else begin
|
||||
redundant_lru <= _T_287;
|
||||
redundant_lru <= _T_306;
|
||||
end
|
||||
end
|
||||
if (reset) begin
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
|
|||
val iccm_rd_data = Output(UInt(64.W))
|
||||
val iccm_rd_data_ecc = Output(UInt(78.W))
|
||||
val scan_mode = Input(Bool())
|
||||
val iccm_bank_wr_data = Output(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
val iccm_bank_addr = Output(Vec(ICCM_NUM_BANKS, UInt()))
|
||||
})
|
||||
io.iccm_rd_data := 0.U
|
||||
io.iccm_rd_data_ecc := 0.U
|
||||
|
|
@ -32,7 +32,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
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val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&((io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)))
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val iccm_bank_wr_data = iccm_bank_wr_data_vec
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io.iccm_bank_wr_data := iccm_bank_wr_data
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//io.iccm_bank_wr_data := iccm_bank_wr_data
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val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))
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val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield wren_bank(i) | rden_bank(i) | io.clk_override
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val addr_bank = (0 until ICCM_NUM_BANKS).map(i=> Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1),
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@ -46,9 +46,14 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
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val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
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val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
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for(i<-0 until ICCM_NUM_BANKS) iccm_mem.write(addr_bank(i), iccm_bank_wr_data, write_vec)
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inter := iccm_mem.read(addr_bank(0))
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inter := (0 until ICCM_NUM_BANKS).map(i=>Fill(39,read_enable(i))& iccm_mem(i)(addr_bank(i)))
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for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout(i) := RegNext(inter(i))
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io.iccm_bank_addr := addr_bank
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||||
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val redundant_valid = WireInit(UInt(2.W), init = 0.U)
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val redundant_address = Wire(Vec(2, UInt((ICCM_BITS-2).W)))
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redundant_address := (0 until 2).map(i=>0.U)
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Reference in New Issue