axi to ahb update
This commit is contained in:
Laraib Khan
parent
d10e4748be
commit
ea912f6dee
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@ -21,9 +21,7 @@
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
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]
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},
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{
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@ -35,6 +33,13 @@
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
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@ -55,24 +60,6 @@
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
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"sources":[
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"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
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"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
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1709
axi4_to_ahb.fir
1709
axi4_to_ahb.fir
File diff suppressed because it is too large
Load Diff
926
axi4_to_ahb.v
926
axi4_to_ahb.v
File diff suppressed because it is too large
Load Diff
307
rvjtag_tap.fir
307
rvjtag_tap.fir
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@ -3,21 +3,20 @@ circuit rvjtag_tap :
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module rvjtag_tap :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, flip rd_data : UInt<32>, flip rd_status : UInt<2>, flip idle : UInt<3>, flip dmi_stat : UInt<2>, flip jtag_id : UInt<32>, flip version : UInt<4>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<7>, wr_en : UInt<1>, rd_en : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>}
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output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>}
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io.tdo <= UInt<1>("h00") @[rvjtag_tap.scala 38:21]
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io.tdoEnable <= UInt<1>("h00") @[rvjtag_tap.scala 39:21]
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io.wr_data <= UInt<1>("h00") @[rvjtag_tap.scala 40:21]
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io.wr_addr <= UInt<1>("h00") @[rvjtag_tap.scala 41:21]
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io.wr_en <= UInt<1>("h00") @[rvjtag_tap.scala 42:21]
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io.rd_en <= UInt<1>("h00") @[rvjtag_tap.scala 43:21]
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io.dmi_reset <= UInt<1>("h00") @[rvjtag_tap.scala 44:21]
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io.dmi_hard_reset <= UInt<1>("h00") @[rvjtag_tap.scala 45:21]
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reg sr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 48:20]
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reg nsr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 49:20]
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reg dr : UInt<41>, clock with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 50:20]
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wire nsr : UInt<41>
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nsr <= UInt<41>("h00")
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reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55]
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sr <= nsr @[rvjtag_tap.scala 32:55]
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wire dr : UInt<41>
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dr <= UInt<41>("h00")
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wire nstate : UInt<4>
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nstate <= UInt<4>("h00")
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reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57]
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state <= nstate @[rvjtag_tap.scala 39:57]
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wire ir : UInt<5>
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ir <= UInt<1>("h00")
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ir <= UInt<5>("h00")
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wire jtag_reset : UInt<1>
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jtag_reset <= UInt<1>("h00")
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wire shift_dr : UInt<1>
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@ -40,182 +39,234 @@ circuit rvjtag_tap :
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dr_en <= UInt<1>("h00")
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wire devid_sel : UInt<1>
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devid_sel <= UInt<1>("h00")
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reg state : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 75:27]
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reg nstate : UInt, clock with : (reset => (reset, UInt<4>("h00"))) @[rvjtag_tap.scala 76:27]
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nstate <= state @[rvjtag_tap.scala 76:27]
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node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
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when _T : @[Conditional.scala 40:58]
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node _T_1 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 80:21]
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when _T_1 : @[rvjtag_tap.scala 80:32]
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nstate <= UInt<4>("h00") @[rvjtag_tap.scala 80:41]
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skip @[rvjtag_tap.scala 80:32]
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else : @[rvjtag_tap.scala 81:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 81:29]
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skip @[rvjtag_tap.scala 81:20]
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node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46]
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nstate <= _T_1 @[rvjtag_tap.scala 55:40]
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jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
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when _T_2 : @[Conditional.scala 39:67]
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node _T_3 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 84:21]
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when _T_3 : @[rvjtag_tap.scala 84:32]
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nstate <= UInt<4>("h02") @[rvjtag_tap.scala 84:40]
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skip @[rvjtag_tap.scala 84:32]
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else : @[rvjtag_tap.scala 85:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 85:28]
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skip @[rvjtag_tap.scala 85:20]
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node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47]
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nstate <= _T_3 @[rvjtag_tap.scala 57:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
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when _T_4 : @[Conditional.scala 39:67]
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node _T_5 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 88:21]
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when _T_5 : @[rvjtag_tap.scala 88:32]
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nstate <= UInt<4>("h09") @[rvjtag_tap.scala 88:40]
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skip @[rvjtag_tap.scala 88:32]
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else : @[rvjtag_tap.scala 89:20]
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nstate <= UInt<4>("h03") @[rvjtag_tap.scala 89:28]
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skip @[rvjtag_tap.scala 89:20]
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node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47]
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nstate <= _T_5 @[rvjtag_tap.scala 58:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
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when _T_6 : @[Conditional.scala 39:67]
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node _T_7 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 92:21]
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when _T_7 : @[rvjtag_tap.scala 92:32]
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nstate <= UInt<4>("h05") @[rvjtag_tap.scala 92:40]
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skip @[rvjtag_tap.scala 92:32]
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else : @[rvjtag_tap.scala 93:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 93:28]
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skip @[rvjtag_tap.scala 93:20]
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node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47]
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nstate <= _T_7 @[rvjtag_tap.scala 59:41]
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capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
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when _T_8 : @[Conditional.scala 39:67]
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node _T_9 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 96:21]
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when _T_9 : @[rvjtag_tap.scala 96:32]
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nstate <= UInt<4>("h05") @[rvjtag_tap.scala 96:40]
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skip @[rvjtag_tap.scala 96:32]
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else : @[rvjtag_tap.scala 97:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 97:28]
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skip @[rvjtag_tap.scala 97:20]
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node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47]
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nstate <= _T_9 @[rvjtag_tap.scala 61:41]
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shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
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when _T_10 : @[Conditional.scala 39:67]
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node _T_11 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 100:21]
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when _T_11 : @[rvjtag_tap.scala 100:32]
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nstate <= UInt<4>("h08") @[rvjtag_tap.scala 100:40]
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skip @[rvjtag_tap.scala 100:32]
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else : @[rvjtag_tap.scala 101:20]
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nstate <= UInt<4>("h06") @[rvjtag_tap.scala 101:28]
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skip @[rvjtag_tap.scala 101:20]
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node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47]
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nstate <= _T_11 @[rvjtag_tap.scala 63:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
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when _T_12 : @[Conditional.scala 39:67]
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node _T_13 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 104:18]
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when _T_13 : @[rvjtag_tap.scala 104:29]
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nstate <= UInt<4>("h07") @[rvjtag_tap.scala 104:37]
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skip @[rvjtag_tap.scala 104:29]
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else : @[rvjtag_tap.scala 105:20]
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nstate <= UInt<4>("h06") @[rvjtag_tap.scala 105:28]
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skip @[rvjtag_tap.scala 105:20]
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node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47]
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nstate <= _T_13 @[rvjtag_tap.scala 64:41]
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pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
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when _T_14 : @[Conditional.scala 39:67]
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node _T_15 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 108:18]
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when _T_15 : @[rvjtag_tap.scala 108:29]
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nstate <= UInt<4>("h08") @[rvjtag_tap.scala 108:37]
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skip @[rvjtag_tap.scala 108:29]
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else : @[rvjtag_tap.scala 109:20]
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nstate <= UInt<4>("h04") @[rvjtag_tap.scala 109:28]
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skip @[rvjtag_tap.scala 109:20]
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node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47]
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nstate <= _T_15 @[rvjtag_tap.scala 66:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
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when _T_16 : @[Conditional.scala 39:67]
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node _T_17 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 112:18]
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when _T_17 : @[rvjtag_tap.scala 112:29]
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nstate <= UInt<4>("h02") @[rvjtag_tap.scala 112:37]
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skip @[rvjtag_tap.scala 112:29]
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else : @[rvjtag_tap.scala 113:20]
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nstate <= UInt<4>("h01") @[rvjtag_tap.scala 113:28]
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skip @[rvjtag_tap.scala 113:20]
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node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47]
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nstate <= _T_17 @[rvjtag_tap.scala 67:41]
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update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
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when _T_18 : @[Conditional.scala 39:67]
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node _T_19 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 116:18]
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when _T_19 : @[rvjtag_tap.scala 116:29]
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nstate <= UInt<4>("h09") @[rvjtag_tap.scala 116:37]
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skip @[rvjtag_tap.scala 116:29]
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else : @[rvjtag_tap.scala 117:20]
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nstate <= UInt<4>("h0a") @[rvjtag_tap.scala 117:28]
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skip @[rvjtag_tap.scala 117:20]
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node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47]
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nstate <= _T_19 @[rvjtag_tap.scala 69:41]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
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when _T_20 : @[Conditional.scala 39:67]
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node _T_21 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 120:18]
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when _T_21 : @[rvjtag_tap.scala 120:29]
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nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 120:37]
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skip @[rvjtag_tap.scala 120:29]
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else : @[rvjtag_tap.scala 121:20]
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nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 121:28]
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skip @[rvjtag_tap.scala 121:20]
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node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47]
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nstate <= _T_21 @[rvjtag_tap.scala 70:41]
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capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
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when _T_22 : @[Conditional.scala 39:67]
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node _T_23 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 124:18]
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when _T_23 : @[rvjtag_tap.scala 124:29]
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nstate <= UInt<4>("h0c") @[rvjtag_tap.scala 124:37]
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skip @[rvjtag_tap.scala 124:29]
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else : @[rvjtag_tap.scala 125:20]
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nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 125:28]
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skip @[rvjtag_tap.scala 125:20]
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node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47]
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nstate <= _T_23 @[rvjtag_tap.scala 72:41]
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shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16]
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skip @[Conditional.scala 39:67]
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else : @[Conditional.scala 39:67]
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node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
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when _T_24 : @[Conditional.scala 39:67]
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node _T_25 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 128:18]
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when _T_25 : @[rvjtag_tap.scala 128:29]
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nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 128:37]
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skip @[rvjtag_tap.scala 128:29]
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else : @[rvjtag_tap.scala 129:20]
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nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 129:28]
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skip @[rvjtag_tap.scala 129:20]
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node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47]
|
||||
nstate <= _T_25 @[rvjtag_tap.scala 74:41]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
|
||||
when _T_26 : @[Conditional.scala 39:67]
|
||||
node _T_27 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 132:18]
|
||||
when _T_27 : @[rvjtag_tap.scala 132:29]
|
||||
nstate <= UInt<4>("h0e") @[rvjtag_tap.scala 132:37]
|
||||
skip @[rvjtag_tap.scala 132:29]
|
||||
else : @[rvjtag_tap.scala 133:20]
|
||||
nstate <= UInt<4>("h0d") @[rvjtag_tap.scala 133:28]
|
||||
skip @[rvjtag_tap.scala 133:20]
|
||||
node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47]
|
||||
nstate <= _T_27 @[rvjtag_tap.scala 75:41]
|
||||
pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
|
||||
when _T_28 : @[Conditional.scala 39:67]
|
||||
node _T_29 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 136:18]
|
||||
when _T_29 : @[rvjtag_tap.scala 136:29]
|
||||
nstate <= UInt<4>("h0f") @[rvjtag_tap.scala 136:37]
|
||||
skip @[rvjtag_tap.scala 136:29]
|
||||
else : @[rvjtag_tap.scala 137:20]
|
||||
nstate <= UInt<4>("h0b") @[rvjtag_tap.scala 137:28]
|
||||
skip @[rvjtag_tap.scala 137:20]
|
||||
node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47]
|
||||
nstate <= _T_29 @[rvjtag_tap.scala 77:41]
|
||||
skip @[Conditional.scala 39:67]
|
||||
else : @[Conditional.scala 39:67]
|
||||
node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
|
||||
when _T_30 : @[Conditional.scala 39:67]
|
||||
node _T_31 = eq(io.tms, UInt<1>("h01")) @[rvjtag_tap.scala 140:18]
|
||||
when _T_31 : @[rvjtag_tap.scala 140:29]
|
||||
nstate <= UInt<4>("h02") @[rvjtag_tap.scala 140:37]
|
||||
skip @[rvjtag_tap.scala 140:29]
|
||||
else : @[rvjtag_tap.scala 141:20]
|
||||
nstate <= UInt<4>("h01") @[rvjtag_tap.scala 141:28]
|
||||
skip @[rvjtag_tap.scala 141:20]
|
||||
node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47]
|
||||
nstate <= _T_31 @[rvjtag_tap.scala 78:41]
|
||||
update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17]
|
||||
skip @[Conditional.scala 39:67]
|
||||
node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28]
|
||||
io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16]
|
||||
node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93]
|
||||
node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98]
|
||||
node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106]
|
||||
node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123]
|
||||
node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89]
|
||||
node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75]
|
||||
node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56]
|
||||
reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52]
|
||||
_T_40 <= _T_39 @[rvjtag_tap.scala 85:52]
|
||||
ir <= _T_40 @[rvjtag_tap.scala 85:6]
|
||||
node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18]
|
||||
devid_sel <= _T_41 @[rvjtag_tap.scala 86:13]
|
||||
node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22]
|
||||
node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32]
|
||||
node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58]
|
||||
dr_en <= _T_44 @[rvjtag_tap.scala 87:13]
|
||||
node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16]
|
||||
when _T_45 : @[rvjtag_tap.scala 92:23]
|
||||
node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15]
|
||||
node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18]
|
||||
when _T_47 : @[rvjtag_tap.scala 93:28]
|
||||
node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49]
|
||||
node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58]
|
||||
nsr <= _T_49 @[rvjtag_tap.scala 93:33]
|
||||
skip @[rvjtag_tap.scala 93:28]
|
||||
else : @[rvjtag_tap.scala 94:54]
|
||||
node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22]
|
||||
node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25]
|
||||
node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44]
|
||||
node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32]
|
||||
when _T_53 : @[rvjtag_tap.scala 94:54]
|
||||
node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106]
|
||||
node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58]
|
||||
node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58]
|
||||
nsr <= _T_57 @[rvjtag_tap.scala 94:59]
|
||||
skip @[rvjtag_tap.scala 94:54]
|
||||
else : @[rvjtag_tap.scala 95:17]
|
||||
node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58]
|
||||
nsr <= _T_59 @[rvjtag_tap.scala 95:22]
|
||||
skip @[rvjtag_tap.scala 95:17]
|
||||
skip @[rvjtag_tap.scala 92:23]
|
||||
else : @[rvjtag_tap.scala 97:33]
|
||||
node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26]
|
||||
when _T_60 : @[rvjtag_tap.scala 97:33]
|
||||
node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17]
|
||||
when _T_61 : @[rvjtag_tap.scala 98:21]
|
||||
node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58]
|
||||
node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58]
|
||||
node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58]
|
||||
node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58]
|
||||
nsr <= _T_66 @[rvjtag_tap.scala 98:26]
|
||||
skip @[rvjtag_tap.scala 98:21]
|
||||
else : @[rvjtag_tap.scala 99:28]
|
||||
node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24]
|
||||
when _T_67 : @[rvjtag_tap.scala 99:28]
|
||||
node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58]
|
||||
node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58]
|
||||
nsr <= _T_70 @[rvjtag_tap.scala 99:33]
|
||||
skip @[rvjtag_tap.scala 99:28]
|
||||
else : @[rvjtag_tap.scala 100:29]
|
||||
when devid_sel : @[rvjtag_tap.scala 100:29]
|
||||
node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58]
|
||||
node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
nsr <= _T_73 @[rvjtag_tap.scala 100:34]
|
||||
skip @[rvjtag_tap.scala 100:29]
|
||||
skip @[rvjtag_tap.scala 97:33]
|
||||
else : @[rvjtag_tap.scala 102:30]
|
||||
node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23]
|
||||
when _T_74 : @[rvjtag_tap.scala 102:30]
|
||||
node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78]
|
||||
node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58]
|
||||
node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
|
||||
nsr <= _T_78 @[rvjtag_tap.scala 102:35]
|
||||
skip @[rvjtag_tap.scala 102:30]
|
||||
else : @[rvjtag_tap.scala 103:32]
|
||||
node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25]
|
||||
when _T_79 : @[rvjtag_tap.scala 103:32]
|
||||
node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
nsr <= _T_81 @[rvjtag_tap.scala 103:37]
|
||||
skip @[rvjtag_tap.scala 103:32]
|
||||
node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40]
|
||||
reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37]
|
||||
_T_83 <= _T_82 @[rvjtag_tap.scala 106:37]
|
||||
io.tdo <= _T_83 @[rvjtag_tap.scala 106:28]
|
||||
node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89]
|
||||
node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99]
|
||||
node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82]
|
||||
node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104]
|
||||
node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71]
|
||||
reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67]
|
||||
_T_89 <= _T_88 @[rvjtag_tap.scala 108:67]
|
||||
io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57]
|
||||
node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84]
|
||||
node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94]
|
||||
node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77]
|
||||
node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99]
|
||||
node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66]
|
||||
reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62]
|
||||
_T_95 <= _T_94 @[rvjtag_tap.scala 109:62]
|
||||
io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52]
|
||||
node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74]
|
||||
node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84]
|
||||
node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67]
|
||||
node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96]
|
||||
node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58]
|
||||
node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56]
|
||||
reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52]
|
||||
_T_102 <= _T_101 @[rvjtag_tap.scala 111:52]
|
||||
dr <= _T_102 @[rvjtag_tap.scala 111:42]
|
||||
node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19]
|
||||
io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14]
|
||||
node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19]
|
||||
io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14]
|
||||
node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19]
|
||||
io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14]
|
||||
node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19]
|
||||
io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14]
|
||||
|
||||
|
|
|
|||
382
rvjtag_tap.v
382
rvjtag_tap.v
|
|
@ -1,30 +1,382 @@
|
|||
module rvjtag_tap(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_trst,
|
||||
input io_tck,
|
||||
input io_tms,
|
||||
input io_tdi,
|
||||
input [31:0] io_rd_data,
|
||||
output io_dmi_reset,
|
||||
output io_dmi_hard_reset,
|
||||
input [1:0] io_rd_status,
|
||||
input [2:0] io_idle,
|
||||
input [1:0] io_dmi_stat,
|
||||
input [31:0] io_jtag_id,
|
||||
input [2:0] io_idle,
|
||||
input [3:0] io_version,
|
||||
input [30:0] io_jtag_id,
|
||||
input [31:0] io_rd_data,
|
||||
output io_tdo,
|
||||
output io_tdoEnable,
|
||||
output [31:0] io_wr_data,
|
||||
output [6:0] io_wr_addr,
|
||||
output io_wr_en,
|
||||
output io_rd_en,
|
||||
output io_dmi_reset,
|
||||
output io_dmi_hard_reset
|
||||
output [31:0] io_wr_data
|
||||
);
|
||||
assign io_tdo = 1'h0; // @[rvjtag_tap.scala 38:21]
|
||||
assign io_tdoEnable = 1'h0; // @[rvjtag_tap.scala 39:21]
|
||||
assign io_wr_data = 32'h0; // @[rvjtag_tap.scala 40:21]
|
||||
assign io_wr_addr = 7'h0; // @[rvjtag_tap.scala 41:21]
|
||||
assign io_wr_en = 1'h0; // @[rvjtag_tap.scala 42:21]
|
||||
assign io_rd_en = 1'h0; // @[rvjtag_tap.scala 43:21]
|
||||
assign io_dmi_reset = 1'h0; // @[rvjtag_tap.scala 44:21]
|
||||
assign io_dmi_hard_reset = 1'h0; // @[rvjtag_tap.scala 45:21]
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [63:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [63:0] _RAND_6;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg [40:0] sr; // @[rvjtag_tap.scala 32:55]
|
||||
reg [3:0] state; // @[rvjtag_tap.scala 39:57]
|
||||
wire jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_2 = 4'h1 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_4 = 4'h2 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_6 = 4'h3 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_8 = 4'h4 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_10 = 4'h5 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_12 = 4'h6 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_14 = 4'h7 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_16 = 4'h8 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_18 = 4'h9 == state; // @[Conditional.scala 37:30]
|
||||
wire _T_20 = 4'ha == state; // @[Conditional.scala 37:30]
|
||||
wire _T_22 = 4'hb == state; // @[Conditional.scala 37:30]
|
||||
wire _T_24 = 4'hc == state; // @[Conditional.scala 37:30]
|
||||
wire _T_26 = 4'hd == state; // @[Conditional.scala 37:30]
|
||||
wire _T_28 = 4'he == state; // @[Conditional.scala 37:30]
|
||||
wire _T_30 = 4'hf == state; // @[Conditional.scala 37:30]
|
||||
wire _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67]
|
||||
wire _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
|
||||
wire _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67]
|
||||
wire _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
|
||||
wire _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67]
|
||||
wire _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
|
||||
wire _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67]
|
||||
wire _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
|
||||
wire _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67]
|
||||
wire _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
|
||||
wire _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
|
||||
wire _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
|
||||
wire _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67]
|
||||
wire _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
|
||||
wire _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
|
||||
wire _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
|
||||
wire _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
|
||||
wire _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
|
||||
wire _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
|
||||
wire _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
|
||||
wire _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
|
||||
wire _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
|
||||
wire _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
|
||||
wire _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
|
||||
wire _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
|
||||
wire _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
|
||||
wire _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
|
||||
wire _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67]
|
||||
wire _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67]
|
||||
wire _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
|
||||
wire _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
|
||||
wire _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
|
||||
wire _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
|
||||
wire _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67]
|
||||
wire _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
|
||||
wire _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
|
||||
wire _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
|
||||
wire _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
|
||||
wire _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
|
||||
wire _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
|
||||
wire _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
|
||||
wire _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
|
||||
wire _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
|
||||
wire _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
|
||||
wire _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
|
||||
wire capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
|
||||
wire shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58]
|
||||
wire update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
|
||||
wire capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58]
|
||||
wire shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
|
||||
wire update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
|
||||
wire _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98]
|
||||
reg [4:0] ir; // @[rvjtag_tap.scala 85:52]
|
||||
wire devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18]
|
||||
wire _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22]
|
||||
wire _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32]
|
||||
wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58]
|
||||
wire _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32]
|
||||
wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_66 = {26'h0,io_idle,io_dmi_stat,6'h7,io_version}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_70 = {7'h0,io_rd_data,io_rd_status}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58]
|
||||
wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58]
|
||||
reg _T_83; // @[rvjtag_tap.scala 106:37]
|
||||
wire _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82]
|
||||
reg _T_89; // @[rvjtag_tap.scala 108:67]
|
||||
reg _T_95; // @[rvjtag_tap.scala 109:62]
|
||||
wire _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67]
|
||||
reg [40:0] dr; // @[rvjtag_tap.scala 111:52]
|
||||
wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58]
|
||||
assign io_dmi_reset = _T_95; // @[rvjtag_tap.scala 109:52]
|
||||
assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57]
|
||||
assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28]
|
||||
assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16]
|
||||
assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14]
|
||||
assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14]
|
||||
assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {2{`RANDOM}};
|
||||
sr = _RAND_0[40:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
state = _RAND_1[3:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
ir = _RAND_2[4:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
_T_83 = _RAND_3[0:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
_T_89 = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_95 = _RAND_5[0:0];
|
||||
_RAND_6 = {2{`RANDOM}};
|
||||
dr = _RAND_6[40:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (io_trst) begin
|
||||
sr = 41'h0;
|
||||
end
|
||||
if (io_trst) begin
|
||||
state = 4'h0;
|
||||
end
|
||||
if (io_trst) begin
|
||||
ir = 5'h1;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_83 = 1'h0;
|
||||
end
|
||||
if (io_trst) begin
|
||||
_T_89 = 1'h0;
|
||||
end
|
||||
if (io_trst) begin
|
||||
_T_95 = 1'h0;
|
||||
end
|
||||
if (io_trst) begin
|
||||
dr = 41'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
sr <= 41'h0;
|
||||
end else if (shift_dr) begin
|
||||
if (dr_en[1]) begin
|
||||
sr <= _T_49;
|
||||
end else if (_T_53) begin
|
||||
sr <= _T_57;
|
||||
end else begin
|
||||
sr <= _T_59;
|
||||
end
|
||||
end else if (capture_dr) begin
|
||||
if (dr_en[0]) begin
|
||||
sr <= _T_66;
|
||||
end else if (dr_en[1]) begin
|
||||
sr <= _T_70;
|
||||
end else if (devid_sel) begin
|
||||
sr <= _T_73;
|
||||
end else begin
|
||||
sr <= 41'h0;
|
||||
end
|
||||
end else if (shift_ir) begin
|
||||
sr <= _T_78;
|
||||
end else if (capture_ir) begin
|
||||
sr <= 41'h1;
|
||||
end else begin
|
||||
sr <= 41'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
state <= 4'h0;
|
||||
end else if (jtag_reset) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h0;
|
||||
end else begin
|
||||
state <= 4'h1;
|
||||
end
|
||||
end else if (_T_2) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h2;
|
||||
end else begin
|
||||
state <= 4'h1;
|
||||
end
|
||||
end else if (_T_4) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h9;
|
||||
end else begin
|
||||
state <= 4'h3;
|
||||
end
|
||||
end else if (_T_6) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h5;
|
||||
end else begin
|
||||
state <= 4'h4;
|
||||
end
|
||||
end else if (_T_8) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h5;
|
||||
end else begin
|
||||
state <= 4'h4;
|
||||
end
|
||||
end else if (_T_10) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h8;
|
||||
end else begin
|
||||
state <= 4'h6;
|
||||
end
|
||||
end else if (_T_12) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h7;
|
||||
end else begin
|
||||
state <= 4'h6;
|
||||
end
|
||||
end else if (_T_14) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h8;
|
||||
end else begin
|
||||
state <= 4'h4;
|
||||
end
|
||||
end else if (_T_16) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h2;
|
||||
end else begin
|
||||
state <= 4'h1;
|
||||
end
|
||||
end else if (_T_18) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h0;
|
||||
end else begin
|
||||
state <= 4'ha;
|
||||
end
|
||||
end else if (_T_20) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'hc;
|
||||
end else begin
|
||||
state <= 4'hb;
|
||||
end
|
||||
end else if (_T_22) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'hc;
|
||||
end else begin
|
||||
state <= 4'hb;
|
||||
end
|
||||
end else if (_T_24) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'hf;
|
||||
end else begin
|
||||
state <= 4'hd;
|
||||
end
|
||||
end else if (_T_26) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'he;
|
||||
end else begin
|
||||
state <= 4'hd;
|
||||
end
|
||||
end else if (_T_28) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'hf;
|
||||
end else begin
|
||||
state <= 4'hb;
|
||||
end
|
||||
end else if (_T_30) begin
|
||||
if (io_tms) begin
|
||||
state <= 4'h2;
|
||||
end else begin
|
||||
state <= 4'h1;
|
||||
end
|
||||
end else begin
|
||||
state <= 4'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
ir <= 5'h1;
|
||||
end else if (jtag_reset) begin
|
||||
ir <= 5'h1;
|
||||
end else if (update_ir) begin
|
||||
if (_T_34) begin
|
||||
ir <= 5'h1f;
|
||||
end else begin
|
||||
ir <= sr[4:0];
|
||||
end
|
||||
end else begin
|
||||
ir <= 5'h0;
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_83 <= 1'h0;
|
||||
end else begin
|
||||
_T_83 <= sr[0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
_T_89 <= 1'h0;
|
||||
end else begin
|
||||
_T_89 <= _T_86 & sr[17];
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
_T_95 <= 1'h0;
|
||||
end else begin
|
||||
_T_95 <= _T_86 & sr[16];
|
||||
end
|
||||
end
|
||||
always @(posedge io_tck or posedge io_trst) begin
|
||||
if (io_trst) begin
|
||||
dr <= 41'h0;
|
||||
end else if (_T_98) begin
|
||||
dr <= sr;
|
||||
end else begin
|
||||
dr <= _T_100;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -57,9 +57,9 @@ class axi4_to_ahb_IO extends Bundle with Config {
|
|||
|
||||
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
|
||||
val io = IO(new axi4_to_ahb_IO)
|
||||
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8)
|
||||
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
|
||||
val buf_state = WireInit(idle)
|
||||
val buf_nxtstate = RegInit(idle)
|
||||
val buf_nxtstate = WireInit(idle)
|
||||
//logic signals
|
||||
val slave_valid = WireInit(Bool(), init = false.B)
|
||||
val slave_ready = WireInit(Bool(), init = false.B)
|
||||
|
|
@ -178,16 +178,16 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
MuxCase(0.U, temp)
|
||||
}
|
||||
|
||||
// Write buffer
|
||||
wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
|
||||
wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
|
||||
wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
|
||||
wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
|
||||
|
||||
io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
|
||||
io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
|
||||
io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
|
||||
io.axi_rlast := true.B
|
||||
// // Write buffer
|
||||
// wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
|
||||
// wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
|
||||
// wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
|
||||
// wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
|
||||
//
|
||||
// io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
|
||||
// io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
|
||||
// io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
|
||||
// io.axi_rlast := true.B
|
||||
|
||||
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
|
||||
master_valid := wr_cmd_vld | io.axi_arvalid
|
||||
|
|
@ -217,13 +217,28 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
//State machine
|
||||
io.ahb_htrans := 0.U
|
||||
master_ready := 0.U
|
||||
buf_state_en := 0.U
|
||||
//master_ready := 0.U
|
||||
buf_state_en := false.B
|
||||
buf_nxtstate := idle
|
||||
buf_wr_en := 0.U
|
||||
buf_data_wr_en := 0.U
|
||||
slvbuf_error_in := 0.U
|
||||
slvbuf_error_en := 0.U
|
||||
buf_write_in := 0.U
|
||||
cmd_done := 0.U
|
||||
trxn_done := 0.U
|
||||
buf_cmd_byte_ptr_en := 0.U
|
||||
buf_cmd_byte_ptr := 0.U
|
||||
slave_valid_pre := 0.U
|
||||
slvbuf_wr_en := 0.U
|
||||
bypass_en := 0.U
|
||||
rd_bypass_idle := 0.U
|
||||
|
||||
switch(buf_state) {
|
||||
is(idle) {
|
||||
master_ready := 1.U
|
||||
val master_ready = 1.U
|
||||
buf_write_in := (master_opc(2, 1) === "b01".U)
|
||||
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
|
||||
val buf_nxtstate = Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
|
||||
buf_state_en := master_valid & master_ready
|
||||
buf_wr_en := buf_state_en
|
||||
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
|
||||
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|
@ -236,11 +251,11 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
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}
|
||||
|
||||
is(cmd_rd) {
|
||||
buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
|
||||
val buf_nxtstate = Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
|
||||
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
|
||||
cmd_done := buf_state_en & !master_valid
|
||||
slvbuf_wr_en := buf_state_en
|
||||
master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
|
||||
val master_ready = (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
|
||||
buf_wr_en := master_ready
|
||||
bypass_en := master_ready & master_valid
|
||||
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
|
||||
|
|
@ -248,9 +263,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
}
|
||||
|
||||
is(stream_rd) {
|
||||
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
|
||||
val master_ready = (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
|
||||
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
|
||||
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
|
||||
val buf_nxtstate = Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
|
||||
buf_state_en := (ahb_hready_q | ahb_hresp_q)
|
||||
buf_data_wr_en := buf_state_en
|
||||
slvbuf_error_in := ahb_hresp_q
|
||||
|
|
@ -294,7 +309,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
is(data_wr) {
|
||||
buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
|
||||
master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
|
||||
val master_ready = ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
|
||||
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
|
||||
slvbuf_error_in := ahb_hresp_q
|
||||
slvbuf_error_en := buf_state_en
|
||||
|
|
@ -346,6 +361,16 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
slave_tag := slvbuf_tag(TAG - 1, 0)
|
||||
|
||||
last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite
|
||||
// Write buffer
|
||||
wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
|
||||
wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
|
||||
wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
|
||||
wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
|
||||
|
||||
io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
|
||||
io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
|
||||
io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
|
||||
io.axi_rlast := true.B
|
||||
|
||||
//rvdffsc
|
||||
wrbuf_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_en.asBool(),1.U,wrbuf_vld) & !wrbuf_rst, 0.U)}
|
||||
|
|
|
|||
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Reference in New Issue