Update quasar_wrapper.scala
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@ -64,7 +64,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
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val scan_mode = Input(Bool())
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})
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// val core_rst_l = core.io.core_rst_l
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val mem = Module(new quasar.mem())
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val dmi_wrapper = Module(new dmi_wrapper())
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val core = Module(new quasar())
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@ -81,7 +81,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
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core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
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core.io.dmi_reg_en := dmi_wrapper.io.reg_en
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core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
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// core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
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io.jtag_tdo := dmi_wrapper.io.tdo
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// Memory signals
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@ -171,4 +170,4 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
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}
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object QUASAR_Wrp extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
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}
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}
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