colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vwayhit corrected

This commit is contained in:
​Laraib Khan 2021-01-22 14:59:02 +05:00
parent 5ec570e847
commit ef2f0bbbb2
10 changed files with 2286 additions and 2721 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
ifu_bp_ctl.anno.json
View File

@ -1,4 +1,13 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
@ -6,6 +15,13 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
@ -13,13 +29,7 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
@ -29,6 +39,13 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
@ -36,56 +53,7 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
@ -105,35 +73,6 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

3351
ifu_bp_ctl.fir
View File

File diff suppressed because it is too large Load Diff

1425
ifu_bp_ctl.v
View File

File diff suppressed because it is too large Load Diff

119
src/main/scala/ifu/ifu_bp_ctl.scala
View File

@ -370,7 +370,9 @@ if(!BTB_FULLYA) {
val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W))) val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
// Final target if its a RET then pop else take the target pc // Final target if its a RET then pop else take the target pc
io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
// mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction
io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
(Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1))) (Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1)))
// Return stack // Return stack
@ -437,7 +439,11 @@ if(!BTB_FULLYA) {
// Writing is always done from dec or exu check if the dec have a valid data // Writing is always done from dec or exu check if the dec have a valid data
val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr) val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U)) val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
// vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
@ -449,59 +455,60 @@ if(!BTB_FULLYA) {
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i))) btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i))) btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
} }
if(BTB_FULLYA){ // if(BTB_FULLYA){
val fetch_mp_collision_f = WireInit(Bool(),init = false.B) // val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B) // val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
//
// Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks // // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry. // // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U // val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
//
// val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) //
// val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) // // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool())) // // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W))) // val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
btbdata := btbdata.map(i=> 0.U) // val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
val hit0 = WireInit(UInt(1.W) ,init = 0.U) // btbdata := btbdata.map(i=> 0.U)
val hit1 = WireInit(UInt(1.W) ,init = 0.U) // val hit0 = WireInit(UInt(1.W) ,init = 0.U)
// val hit1 = WireInit(UInt(1.W) ,init = 0.U)
// btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i))) //
// val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) // // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
// val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) // // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// hit unless we are also writing this entry at the same time //
val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U)) // // hit unless we are also writing this entry at the same time
val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U)) // val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
// Mux out the 2 potential branches // val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_)) // // Mux out the 2 potential branches
btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_)) // btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U)) // btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U) //
way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f) // vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) | // way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_)) // wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode)) // ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U) //
io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U) // io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
val btb_used_reset = btb_used.andR() //
val btb_used_ns = Mux1H(Seq( // val btb_used_reset = btb_used.andR()
vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)), // val btb_used_ns = Mux1H(Seq(
vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)), // vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
(exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)), // vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
btb_used_reset.asBool -> Fill(BTB_SIZE,0.U), // (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
(!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))), // btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
!(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used // (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
)) // !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb // ))
btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode) // val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
} // btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
// }
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
@ -540,6 +547,6 @@ if(!BTB_FULLYA) {
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
} }
object bp extends App { object bp_MAIN extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl()))
} }

1
src/main/scala/lib/param.scala
View File

@ -161,5 +161,4 @@ trait param {
val BTB_ENABLE = 0x1 val BTB_ENABLE = 0x1
val BTB_TOFFSET_SIZE = 0x00C val BTB_TOFFSET_SIZE = 0x00C
val BTB_FULLYA = 0x00 val BTB_FULLYA = 0x00
} }

BIN
target/scala-2.12/classes/ifu/bp$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/bp$.class → target/scala-2.12/classes/ifu/bp_MAIN$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/bp_MAIN$delayedInit$body.class Normal file
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/bp.class → target/scala-2.12/classes/ifu/bp_MAIN.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_bp_ctl.class
View File

Binary file not shown.