vwayhit corrected
This commit is contained in:
Laraib Khan
parent
5ec570e847
commit
ef2f0bbbb2
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@ -1,4 +1,13 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
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@ -6,6 +15,13 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
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@ -13,13 +29,7 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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@ -29,6 +39,13 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
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@ -36,56 +53,7 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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@ -105,35 +73,6 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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3351
ifu_bp_ctl.fir
3351
ifu_bp_ctl.fir
File diff suppressed because it is too large
Load Diff
1425
ifu_bp_ctl.v
1425
ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -370,6 +370,8 @@ if(!BTB_FULLYA) {
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val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
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rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
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// Final target if its a RET then pop else take the target pc
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// mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction
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io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
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(Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1)))
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@ -437,7 +439,11 @@ if(!BTB_FULLYA) {
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// Writing is always done from dec or exu check if the dec have a valid data
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val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
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vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
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val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
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io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
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// vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
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val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
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val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
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@ -449,59 +455,60 @@ if(!BTB_FULLYA) {
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btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
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btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
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}
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if(BTB_FULLYA){
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val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
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val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
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// Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
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// Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
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val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
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// val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
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// val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
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// val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
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val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
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btbdata := btbdata.map(i=> 0.U)
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val hit0 = WireInit(UInt(1.W) ,init = 0.U)
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val hit1 = WireInit(UInt(1.W) ,init = 0.U)
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// btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
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// val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
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// val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
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// hit unless we are also writing this entry at the same time
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val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
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val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
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// Mux out the 2 potential branches
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btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
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btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
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val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
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vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
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way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
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wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
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((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
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btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
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io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
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io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
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val btb_used_reset = btb_used.andR()
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val btb_used_ns = Mux1H(Seq(
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vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
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vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
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(exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
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btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
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(!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
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!(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
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))
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val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
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btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
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}
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// if(BTB_FULLYA){
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// val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
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// val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
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//
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// // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
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// // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
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// val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
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//
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//
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// // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
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// // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
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// // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
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// val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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// val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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// val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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// val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
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// val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
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// btbdata := btbdata.map(i=> 0.U)
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// val hit0 = WireInit(UInt(1.W) ,init = 0.U)
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// val hit1 = WireInit(UInt(1.W) ,init = 0.U)
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//
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// // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
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// // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
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// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
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//
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||||
// // hit unless we are also writing this entry at the same time
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// val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
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// val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
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// // Mux out the 2 potential branches
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// btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
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// btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
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// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
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//
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// vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
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||||
// way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
|
||||
// wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
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// ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
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// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
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//
|
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// io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
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||||
// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
|
||||
//
|
||||
// val btb_used_reset = btb_used.andR()
|
||||
// val btb_used_ns = Mux1H(Seq(
|
||||
// vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
|
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// vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
|
||||
// (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
|
||||
// btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
|
||||
// (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
|
||||
// !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
|
||||
// ))
|
||||
// val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
|
||||
// btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
|
||||
// }
|
||||
|
||||
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
|
||||
|
||||
|
|
@ -540,6 +547,6 @@ if(!BTB_FULLYA) {
|
|||
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
|
||||
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
|
||||
}
|
||||
object bp extends App {
|
||||
object bp_MAIN extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl()))
|
||||
}
|
||||
|
|
@ -161,5 +161,4 @@ trait param {
|
|||
val BTB_ENABLE = 0x1
|
||||
val BTB_TOFFSET_SIZE = 0x00C
|
||||
val BTB_FULLYA = 0x00
|
||||
|
||||
}
|
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Reference in New Issue