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Predictor hash check

This commit is contained in:
waleed-lm 2020-10-06 11:07:39 +05:00
parent 3e37095f97
commit efa066a687
5 changed files with 63 additions and 62 deletions
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29
el2_ifu_bp_ctl.anno.json
View File

@ -89,6 +89,22 @@
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test2",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_br_error",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
@ -130,19 +146,6 @@
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test2",
"sources":[
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_inst_mask_f",

5
el2_ifu_bp_ctl.fir
View File

@ -230,7 +230,6 @@ circuit el2_ifu_bp_ctl :
node mp_wrindex_dec = dshl(UInt<1>("h01"), io.exu_mp_index) @[el2_ifu_bp_ctl.scala 183:28]
node fetch_wrindex_dec = dshl(UInt<1>("h01"), btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 185:31]
node fetch_wrindex_p1_dec = dshl(UInt<1>("h01"), btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 187:34]
io.test2 <= fetch_wrindex_p1_dec @[el2_ifu_bp_ctl.scala 188:12]
node _T_148 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_149 = mux(_T_148, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node mp_wrlru_b0 = and(mp_wrindex_dec, _T_149) @[el2_ifu_bp_ctl.scala 189:36]
@ -312,10 +311,10 @@ circuit el2_ifu_bp_ctl :
node _T_212 = or(_T_210, _T_211) @[Mux.scala 27:72]
wire tag_match_vway1_expanded_f : UInt<2> @[Mux.scala 27:72]
tag_match_vway1_expanded_f <= _T_212 @[Mux.scala 27:72]
node _T_213 = eq(vwayhit_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 217:47]
node _T_213 = not(vwayhit_f) @[el2_ifu_bp_ctl.scala 217:47]
node _T_214 = and(_T_213, btb_vlru_rd_f) @[el2_ifu_bp_ctl.scala 217:58]
node way_raw = or(tag_match_vway1_expanded_f, _T_214) @[el2_ifu_bp_ctl.scala 217:44]
io.test2 <= btb_vlru_rd_f @[el2_ifu_bp_ctl.scala 220:12]
io.test2 <= way_raw @[el2_ifu_bp_ctl.scala 220:12]
node _T_215 = or(io.ifc_fetch_req_f, exu_mp_valid) @[el2_ifu_bp_ctl.scala 222:75]
node _T_216 = bits(_T_215, 0, 0) @[el2_ifu_bp_ctl.scala 222:90]
reg _T_217 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]

85
el2_ifu_bp_ctl.v
View File

@ -47,7 +47,7 @@ module el2_ifu_bp_ctl(
output [1:0] io_ifu_bp_valid_f,
output [11:0] io_ifu_bp_poffset_f,
output [255:0] io_test1,
output [255:0] io_test2
output [1:0] io_test2
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
@ -6881,9 +6881,8 @@ module el2_ifu_bp_ctl(
wire [1:0] _T_210 = _T_143 ? tag_match_way1_expanded_f : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_211 = io_ifc_fetch_addr_f[0] ? _T_209 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] tag_match_vway1_expanded_f = _T_210 | _T_211; // @[Mux.scala 27:72]
wire _T_213 = vwayhit_f == 2'h0; // @[el2_ifu_bp_ctl.scala 217:47]
wire [1:0] _GEN_1036 = {{1'd0}, _T_213}; // @[el2_ifu_bp_ctl.scala 217:58]
wire [1:0] _T_214 = _GEN_1036 & btb_vlru_rd_f; // @[el2_ifu_bp_ctl.scala 217:58]
wire [1:0] _T_213 = ~vwayhit_f; // @[el2_ifu_bp_ctl.scala 217:47]
wire [1:0] _T_214 = _T_213 & btb_vlru_rd_f; // @[el2_ifu_bp_ctl.scala 217:58]
wire _T_215 = io_ifc_fetch_req_f | exu_mp_valid; // @[el2_ifu_bp_ctl.scala 222:75]
wire [15:0] _T_230 = btb_sel_f[1] ? btb_vbank1_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
wire [15:0] _T_231 = btb_sel_f[0] ? btb_vbank1_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72]
@ -6962,10 +6961,10 @@ module el2_ifu_bp_ctl(
wire [29:0] _T_384 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72]
wire [30:0] _T_385 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 31'h0; // @[Mux.scala 27:72]
wire [29:0] _T_386 = _T_381 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72]
wire [30:0] _GEN_1037 = {{1'd0}, _T_384}; // @[Mux.scala 27:72]
wire [30:0] _T_387 = _GEN_1037 | _T_385; // @[Mux.scala 27:72]
wire [30:0] _GEN_1038 = {{1'd0}, _T_386}; // @[Mux.scala 27:72]
wire [30:0] adder_pc_in_f = _T_387 | _GEN_1038; // @[Mux.scala 27:72]
wire [30:0] _GEN_1036 = {{1'd0}, _T_384}; // @[Mux.scala 27:72]
wire [30:0] _T_387 = _GEN_1036 | _T_385; // @[Mux.scala 27:72]
wire [30:0] _GEN_1037 = {{1'd0}, _T_386}; // @[Mux.scala 27:72]
wire [30:0] adder_pc_in_f = _T_387 | _GEN_1037; // @[Mux.scala 27:72]
wire [31:0] _T_391 = {adder_pc_in_f[29:0],bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_392 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_395 = _T_391[12:1] + _T_392[12:1]; // @[el2_lib.scala 200:31]
@ -7905,8 +7904,8 @@ module el2_ifu_bp_ctl(
wire _T_6473 = _T_6326 & br0_hashed_wb[4]; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6482 = _T_6335 & br0_hashed_wb[4]; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6491 = _T_6344 & br0_hashed_wb[4]; // @[el2_ifu_bp_ctl.scala 380:86]
wire [1:0] _GEN_1039 = {{1'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6499 = _GEN_1039 == 2'h2; // @[el2_ifu_bp_ctl.scala 380:171]
wire [1:0] _GEN_1038 = {{1'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6499 = _GEN_1038 == 2'h2; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6500 = _T_6209 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6509 = _T_6218 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6518 = _T_6227 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
@ -7923,7 +7922,7 @@ module el2_ifu_bp_ctl(
wire _T_6617 = _T_6326 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6626 = _T_6335 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6635 = _T_6344 & _T_6499; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6643 = _GEN_1039 == 2'h3; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6643 = _GEN_1038 == 2'h3; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6644 = _T_6209 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6653 = _T_6218 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6662 = _T_6227 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
@ -7940,8 +7939,8 @@ module el2_ifu_bp_ctl(
wire _T_6761 = _T_6326 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6770 = _T_6335 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6779 = _T_6344 & _T_6643; // @[el2_ifu_bp_ctl.scala 380:86]
wire [2:0] _GEN_1071 = {{2'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6787 = _GEN_1071 == 3'h4; // @[el2_ifu_bp_ctl.scala 380:171]
wire [2:0] _GEN_1070 = {{2'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6787 = _GEN_1070 == 3'h4; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6788 = _T_6209 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6797 = _T_6218 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6806 = _T_6227 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
@ -7958,7 +7957,7 @@ module el2_ifu_bp_ctl(
wire _T_6905 = _T_6326 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6914 = _T_6335 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6923 = _T_6344 & _T_6787; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6931 = _GEN_1071 == 3'h5; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6931 = _GEN_1070 == 3'h5; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_6932 = _T_6209 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6941 = _T_6218 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_6950 = _T_6227 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
@ -7975,7 +7974,7 @@ module el2_ifu_bp_ctl(
wire _T_7049 = _T_6326 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7058 = _T_6335 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7067 = _T_6344 & _T_6931; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7075 = _GEN_1071 == 3'h6; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7075 = _GEN_1070 == 3'h6; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7076 = _T_6209 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7085 = _T_6218 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7094 = _T_6227 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
@ -7992,7 +7991,7 @@ module el2_ifu_bp_ctl(
wire _T_7193 = _T_6326 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7202 = _T_6335 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7211 = _T_6344 & _T_7075; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7219 = _GEN_1071 == 3'h7; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7219 = _GEN_1070 == 3'h7; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7220 = _T_6209 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7229 = _T_6218 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7238 = _T_6227 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8009,8 +8008,8 @@ module el2_ifu_bp_ctl(
wire _T_7337 = _T_6326 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7346 = _T_6335 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7355 = _T_6344 & _T_7219; // @[el2_ifu_bp_ctl.scala 380:86]
wire [3:0] _GEN_1135 = {{3'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7363 = _GEN_1135 == 4'h8; // @[el2_ifu_bp_ctl.scala 380:171]
wire [3:0] _GEN_1134 = {{3'd0}, br0_hashed_wb[4]}; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7363 = _GEN_1134 == 4'h8; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7364 = _T_6209 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7373 = _T_6218 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7382 = _T_6227 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8027,7 +8026,7 @@ module el2_ifu_bp_ctl(
wire _T_7481 = _T_6326 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7490 = _T_6335 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7499 = _T_6344 & _T_7363; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7507 = _GEN_1135 == 4'h9; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7507 = _GEN_1134 == 4'h9; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7508 = _T_6209 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7517 = _T_6218 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7526 = _T_6227 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8044,7 +8043,7 @@ module el2_ifu_bp_ctl(
wire _T_7625 = _T_6326 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7634 = _T_6335 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7643 = _T_6344 & _T_7507; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7651 = _GEN_1135 == 4'ha; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7651 = _GEN_1134 == 4'ha; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7652 = _T_6209 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7661 = _T_6218 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7670 = _T_6227 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8061,7 +8060,7 @@ module el2_ifu_bp_ctl(
wire _T_7769 = _T_6326 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7778 = _T_6335 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7787 = _T_6344 & _T_7651; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7795 = _GEN_1135 == 4'hb; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7795 = _GEN_1134 == 4'hb; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7796 = _T_6209 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7805 = _T_6218 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7814 = _T_6227 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8078,7 +8077,7 @@ module el2_ifu_bp_ctl(
wire _T_7913 = _T_6326 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7922 = _T_6335 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7931 = _T_6344 & _T_7795; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7939 = _GEN_1135 == 4'hc; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7939 = _GEN_1134 == 4'hc; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_7940 = _T_6209 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7949 = _T_6218 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_7958 = _T_6227 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8095,7 +8094,7 @@ module el2_ifu_bp_ctl(
wire _T_8057 = _T_6326 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8066 = _T_6335 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8075 = _T_6344 & _T_7939; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8083 = _GEN_1135 == 4'hd; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8083 = _GEN_1134 == 4'hd; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8084 = _T_6209 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8093 = _T_6218 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8102 = _T_6227 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8112,7 +8111,7 @@ module el2_ifu_bp_ctl(
wire _T_8201 = _T_6326 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8210 = _T_6335 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8219 = _T_6344 & _T_8083; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8227 = _GEN_1135 == 4'he; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8227 = _GEN_1134 == 4'he; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8228 = _T_6209 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8237 = _T_6218 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8246 = _T_6227 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8129,7 +8128,7 @@ module el2_ifu_bp_ctl(
wire _T_8345 = _T_6326 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8354 = _T_6335 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8363 = _T_6344 & _T_8227; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8371 = _GEN_1135 == 4'hf; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8371 = _GEN_1134 == 4'hf; // @[el2_ifu_bp_ctl.scala 380:171]
wire _T_8372 = _T_6209 & _T_8371; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8381 = _T_6218 & _T_8371; // @[el2_ifu_bp_ctl.scala 380:86]
wire _T_8390 = _T_6227 & _T_8371; // @[el2_ifu_bp_ctl.scala 380:86]
@ -8515,8 +8514,8 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_1_14 = _T_11300 | _T_6482; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11316 = _T_11057 & mp_hashed[4]; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_1_15 = _T_11316 | _T_6491; // @[el2_ifu_bp_ctl.scala 383:204]
wire [1:0] _GEN_1487 = {{1'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11331 = _GEN_1487 == 2'h2; // @[el2_ifu_bp_ctl.scala 383:169]
wire [1:0] _GEN_1486 = {{1'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11331 = _GEN_1486 == 2'h2; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11332 = _T_10817 & _T_11331; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_2_0 = _T_11332 | _T_6500; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11348 = _T_10833 & _T_11331; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8549,7 +8548,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_2_14 = _T_11556 | _T_6626; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11572 = _T_11057 & _T_11331; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_2_15 = _T_11572 | _T_6635; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11587 = _GEN_1487 == 2'h3; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11587 = _GEN_1486 == 2'h3; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11588 = _T_10817 & _T_11587; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_3_0 = _T_11588 | _T_6644; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11604 = _T_10833 & _T_11587; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8582,8 +8581,8 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_3_14 = _T_11812 | _T_6770; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11828 = _T_11057 & _T_11587; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_3_15 = _T_11828 | _T_6779; // @[el2_ifu_bp_ctl.scala 383:204]
wire [2:0] _GEN_1551 = {{2'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11843 = _GEN_1551 == 3'h4; // @[el2_ifu_bp_ctl.scala 383:169]
wire [2:0] _GEN_1550 = {{2'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11843 = _GEN_1550 == 3'h4; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_11844 = _T_10817 & _T_11843; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_4_0 = _T_11844 | _T_6788; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_11860 = _T_10833 & _T_11843; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8616,7 +8615,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_4_14 = _T_12068 | _T_6914; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12084 = _T_11057 & _T_11843; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_4_15 = _T_12084 | _T_6923; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12099 = _GEN_1551 == 3'h5; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12099 = _GEN_1550 == 3'h5; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12100 = _T_10817 & _T_12099; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_5_0 = _T_12100 | _T_6932; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12116 = _T_10833 & _T_12099; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8649,7 +8648,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_5_14 = _T_12324 | _T_7058; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12340 = _T_11057 & _T_12099; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_5_15 = _T_12340 | _T_7067; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12355 = _GEN_1551 == 3'h6; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12355 = _GEN_1550 == 3'h6; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12356 = _T_10817 & _T_12355; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_6_0 = _T_12356 | _T_7076; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12372 = _T_10833 & _T_12355; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8682,7 +8681,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_6_14 = _T_12580 | _T_7202; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12596 = _T_11057 & _T_12355; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_6_15 = _T_12596 | _T_7211; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12611 = _GEN_1551 == 3'h7; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12611 = _GEN_1550 == 3'h7; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12612 = _T_10817 & _T_12611; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_7_0 = _T_12612 | _T_7220; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12628 = _T_10833 & _T_12611; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8715,8 +8714,8 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_7_14 = _T_12836 | _T_7346; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12852 = _T_11057 & _T_12611; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_7_15 = _T_12852 | _T_7355; // @[el2_ifu_bp_ctl.scala 383:204]
wire [3:0] _GEN_1679 = {{3'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12867 = _GEN_1679 == 4'h8; // @[el2_ifu_bp_ctl.scala 383:169]
wire [3:0] _GEN_1678 = {{3'd0}, mp_hashed[4]}; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12867 = _GEN_1678 == 4'h8; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_12868 = _T_10817 & _T_12867; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_8_0 = _T_12868 | _T_7364; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_12884 = _T_10833 & _T_12867; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8749,7 +8748,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_8_14 = _T_13092 | _T_7490; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13108 = _T_11057 & _T_12867; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_8_15 = _T_13108 | _T_7499; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13123 = _GEN_1679 == 4'h9; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13123 = _GEN_1678 == 4'h9; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13124 = _T_10817 & _T_13123; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_9_0 = _T_13124 | _T_7508; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13140 = _T_10833 & _T_13123; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8782,7 +8781,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_9_14 = _T_13348 | _T_7634; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13364 = _T_11057 & _T_13123; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_9_15 = _T_13364 | _T_7643; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13379 = _GEN_1679 == 4'ha; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13379 = _GEN_1678 == 4'ha; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13380 = _T_10817 & _T_13379; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_10_0 = _T_13380 | _T_7652; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13396 = _T_10833 & _T_13379; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8815,7 +8814,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_10_14 = _T_13604 | _T_7778; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13620 = _T_11057 & _T_13379; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_10_15 = _T_13620 | _T_7787; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13635 = _GEN_1679 == 4'hb; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13635 = _GEN_1678 == 4'hb; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13636 = _T_10817 & _T_13635; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_11_0 = _T_13636 | _T_7796; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13652 = _T_10833 & _T_13635; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8848,7 +8847,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_11_14 = _T_13860 | _T_7922; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13876 = _T_11057 & _T_13635; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_11_15 = _T_13876 | _T_7931; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13891 = _GEN_1679 == 4'hc; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13891 = _GEN_1678 == 4'hc; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_13892 = _T_10817 & _T_13891; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_12_0 = _T_13892 | _T_7940; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_13908 = _T_10833 & _T_13891; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8881,7 +8880,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_12_14 = _T_14116 | _T_8066; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14132 = _T_11057 & _T_13891; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_12_15 = _T_14132 | _T_8075; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14147 = _GEN_1679 == 4'hd; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14147 = _GEN_1678 == 4'hd; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14148 = _T_10817 & _T_14147; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_13_0 = _T_14148 | _T_8084; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14164 = _T_10833 & _T_14147; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8914,7 +8913,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_13_14 = _T_14372 | _T_8210; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14388 = _T_11057 & _T_14147; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_13_15 = _T_14388 | _T_8219; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14403 = _GEN_1679 == 4'he; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14403 = _GEN_1678 == 4'he; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14404 = _T_10817 & _T_14403; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_14_0 = _T_14404 | _T_8228; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14420 = _T_10833 & _T_14403; // @[el2_ifu_bp_ctl.scala 383:82]
@ -8947,7 +8946,7 @@ module el2_ifu_bp_ctl(
wire bht_bank_sel_0_14_14 = _T_14628 | _T_8354; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14644 = _T_11057 & _T_14403; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_14_15 = _T_14644 | _T_8363; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14659 = _GEN_1679 == 4'hf; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14659 = _GEN_1678 == 4'hf; // @[el2_ifu_bp_ctl.scala 383:169]
wire _T_14660 = _T_10817 & _T_14659; // @[el2_ifu_bp_ctl.scala 383:82]
wire bht_bank_sel_0_15_0 = _T_14660 | _T_8372; // @[el2_ifu_bp_ctl.scala 383:204]
wire _T_14676 = _T_10833 & _T_14659; // @[el2_ifu_bp_ctl.scala 383:82]
@ -9520,7 +9519,7 @@ module el2_ifu_bp_ctl(
assign io_ifu_bp_valid_f = vwayhit_f & _T_344; // @[el2_ifu_bp_ctl.scala 297:21]
assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 310:23]
assign io_test1 = _T_172 & _T_173; // @[el2_ifu_bp_ctl.scala 199:12]
assign io_test2 = {{254'd0}, btb_vlru_rd_f}; // @[el2_ifu_bp_ctl.scala 188:12 el2_ifu_bp_ctl.scala 220:12]
assign io_test2 = tag_match_vway1_expanded_f | _T_214; // @[el2_ifu_bp_ctl.scala 220:12]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif

6
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -185,7 +185,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val fetch_wrindex_dec = 1.U << btb_rd_addr_f
//io.test1 := fetch_wrindex_dec
val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f
io.test2 := fetch_wrindex_p1_dec
//io.test2 := fetch_wrindex_p1_dec
val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
val vwayhit_f = Mux1H(Seq(~io.ifc_fetch_addr_f(0).asBool->wayhit_f,
io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
@ -214,10 +214,10 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val tag_match_vway1_expanded_f = Mux1H(Seq(~io.ifc_fetch_addr_f(0).asBool->tag_match_way1_expanded_f,
io.ifc_fetch_addr_f(0).asBool->Cat(tag_match_way1_expanded_p1_f(0),tag_match_way1_expanded_f(1))))
val way_raw = tag_match_vway1_expanded_f | (!vwayhit_f & btb_vlru_rd_f)
val way_raw = tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f)
//io.test1 := tag_match_vway1_expanded_f
io.test2 := btb_vlru_rd_f
io.test2 := way_raw
btb_lru_b0_f := RegEnable(btb_lru_b0_ns, init = 0.U, (io.ifc_fetch_req_f|exu_mp_valid).asBool)

BIN
target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
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