Dec added
This commit is contained in:
Laraib Khan
parent
6479386424
commit
f23f878f60
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,683 @@
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[
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_unshfl",
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||||
"sources":[
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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||||
]
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||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_packh",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32_w",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
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||||
},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rd",
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||||
"sources":[
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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||||
]
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||||
},
|
||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32_b",
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||||
"sources":[
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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||||
},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zba",
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||||
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_presync",
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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||||
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs1_sign",
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||||
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||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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||||
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ror",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs2",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pc",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_load",
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_clr",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_grev",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_alu",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_mul",
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"sources":[
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_min",
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||||
"sources":[
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]
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},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbp",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clmulr",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_imm12",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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||||
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_gorc",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pcnt",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_beq",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sra",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ebreak",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_by",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sub",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_max",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_write",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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||||
{
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||||
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sll",
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||||
"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbe",
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},
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{
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||||
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_slt",
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||||
"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sext_h",
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"sources":[
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
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||||
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_fence",
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||||
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||||
{
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||||
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||||
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||||
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
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||||
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||||
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||||
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||||
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||||
{
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||||
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||||
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||||
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||||
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||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_packu",
|
||||
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||||
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||||
]
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||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
{
|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
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|
||||
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|
||||
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|
||||
]
|
||||
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|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_blt",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
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|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
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|
||||
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|
||||
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|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbb",
|
||||
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|
||||
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|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_shfl",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ctz",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
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|
||||
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|
||||
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|
||||
]
|
||||
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|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_fence_i",
|
||||
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|
||||
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|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_unsign",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_lxor",
|
||||
"sources":[
|
||||
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|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_mret",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs1",
|
||||
"sources":[
|
||||
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|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_imm",
|
||||
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|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbr",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bge",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pm_alu",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sbinv",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_div",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bfp",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sext_b",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_add",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32c_b",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_land",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sbext",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_half",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sh1add",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_word",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bne",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbc",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sh2add",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bext",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_zbs",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_read",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_lor",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_csr_set",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_srl",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_low",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_ecall",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sbclr",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_crc32c_w",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rol",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_pack",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_condbr",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_legal",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_lsu",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clmulh",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sh3add",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_postsync",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clz",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_sro",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_imm20",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_clmul",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_rs2_sign",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_bdep",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_shimm5",
|
||||
"sources":[
|
||||
"~dec_dec_ctl|dec_dec_ctl>io_ins"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"dec_dec_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,37 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_gpr_ctl|dec_gpr_ctl>io_gpr_exu_gpr_i0_rs1_d",
|
||||
"sources":[
|
||||
"~dec_gpr_ctl|dec_gpr_ctl>io_raddr0"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_gpr_ctl|dec_gpr_ctl>io_gpr_exu_gpr_i0_rs2_d",
|
||||
"sources":[
|
||||
"~dec_gpr_ctl|dec_gpr_ctl>io_raddr1"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"dec_gpr_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"dec_gpr_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,198 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_debug_valid_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_instr_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_instr",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_addr",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_btag",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_btag"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_type_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf_type"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_debug_fence_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_addr",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_fa_index",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_i0_fa_index"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_way",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_way"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_pc4_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_pc4"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_dbecc_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_dbecc"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_ib0_valid_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_valid",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_br_error",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_br_error"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_br_start_error",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_br_start_error"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_icaf_second_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_icaf_second"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_fghr",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_fghr"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_toffset",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_toffset"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_ret",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_ret"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_bank",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_bank"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_ib_exu_dec_i0_pc_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_pc"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_bp_index",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_ifu_i0_bp_index"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_ib_exu_dec_debug_wdata_rs1_d",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_write",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_type",
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_dbg_ib_dbg_cmd_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_hist",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_hist"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_valid",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_ib_ctl|dec_ib_ctl>io_dec_i0_brp_bits_prett",
|
||||
"sources":[
|
||||
"~dec_ib_ctl|dec_ib_ctl>io_ifu_ib_i0_brp_bits_prett"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"dec_ib_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||
circuit dec_ib_ctl :
|
||||
module dec_ib_ctl :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_debug_valid_d : UInt<1>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, flip ifu_i0_fa_index : UInt<9>, dec_i0_bp_fa_index : UInt<9>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_second_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>}
|
||||
|
||||
io.dec_i0_icaf_second_d <= io.ifu_ib.ifu_i0_icaf_second @[dec_ib_ctl.scala 34:35]
|
||||
io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 35:31]
|
||||
io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 36:31]
|
||||
io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 37:31]
|
||||
io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 38:31]
|
||||
io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 39:31]
|
||||
io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 40:31]
|
||||
io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 41:31]
|
||||
io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 42:31]
|
||||
io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 43:31]
|
||||
io.dec_i0_bp_fa_index <= io.ifu_i0_fa_index @[dec_ib_ctl.scala 44:25]
|
||||
node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 58:74]
|
||||
node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 58:48]
|
||||
node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 59:38]
|
||||
node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 59:36]
|
||||
node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 60:36]
|
||||
io.dec_debug_valid_d <= debug_valid @[dec_ib_ctl.scala 61:24]
|
||||
node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 62:62]
|
||||
node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 62:37]
|
||||
node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 63:62]
|
||||
node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 63:37]
|
||||
node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 64:62]
|
||||
node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 64:37]
|
||||
node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 65:62]
|
||||
node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 65:37]
|
||||
node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 67:47]
|
||||
node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 68:47]
|
||||
node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 71:20]
|
||||
node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
|
||||
node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
|
||||
node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 72:21]
|
||||
node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
|
||||
node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
|
||||
node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 73:20]
|
||||
node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
|
||||
node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 74:21]
|
||||
node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
|
||||
node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
|
||||
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
|
||||
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
|
||||
wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
|
||||
ib0_debug_in <= _T_23 @[Mux.scala 27:72]
|
||||
node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 78:54]
|
||||
io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 78:35]
|
||||
node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 81:51]
|
||||
node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 81:43]
|
||||
io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 81:24]
|
||||
node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 83:48]
|
||||
io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 83:22]
|
||||
node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 84:41]
|
||||
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 84:28]
|
||||
io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 84:22]
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
module dec_ib_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_ifu_ib_ifu_i0_icaf,
|
||||
input [1:0] io_ifu_ib_ifu_i0_icaf_type,
|
||||
input io_ifu_ib_ifu_i0_icaf_second,
|
||||
input io_ifu_ib_ifu_i0_dbecc,
|
||||
input [7:0] io_ifu_ib_ifu_i0_bp_index,
|
||||
input [7:0] io_ifu_ib_ifu_i0_bp_fghr,
|
||||
input [4:0] io_ifu_ib_ifu_i0_bp_btag,
|
||||
input io_ifu_ib_ifu_i0_valid,
|
||||
input [31:0] io_ifu_ib_ifu_i0_instr,
|
||||
input [30:0] io_ifu_ib_ifu_i0_pc,
|
||||
input io_ifu_ib_ifu_i0_pc4,
|
||||
input io_ifu_ib_i0_brp_valid,
|
||||
input [11:0] io_ifu_ib_i0_brp_bits_toffset,
|
||||
input [1:0] io_ifu_ib_i0_brp_bits_hist,
|
||||
input io_ifu_ib_i0_brp_bits_br_error,
|
||||
input io_ifu_ib_i0_brp_bits_br_start_error,
|
||||
input io_ifu_ib_i0_brp_bits_bank,
|
||||
input [30:0] io_ifu_ib_i0_brp_bits_prett,
|
||||
input io_ifu_ib_i0_brp_bits_way,
|
||||
input io_ifu_ib_i0_brp_bits_ret,
|
||||
output [30:0] io_ib_exu_dec_i0_pc_d,
|
||||
output io_ib_exu_dec_debug_wdata_rs1_d,
|
||||
input io_dbg_ib_dbg_cmd_valid,
|
||||
input io_dbg_ib_dbg_cmd_write,
|
||||
input [1:0] io_dbg_ib_dbg_cmd_type,
|
||||
input [31:0] io_dbg_ib_dbg_cmd_addr,
|
||||
output io_dec_debug_valid_d,
|
||||
output io_dec_ib0_valid_d,
|
||||
output [1:0] io_dec_i0_icaf_type_d,
|
||||
output [31:0] io_dec_i0_instr_d,
|
||||
output io_dec_i0_pc4_d,
|
||||
output io_dec_i0_brp_valid,
|
||||
output [11:0] io_dec_i0_brp_bits_toffset,
|
||||
output [1:0] io_dec_i0_brp_bits_hist,
|
||||
output io_dec_i0_brp_bits_br_error,
|
||||
output io_dec_i0_brp_bits_br_start_error,
|
||||
output io_dec_i0_brp_bits_bank,
|
||||
output [30:0] io_dec_i0_brp_bits_prett,
|
||||
output io_dec_i0_brp_bits_way,
|
||||
output io_dec_i0_brp_bits_ret,
|
||||
output [7:0] io_dec_i0_bp_index,
|
||||
output [7:0] io_dec_i0_bp_fghr,
|
||||
output [4:0] io_dec_i0_bp_btag,
|
||||
input [8:0] io_ifu_i0_fa_index,
|
||||
output [8:0] io_dec_i0_bp_fa_index,
|
||||
output io_dec_i0_icaf_d,
|
||||
output io_dec_i0_icaf_second_d,
|
||||
output io_dec_i0_dbecc_d,
|
||||
output io_dec_debug_fence_d
|
||||
);
|
||||
wire _T = io_dbg_ib_dbg_cmd_type != 2'h2; // @[dec_ib_ctl.scala 58:74]
|
||||
wire debug_valid = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 58:48]
|
||||
wire _T_1 = ~io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 59:38]
|
||||
wire debug_read = debug_valid & _T_1; // @[dec_ib_ctl.scala 59:36]
|
||||
wire debug_write = debug_valid & io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 60:36]
|
||||
wire _T_2 = io_dbg_ib_dbg_cmd_type == 2'h0; // @[dec_ib_ctl.scala 62:62]
|
||||
wire debug_read_gpr = debug_read & _T_2; // @[dec_ib_ctl.scala 62:37]
|
||||
wire debug_write_gpr = debug_write & _T_2; // @[dec_ib_ctl.scala 63:37]
|
||||
wire _T_4 = io_dbg_ib_dbg_cmd_type == 2'h1; // @[dec_ib_ctl.scala 64:62]
|
||||
wire debug_read_csr = debug_read & _T_4; // @[dec_ib_ctl.scala 64:37]
|
||||
wire debug_write_csr = debug_write & _T_4; // @[dec_ib_ctl.scala 65:37]
|
||||
wire [4:0] dreg = io_dbg_ib_dbg_cmd_addr[4:0]; // @[dec_ib_ctl.scala 67:47]
|
||||
wire [11:0] dcsr = io_dbg_ib_dbg_cmd_addr[11:0]; // @[dec_ib_ctl.scala 68:47]
|
||||
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||
wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72]
|
||||
wire _T_25 = dcsr == 12'h7c4; // @[dec_ib_ctl.scala 81:51]
|
||||
assign io_ib_exu_dec_i0_pc_d = io_ifu_ib_ifu_i0_pc; // @[dec_ib_ctl.scala 37:31]
|
||||
assign io_ib_exu_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[dec_ib_ctl.scala 78:35]
|
||||
assign io_dec_debug_valid_d = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 61:24]
|
||||
assign io_dec_ib0_valid_d = io_ifu_ib_ifu_i0_valid | debug_valid; // @[dec_ib_ctl.scala 83:22]
|
||||
assign io_dec_i0_icaf_type_d = io_ifu_ib_ifu_i0_icaf_type; // @[dec_ib_ctl.scala 39:31]
|
||||
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_ib_ifu_i0_instr; // @[dec_ib_ctl.scala 84:22]
|
||||
assign io_dec_i0_pc4_d = io_ifu_ib_ifu_i0_pc4; // @[dec_ib_ctl.scala 38:31]
|
||||
assign io_dec_i0_brp_valid = io_ifu_ib_i0_brp_valid; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_toffset = io_ifu_ib_i0_brp_bits_toffset; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_hist = io_ifu_ib_i0_brp_bits_hist; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_br_error = io_ifu_ib_i0_brp_bits_br_error; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_br_start_error = io_ifu_ib_i0_brp_bits_br_start_error; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_bank = io_ifu_ib_i0_brp_bits_bank; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_prett = io_ifu_ib_i0_brp_bits_prett; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_way = io_ifu_ib_i0_brp_bits_way; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_brp_bits_ret = io_ifu_ib_i0_brp_bits_ret; // @[dec_ib_ctl.scala 40:31]
|
||||
assign io_dec_i0_bp_index = io_ifu_ib_ifu_i0_bp_index; // @[dec_ib_ctl.scala 41:31]
|
||||
assign io_dec_i0_bp_fghr = io_ifu_ib_ifu_i0_bp_fghr; // @[dec_ib_ctl.scala 42:31]
|
||||
assign io_dec_i0_bp_btag = io_ifu_ib_ifu_i0_bp_btag; // @[dec_ib_ctl.scala 43:31]
|
||||
assign io_dec_i0_bp_fa_index = io_ifu_i0_fa_index; // @[dec_ib_ctl.scala 44:25]
|
||||
assign io_dec_i0_icaf_d = io_ifu_ib_ifu_i0_icaf; // @[dec_ib_ctl.scala 36:31]
|
||||
assign io_dec_i0_icaf_second_d = io_ifu_ib_ifu_i0_icaf_second; // @[dec_ib_ctl.scala 34:35]
|
||||
assign io_dec_i0_dbecc_d = io_ifu_ib_ifu_i0_dbecc; // @[dec_ib_ctl.scala 35:31]
|
||||
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[dec_ib_ctl.scala 81:24]
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_hist_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_path_r",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_rst_vec",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_pc_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_nmi_vec",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_addr",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_npc_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_wr_pause_r",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rddata_d",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_core_id",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_way",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_exu_i0_br_way_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt2",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_extint",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt1",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_presync_d",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_i0_commit_cmt",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_leak_one_wb",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_resume_ack",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt0",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_postsync_d",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_legal_d",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_fail",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_fence_i_wb",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_err_wb",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_core_empty",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_valid",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_mp_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_pmu_i0_br_ataken"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_middle_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt3",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r",
|
||||
"sources":[
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"dec_tlu_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"dec_tlu_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -1,301 +1,325 @@
|
|||
//package dec
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//import lib._
|
||||
//import lsu._
|
||||
//
|
||||
//class dec_IO extends Bundle with lib {
|
||||
// val free_clk = Input(Clock())
|
||||
// val active_clk = Input(Clock())
|
||||
// val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
|
||||
// val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
|
||||
// val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
|
||||
//
|
||||
// val nmi_int = Input(Bool()) // NMI pin
|
||||
// val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
|
||||
//
|
||||
// val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
|
||||
// val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
|
||||
//
|
||||
// val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
|
||||
// val o_cpu_halt_ack = Output(Bool()) // Halt request ack
|
||||
// val o_cpu_run_ack = Output(Bool()) // Run request ack
|
||||
// val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
|
||||
//
|
||||
// val core_id = Input(UInt(28.W)) // [31:4] CORE ID
|
||||
//
|
||||
// val mpc_debug_halt_req = Input(Bool()) // Async halt request
|
||||
// val mpc_debug_run_req = Input(Bool()) // Async run request
|
||||
// val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
|
||||
// val mpc_debug_halt_ack = Output(Bool()) // Halt ack
|
||||
// val mpc_debug_run_ack = Output(Bool()) // Run ack
|
||||
// val debug_brkpt_status = Output(Bool()) // debug breakpoint
|
||||
// val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
|
||||
//
|
||||
//
|
||||
// val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
|
||||
// val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
|
||||
//
|
||||
// val lsu_trigger_match_m = Input(UInt(4.W))
|
||||
// val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||
// val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
|
||||
// val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
||||
// val exu_div_result = Input(UInt(32.W)) // final div result
|
||||
// val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
|
||||
// val lsu_result_m = Input(UInt(32.W)) // load result
|
||||
// val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
|
||||
//
|
||||
// val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
|
||||
// val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
|
||||
//
|
||||
//
|
||||
// val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
|
||||
//
|
||||
// val exu_flush_final = Input(Bool()) // slot0 flush
|
||||
// val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
|
||||
// val soft_int = Input(Bool()) // Software interrupt pending (from pin)
|
||||
//
|
||||
//
|
||||
//
|
||||
// // Debug start
|
||||
// val dbg_halt_req = Input(Bool()) // DM requests a halt
|
||||
// val dbg_resume_req = Input(Bool()) // DM requests a resume
|
||||
// val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
|
||||
// val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
|
||||
// val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
|
||||
// val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
|
||||
// val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
|
||||
//
|
||||
// val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
|
||||
// val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
|
||||
//
|
||||
// val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
|
||||
// val exu_i0_br_way_r = Input(Bool()) // way hit or repl
|
||||
// val lsu_p = Valid(new lsu_pkt_t) // lsu packet
|
||||
// val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
||||
// val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||
// val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||
// val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||
// val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
||||
// val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
||||
// val dec_lsu_valid_raw_d = Output(Bool())
|
||||
// val rv_trace_pkt = (new trace_pkt_t) // trace packet
|
||||
//
|
||||
// // clock gating overrides from mcgc
|
||||
// val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
|
||||
// val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
|
||||
// val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
|
||||
// val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
|
||||
// val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
|
||||
// val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
|
||||
// val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
|
||||
//
|
||||
// val scan_mode = Input(Bool())
|
||||
// val ifu_dec = Flipped(new ifu_dec)
|
||||
// val dec_exu = Flipped(new dec_exu)
|
||||
// val lsu_dec = Flipped (new lsu_dec)
|
||||
// val lsu_tlu = Flipped (new lsu_tlu)
|
||||
// val dec_dbg = new dec_dbg
|
||||
// val dec_dma = new dec_dma
|
||||
// val dec_pic = new dec_pic
|
||||
//}
|
||||
//class dec extends Module with param with RequireAsyncReset{
|
||||
// val io = IO(new dec_IO)
|
||||
//
|
||||
// val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
|
||||
// val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
|
||||
// val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
// val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
//
|
||||
// val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
|
||||
// val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
|
||||
// val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
|
||||
//
|
||||
//
|
||||
// //--------------------------------------------------------------------------//
|
||||
// val instbuff = Module(new dec_ib_ctl)
|
||||
// val decode = Module(new dec_decode_ctl)
|
||||
// val gpr = Module(new dec_gpr_ctl)
|
||||
// val tlu = Module(new dec_tlu_ctl)
|
||||
// val dec_trigger = Module(new dec_trigger)
|
||||
//
|
||||
// //connections for dec_Ib
|
||||
// //inputs
|
||||
// instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
|
||||
// instbuff.io.ib_exu <> io.dec_exu.ib_exu
|
||||
// instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
|
||||
// dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
|
||||
// dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
//
|
||||
// val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
||||
// dontTouch(dec_i0_trigger_match_d)
|
||||
// decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
|
||||
//
|
||||
// decode.io.decode_exu<> io.dec_exu.decode_exu
|
||||
// decode.io.dec_alu<> io.dec_exu.dec_alu
|
||||
// decode.io.dec_div<> io.dec_exu.dec_div
|
||||
// decode.io.dctl_dma <> io.dec_dma.dctl_dma
|
||||
// decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||
// decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
|
||||
// decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
|
||||
// decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
|
||||
// decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
||||
// decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
|
||||
// decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
|
||||
// decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
|
||||
// decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
||||
// decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
|
||||
// decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
|
||||
// decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
|
||||
// decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
|
||||
// decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
|
||||
// decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
|
||||
// decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
|
||||
// decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
|
||||
// decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
|
||||
// decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
|
||||
// decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
|
||||
// decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
|
||||
// decode.io.lsu_idle_any := io.lsu_idle_any
|
||||
// decode.io.lsu_load_stall_any := io.lsu_load_stall_any
|
||||
// decode.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
// decode.io.exu_div_wren := io.exu_div_wren
|
||||
// decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||
// decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
// decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
// decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
|
||||
// decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
||||
// decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
||||
// decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
||||
// decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
|
||||
// decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
// decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||
// decode.io.lsu_result_m := io.lsu_result_m
|
||||
// decode.io.lsu_result_corr_r := io.lsu_result_corr_r
|
||||
// decode.io.exu_flush_final := io.exu_flush_final
|
||||
// decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
|
||||
// decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
||||
// decode.io.free_clk := io.free_clk
|
||||
// decode.io.active_clk := io.active_clk
|
||||
// decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
||||
// decode.io.scan_mode := io.scan_mode
|
||||
// dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
|
||||
// dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
|
||||
// io.lsu_p := decode.io.lsu_p
|
||||
// io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
|
||||
// io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
|
||||
// io.dec_pause_state_cg := decode.io.dec_pause_state_cg
|
||||
// gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
||||
// gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
||||
// gpr.io.wen0 := decode.io.dec_i0_wen_r
|
||||
// gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
||||
// gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
||||
// gpr.io.wen1 := decode.io.dec_nonblock_load_wen
|
||||
// gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
|
||||
// gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data
|
||||
// gpr.io.wen2 := io.exu_div_wren
|
||||
// gpr.io.waddr2 := decode.io.div_waddr_wb
|
||||
// gpr.io.wd2 := io.exu_div_result
|
||||
// gpr.io.scan_mode := io.scan_mode
|
||||
// io.dec_exu.gpr_exu <> gpr.io.gpr_exu
|
||||
// tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
|
||||
// tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
|
||||
// tlu.io.tlu_bp <> io.ifu_dec.dec_bp
|
||||
// tlu.io.tlu_exu <> io.dec_exu.tlu_exu
|
||||
// tlu.io.tlu_dma <> io.dec_dma.tlu_dma
|
||||
// tlu.io.active_clk := io.active_clk
|
||||
// tlu.io.free_clk := io.free_clk
|
||||
// tlu.io.scan_mode := io.scan_mode
|
||||
// tlu.io.rst_vec := io.rst_vec
|
||||
// tlu.io.nmi_int := io.nmi_int
|
||||
// tlu.io.nmi_vec := io.nmi_vec
|
||||
// tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
// tlu.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
// tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
|
||||
// tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
|
||||
// tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
|
||||
// tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
|
||||
// tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
|
||||
// tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
||||
// tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
// io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
|
||||
// io.lsu_tlu <> tlu.io.lsu_tlu
|
||||
// io.dec_pic <> tlu.io.dec_pic
|
||||
// tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
||||
// tlu.io.lsu_fir_error := io.lsu_fir_error
|
||||
// tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
||||
// tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
||||
// tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
||||
// tlu.io.dec_pause_state := decode.io.dec_pause_state
|
||||
// tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
||||
// tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
||||
// tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
||||
// tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
||||
// tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
||||
// tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
||||
// tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
||||
// tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
||||
// tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
||||
// tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
||||
// tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
||||
// tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
|
||||
// tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
|
||||
// tlu.io.dbg_halt_req := io.dbg_halt_req
|
||||
// tlu.io.dbg_resume_req := io.dbg_resume_req
|
||||
// tlu.io.lsu_idle_any := io.lsu_idle_any
|
||||
// tlu.io.dec_div_active := decode.io.dec_div_active
|
||||
// tlu.io.timer_int := io.timer_int
|
||||
// tlu.io.soft_int := io.soft_int
|
||||
// tlu.io.core_id := io.core_id
|
||||
// tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
// tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
// tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
// io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
|
||||
// io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
|
||||
// io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
|
||||
// io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
|
||||
// io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
|
||||
// io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
|
||||
// io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
// io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
||||
// io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
||||
// io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
||||
// io.o_debug_mode_status := tlu.io.o_debug_mode_status
|
||||
// io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
|
||||
// io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
|
||||
// io.debug_brkpt_status := tlu.io.debug_brkpt_status
|
||||
// io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
// io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
|
||||
// io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
|
||||
// io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
|
||||
// io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
|
||||
// dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||
// dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
|
||||
// dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
|
||||
// dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
|
||||
// dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
|
||||
// io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
|
||||
// io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
|
||||
// io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
|
||||
// io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
|
||||
// io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
|
||||
// io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
|
||||
// io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
|
||||
//
|
||||
// //--------------------------------------------------------------------------//
|
||||
//
|
||||
// io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1
|
||||
// io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U)
|
||||
// io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1)
|
||||
// io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1)
|
||||
// io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
|
||||
// io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U)
|
||||
// io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
|
||||
//
|
||||
//
|
||||
// // debug command read data
|
||||
// io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||
//}
|
||||
//
|
||||
//
|
||||
package dec
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
import lsu._
|
||||
|
||||
class dec_IO extends Bundle with lib {
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val free_l2clk = Input(Clock())
|
||||
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
|
||||
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
|
||||
val dec_tlu_core_empty = Output(Bool())
|
||||
val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
|
||||
val ifu_i0_fa_index = Input(UInt(log2Ceil(BTB_SIZE).W))
|
||||
val dec_fa_error_index = Output(UInt(log2Ceil(BTB_SIZE).W))
|
||||
val nmi_int = Input(Bool()) // NMI pin
|
||||
val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
|
||||
val lsu_nonblock_load_data = Input(UInt(32.W))
|
||||
|
||||
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
|
||||
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
|
||||
|
||||
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
|
||||
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
|
||||
val o_cpu_run_ack = Output(Bool()) // Run request ack
|
||||
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
|
||||
|
||||
val core_id = Input(UInt(28.W)) // [31:4] CORE ID
|
||||
|
||||
val mpc_debug_halt_req = Input(Bool()) // Async halt request
|
||||
val mpc_debug_run_req = Input(Bool()) // Async run request
|
||||
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
|
||||
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
|
||||
val mpc_debug_run_ack = Output(Bool()) // Run ack
|
||||
val debug_brkpt_status = Output(Bool()) // debug breakpoint
|
||||
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
|
||||
|
||||
|
||||
val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
|
||||
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
|
||||
|
||||
val lsu_trigger_match_m = Input(UInt(4.W))
|
||||
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||
val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
|
||||
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
||||
val exu_div_result = Input(UInt(32.W)) // final div result
|
||||
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
|
||||
val lsu_result_m = Input(UInt(32.W)) // load result
|
||||
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
|
||||
|
||||
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
|
||||
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
|
||||
|
||||
|
||||
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
|
||||
|
||||
val exu_flush_final = Input(Bool()) // slot0 flush
|
||||
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
|
||||
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
|
||||
|
||||
|
||||
|
||||
// Debug start
|
||||
val dbg_halt_req = Input(Bool()) // DM requests a halt
|
||||
val dbg_resume_req = Input(Bool()) // DM requests a resume
|
||||
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
|
||||
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
|
||||
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
|
||||
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
|
||||
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
|
||||
val dec_csr_rddata_d = Output(UInt(32.W))
|
||||
|
||||
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
|
||||
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
|
||||
|
||||
val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
|
||||
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
|
||||
val lsu_p = Valid(new lsu_pkt_t) // lsu packet
|
||||
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
||||
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
||||
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
||||
val dec_tlu_flush_lower_wb = Output(Bool())
|
||||
val dec_lsu_valid_raw_d = Output(Bool())
|
||||
val trace_rv_trace_pkt = (new trace_pkt_t) // trace packet
|
||||
|
||||
// clock gating overrides from mcgc
|
||||
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
|
||||
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
|
||||
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
|
||||
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
|
||||
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
|
||||
val dec_tlu_picio_clk_override = Output(Bool())
|
||||
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
|
||||
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
|
||||
|
||||
val scan_mode = Input(Bool())
|
||||
val ifu_dec = Flipped(new ifu_dec)
|
||||
val dec_exu = Flipped(new dec_exu)
|
||||
val lsu_dec = Flipped (new lsu_dec)
|
||||
val lsu_tlu = Flipped (new lsu_tlu)
|
||||
val dec_dbg = new dec_dbg
|
||||
val dec_dma = new dec_dma
|
||||
val dec_pic = new dec_pic
|
||||
}
|
||||
class dec extends Module with param with RequireAsyncReset{
|
||||
val io = IO(new dec_IO)
|
||||
|
||||
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
|
||||
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
|
||||
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
|
||||
val dec_tlu_trace_disable = WireInit(Bool(),0.B)
|
||||
// val dec_i0_bp_fa_index = WireInit(UInt(log2Ceil(BTB_SIZE).W),0.U)
|
||||
//val dec_debug_valid_d = WireInit(Bool(),0.B)
|
||||
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------//
|
||||
val instbuff = Module(new dec_ib_ctl)
|
||||
val decode = Module(new dec_decode_ctl)
|
||||
val gpr = Module(new dec_gpr_ctl)
|
||||
val tlu = Module(new dec_tlu_ctl)
|
||||
val dec_trigger = Module(new dec_trigger)
|
||||
|
||||
//connections for dec_Ib
|
||||
//inputs
|
||||
instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
|
||||
instbuff.io.ib_exu <> io.dec_exu.ib_exu
|
||||
instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
|
||||
instbuff.io.ifu_i0_fa_index := io.ifu_i0_fa_index
|
||||
dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
|
||||
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
|
||||
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
||||
dontTouch(dec_i0_trigger_match_d)
|
||||
decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
|
||||
|
||||
decode.io.decode_exu<> io.dec_exu.decode_exu
|
||||
decode.io.dec_alu<> io.dec_exu.dec_alu
|
||||
decode.io.dec_div<> io.dec_exu.dec_div
|
||||
decode.io.dctl_dma <> io.dec_dma.dctl_dma
|
||||
decode.io.dec_tlu_trace_disable := tlu.io.dec_tlu_trace_disable
|
||||
decode.io.dec_debug_valid_d := instbuff.io.dec_debug_fence_d
|
||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||
decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
|
||||
decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
|
||||
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
|
||||
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
||||
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
|
||||
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
|
||||
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
|
||||
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
||||
decode.io.dec_i0_bp_fa_index := instbuff.io.dec_i0_bp_fa_index
|
||||
decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
|
||||
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
|
||||
decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
|
||||
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
|
||||
decode.io.dec_i0_icaf_second_d := instbuff.io.dec_i0_icaf_second_d
|
||||
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
|
||||
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
|
||||
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
|
||||
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
|
||||
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
|
||||
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
|
||||
decode.io.lsu_idle_any := io.lsu_idle_any
|
||||
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
|
||||
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
decode.io.exu_div_wren := io.exu_div_wren
|
||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
|
||||
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
||||
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
||||
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
||||
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
|
||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||
decode.io.lsu_result_m := io.lsu_result_m
|
||||
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
|
||||
decode.io.exu_flush_final := io.exu_flush_final
|
||||
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
|
||||
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
||||
decode.io.free_l2clk := io.free_l2clk
|
||||
decode.io.active_clk := io.active_clk
|
||||
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
||||
decode.io.scan_mode := io.scan_mode
|
||||
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb //for tracer
|
||||
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb //for tracer
|
||||
io.lsu_p := decode.io.lsu_p
|
||||
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
|
||||
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
|
||||
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
|
||||
io.dec_exu.decode_exu.dec_qual_lsu_d := decode.io.decode_exu.dec_qual_lsu_d
|
||||
io.dec_fa_error_index :=decode.io.dec_fa_error_index
|
||||
|
||||
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
||||
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
||||
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
||||
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
||||
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
||||
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
|
||||
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
|
||||
gpr.io.wd1 := io.lsu_nonblock_load_data
|
||||
gpr.io.wen2 := io.exu_div_wren
|
||||
gpr.io.waddr2 := decode.io.div_waddr_wb
|
||||
gpr.io.wd2 := io.exu_div_result
|
||||
gpr.io.scan_mode := io.scan_mode
|
||||
io.dec_exu.gpr_exu <> gpr.io.gpr_exu
|
||||
|
||||
tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
|
||||
tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
|
||||
tlu.io.tlu_bp <> io.ifu_dec.dec_bp
|
||||
tlu.io.tlu_exu <> io.dec_exu.tlu_exu
|
||||
tlu.io.tlu_dma <> io.dec_dma.tlu_dma
|
||||
tlu.io.free_l2clk := io.free_l2clk
|
||||
tlu.io.free_clk := io.free_clk
|
||||
tlu.io.scan_mode := io.scan_mode
|
||||
tlu.io.rst_vec := io.rst_vec
|
||||
tlu.io.nmi_int := io.nmi_int
|
||||
tlu.io.nmi_vec := io.nmi_vec
|
||||
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
tlu.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
|
||||
tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
|
||||
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
|
||||
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
|
||||
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
||||
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
|
||||
io.lsu_tlu <> tlu.io.lsu_tlu
|
||||
io.dec_pic <> tlu.io.dec_pic
|
||||
tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
||||
tlu.io.lsu_fir_error := io.lsu_fir_error
|
||||
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
||||
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
||||
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
||||
tlu.io.dec_pause_state := decode.io.dec_pause_state
|
||||
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
||||
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
||||
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
||||
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
||||
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
||||
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
||||
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
||||
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
||||
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
||||
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
||||
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
||||
tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
|
||||
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
|
||||
tlu.io.dbg_halt_req := io.dbg_halt_req
|
||||
tlu.io.dbg_resume_req := io.dbg_resume_req
|
||||
tlu.io.lsu_idle_any := io.lsu_idle_any
|
||||
tlu.io.dec_div_active := decode.io.dec_div_active
|
||||
tlu.io.timer_int := io.timer_int
|
||||
tlu.io.soft_int := io.soft_int
|
||||
tlu.io.core_id := io.core_id
|
||||
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
|
||||
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
|
||||
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
|
||||
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
|
||||
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
|
||||
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
|
||||
io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
||||
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
||||
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
||||
io.o_debug_mode_status := tlu.io.o_debug_mode_status
|
||||
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
|
||||
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
|
||||
io.debug_brkpt_status := tlu.io.debug_brkpt_status
|
||||
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
|
||||
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
|
||||
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
|
||||
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
|
||||
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
|
||||
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
|
||||
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
|
||||
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
|
||||
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
|
||||
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
|
||||
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
|
||||
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
|
||||
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
|
||||
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
|
||||
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
|
||||
io.dec_tlu_picio_clk_override := tlu.io.dec_tlu_icm_clk_override
|
||||
io.dec_tlu_core_empty := tlu.io.dec_tlu_core_empty
|
||||
io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
io.trace_rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb
|
||||
io.trace_rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb, 0.U)
|
||||
io.trace_rv_trace_pkt.rv_i_valid_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||
io.trace_rv_trace_pkt.rv_i_exception_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||
io.trace_rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
|
||||
io.trace_rv_trace_pkt.rv_i_interrupt_ip := tlu.io.dec_tlu_int_valid_wb1
|
||||
io.trace_rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
|
||||
|
||||
|
||||
// debug command read data
|
||||
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||
}
|
||||
object dec_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -17,105 +17,254 @@ class dec_dec_ctl extends Module with lib{
|
|||
pat.reduce(_&_)
|
||||
}
|
||||
|
||||
io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4))
|
||||
io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) |
|
||||
pattern(List(19,13,-2)) | pattern(List(-13,10,-2)) |
|
||||
pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) |
|
||||
pattern(List(17,13,-2)) | pattern(List(-13,8,-2)) |
|
||||
pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) |
|
||||
io.out.alu := pattern(List(30,24,23,-22,-21,-20,14,-5,4)) | pattern(List(29,-27,-24,4)) |
|
||||
pattern(List(-25,-13,-12,4)) | pattern(List(-30,-25,13,12)) | pattern(List(27,25,14,4)) |
|
||||
pattern(List(29,27,-14,4)) | pattern(List(29,-14,5,4)) | pattern(List(-27,-25,14,4)) |
|
||||
pattern(List(30,-29,-13,4)) | pattern(List(-30,-27,-25,4)) | pattern(List(13,-5,4)) |
|
||||
pattern(List(-12,-5,4)) | pattern(List(2)) | pattern(List(6)) | pattern(List(30,24,23,22,21,20,-5,4)) |
|
||||
pattern(List(-30,29,-24,-23,22,21,20,-5,4)) | pattern(List(-30,24,-23,-22,-21,-20,-5,4))
|
||||
|
||||
io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) | pattern(List(19,13,-2)) |
|
||||
pattern(List(-13,10,-2)) | pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) | pattern(List(17,13,-2)) |
|
||||
pattern(List(-13,8,-2)) | pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) |
|
||||
pattern(List(15,13,-2)) | pattern(List(-4,-3)) | pattern(List(-6,-2))
|
||||
|
||||
io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2))
|
||||
io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) |
|
||||
pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2))
|
||||
io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4)
|
||||
io.out.shimm5 := pattern(List(-13,12,-5,4,-2))
|
||||
io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2))
|
||||
io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3))
|
||||
|
||||
io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) | pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2))
|
||||
|
||||
io.out.rd := pattern(List(-5,-2)) | pattern(List(5,2)) | pattern(List(4))
|
||||
|
||||
io.out.shimm5 := pattern(List(27,-13,12,-5,4,-2)) | pattern(List(-30,-13,12,-5,4,-2)) | pattern(List(14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.imm20 := pattern(List(5,3)) | pattern(List(4,2))
|
||||
|
||||
io.out.pc := pattern(List(-5,-3,2)) | pattern(List(5,3))
|
||||
|
||||
io.out.load := pattern(List(-5,-4,-2))
|
||||
|
||||
io.out.store := pattern(List(-6,5,-4))
|
||||
|
||||
io.out.lsu := pattern(List(-6,-4,-2))
|
||||
io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) |
|
||||
pattern(List(-30,-25,-14,-13,-12,-6,4,-2))
|
||||
io.out.sub := pattern(List(30,-12,-6,5,4,-2)) | pattern(List(-25,-14,13,-6,4,-2)) |
|
||||
pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2))
|
||||
io.out.land := pattern(List(14,13,12,-5,-2)) | pattern(List(-25,14,13,12,-6,-2))
|
||||
io.out.lor := pattern(List(-6,3)) | pattern(List(-25,14,13,-12,-6,-2)) |
|
||||
pattern(List(5,4,2)) | pattern(List(-13,-12,6,4)) |
|
||||
pattern(List(14,13,-12,-5,-2))
|
||||
io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2))
|
||||
io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2))
|
||||
io.out.sra := pattern(List(30,-13,12,-6,4,-2))
|
||||
io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2))
|
||||
io.out.slt := pattern(List(-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2))
|
||||
io.out.unsign := pattern(List(-14,13,12,-5,-2)) | pattern(List(13,6,-4,-2)) |
|
||||
pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) |
|
||||
pattern(List(25,14,12,-6,5,-2))
|
||||
|
||||
io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) | pattern(List(-30,-25,-14,-13,-12,-6,4,-2))
|
||||
|
||||
io.out.sub := pattern(List(30,-14,-12,-6,5,4,-2)) | pattern(List(-29,-25,-14,13,-6,4,-2)) |
|
||||
pattern(List(27,25,14,-6,5,-2)) | pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2))
|
||||
|
||||
io.out.land := pattern(List(-27,-25,14,13,12,-6,-2)) | pattern(List(14,13,12,-5,-2))
|
||||
|
||||
io.out.lor := pattern(List(-6,3)) | pattern(List(-29,-27,-25,14,13,-12,-6,-2)) | pattern(List(5,4,2)) |
|
||||
pattern(List(-13,-12,6,4)) | pattern(List(14,13,-12,-5,-2))
|
||||
|
||||
io.out.lxor := pattern(List(-29,-27,-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2))
|
||||
|
||||
io.out.sll := pattern(List(-29,-27,-25,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.sra := pattern(List(30,-29,-27,-13,12,-6,4,-2))
|
||||
|
||||
io.out.srl := pattern(List(-30,-29,-27,-25,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.slt := pattern(List(-29,-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2))
|
||||
|
||||
io.out.unsign := pattern(List(-27,25,14,12,-6,5,-2)) | pattern(List(-14,13,12,-5,-2)) |
|
||||
pattern(List(13,6,-4,-2)) | pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) |
|
||||
pattern(List(27,25,14,13,-6,5,-2))
|
||||
|
||||
io.out.condbr := pattern(List(6,-4,-2))
|
||||
|
||||
io.out.beq := pattern(List(-14,-12,6,-4,-2))
|
||||
|
||||
io.out.bne := pattern(List(-14,12,6,-4,-2))
|
||||
|
||||
io.out.bge := pattern(List(14,12,5,-4,-2))
|
||||
|
||||
io.out.blt := pattern(List(14,-12,5,-4,-2))
|
||||
|
||||
io.out.jal := pattern(List(6,2))
|
||||
|
||||
io.out.by := pattern(List(-13,-12,-6,-4,-2))
|
||||
|
||||
io.out.half := pattern(List(12,-6,-4,-2))
|
||||
|
||||
io.out.word := pattern(List(13,-6,-4))
|
||||
io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) |
|
||||
pattern(List(8,6,4)) | pattern(List(9,6,4)) | pattern(List(10,6,4)) |
|
||||
pattern(List(11,6,4))
|
||||
|
||||
io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) | pattern(List(8,6,4)) |
|
||||
pattern(List(9,6,4)) | pattern(List(10,6,4)) | pattern(List(11,6,4))
|
||||
|
||||
io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) |
|
||||
pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) |
|
||||
pattern(List(19,13,12,6,4))
|
||||
pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) | pattern(List(19,13,12,6,4))
|
||||
|
||||
io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) | pattern(List(17,-12,6,4)) |
|
||||
pattern(List(18,-12,6,4)) | pattern(List(19,-12,6,4))
|
||||
|
||||
io.out.csr_write := pattern(List(-13,12,6,4))
|
||||
io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) |
|
||||
pattern(List(16,14,6,4)) | pattern(List(17,14,6,4)) |
|
||||
pattern(List(18,14,6,4)) | pattern(List(19,14,6,4))
|
||||
io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) |
|
||||
pattern(List(17,-12,6,4)) | pattern(List(18,-12,6,4)) |
|
||||
pattern(List(19,-12,6,4))
|
||||
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4))
|
||||
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4))
|
||||
io.out.mret := pattern(List(29,-13,-12,6,4))
|
||||
io.out.mul := pattern(List(25,-14,-6,5,4,-2))
|
||||
io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)) |
|
||||
pattern(List(25,-14,-13,12,-6,4,-2))
|
||||
io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2))
|
||||
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2))
|
||||
io.out.div := pattern(List(25,14,-6,5,-2))
|
||||
io.out.rem := pattern(List(25,14,13,-6,5,-2))
|
||||
io.out.fence := pattern(List(-5,3))
|
||||
io.out.fence_i := pattern(List(12,-5,3))
|
||||
io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(4,2)) |
|
||||
pattern(List(-25,-6,4)) | pattern(List(-5,4))
|
||||
io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) |
|
||||
pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) |
|
||||
pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) |
|
||||
pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) |
|
||||
pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) |
|
||||
pattern(List(19,13,6,4))
|
||||
io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) |
|
||||
pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) |
|
||||
pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) |
|
||||
pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) |
|
||||
pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
|
||||
|
||||
io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) | pattern(List(16,14,6,4)) |
|
||||
pattern(List(17,14,6,4)) | pattern(List(18,14,6,4)) | pattern(List(19,14,6,4))
|
||||
|
||||
io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) |
|
||||
pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) |
|
||||
pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
|
||||
pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
|
||||
io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||
|
||||
io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) |
|
||||
pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) |
|
||||
pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
|
||||
pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
|
||||
|
||||
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4))
|
||||
|
||||
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4))
|
||||
|
||||
io.out.mret := pattern(List(29,-13,-12,6,4))
|
||||
|
||||
io.out.mul := pattern(List(-30,27,24,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-24,23,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(29,27,-24,-20,14,-13,12,-5,4,-2)) | pattern(List(27,-25,13,-12,-6,5,4,-2)) |
|
||||
pattern(List(30,27,13,-6,5,4,-2)) | pattern(List(29,27,22,-20,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(29,27,-21,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-22,21,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(30,29,27,-23,14,-13,12,-5,4,-2)) | pattern(List(-30,27,23,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(-30,-29,27,-25,-13,12,-6,4,-2)) | pattern(List(25,-14,-6,5,4,-2)) |
|
||||
pattern(List(30,-27,24,-14,-13,12,-5,4,-2)) | pattern(List(29,27,14,-6,5,-2))
|
||||
|
||||
io.out.rs1_sign := pattern(List(-27,25,-14,13,-12,-6,5,4,-2)) | pattern(List(-27,25,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.rs2_sign := pattern(List(-27,25,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2))
|
||||
|
||||
io.out.div := pattern(List(-27,25,14,-6,5,-2))
|
||||
|
||||
io.out.rem := pattern(List(-27,25,14,13,-6,5,-2))
|
||||
|
||||
io.out.fence := pattern(List(-5,3))
|
||||
|
||||
io.out.fence_i := pattern(List(12,-5,3))
|
||||
|
||||
io.out.clz := pattern(List(30,-27,-24,-22,-21,-20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.ctz := pattern(List(30,-27,-24,-22,20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.pcnt := pattern(List(30,-27,-24,21,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.sext_b := pattern(List(30,-27,22,-20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.sext_h := pattern(List(30,-27,22,20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.slo := pattern(List(-30,29,-27,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.sro := pattern(List(-30,29,-27,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.min := pattern(List(27,25,14,-12,-6,5,-2))
|
||||
|
||||
io.out.max := pattern(List(27,25,14,12,-6,5,-2))
|
||||
|
||||
io.out.pack := pattern(List(-30,27,-25,-13,-12,5,4,-2))
|
||||
|
||||
io.out.packu := pattern(List(30,27,-13,-12,5,4,-2))
|
||||
|
||||
io.out.packh := pattern(List(-30,27,-25,13,12,-6,5,-2))
|
||||
|
||||
io.out.rol := pattern(List(30,-27,-14,12,-6,5,4,-2))
|
||||
|
||||
io.out.ror := pattern(List(30,29,-27,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.zbb := pattern(List(30,-27,-24,-14,-13,12,-5,4,-2)) | pattern(List(-30,27,14,13,12,-6,5,-2)) |
|
||||
pattern(List(30,29,-27,14,-13,12,-5,4,-2)) | pattern(List(27,-13,-12,5,4,-2)) |
|
||||
pattern(List(30,14,-13,-12,-6,5,-2)) | pattern(List(30,-27,13,-6,5,4,-2)) |
|
||||
pattern(List(30,29,-27,-6,5,4,-2)) | pattern(List(30,29,24,23,22,21,20,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(-30,29,27,-24,-23,22,21,20,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(-30,27,24,-23,-22,-21,-20,14,-13,12,-5,4,-2)) |
|
||||
pattern(List(30,29,24,23,-22,-21,-20,14,-13,12,-5,4,-2)) | pattern(List(27,25,14,-6,5,-2))
|
||||
|
||||
io.out.sbset := pattern(List(-30,29,27,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.sbclr := pattern(List(30,-29,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.sbinv := pattern(List(30,29,27,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.sbext := pattern(List(30,-29,27,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.zbs := pattern(List(29,27,-14,-13,12,-6,4,-2)) | pattern(List(30,-29,27,-13,12,-6,4,-2))
|
||||
|
||||
io.out.bext := pattern(List(-30,27,-25,13,-12,-6,5,4,-2))
|
||||
|
||||
io.out.bdep := pattern(List(30,27,13,-12,-6,5,4,-2))
|
||||
|
||||
io.out.zbe := pattern(List(27,-25,13,-12,-6,5,4,-2))
|
||||
|
||||
io.out.clmul := pattern(List(27,25,-14,-13,-6,5,4,-2))
|
||||
|
||||
io.out.clmulh := pattern(List(27,-14,13,12,-6,5,-2))
|
||||
|
||||
io.out.clmulr := pattern(List(27,-14,-12,-6,5,4,-2))
|
||||
|
||||
io.out.zbc := pattern(List(27,25,-14,-6,5,4,-2))
|
||||
|
||||
io.out.grev := pattern(List(30,29,27,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.gorc := pattern(List(-30,29,27,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.shfl := pattern(List(-30,-29,27,-25,-14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.unshfl := pattern(List(-30,-29,27,-25,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.zbp := pattern(List(-30,29,-27,-13,12,-5,4,-2)) | pattern(List(-30,-29,27,-13,12,-5,4,-2)) |
|
||||
pattern(List(30,-27,13,-6,5,4,-2)) | pattern(List(27,-25,-13,-12,5,4,-2)) |
|
||||
pattern(List(30,14,-13,-12,5,4,-2)) | pattern(List(29,-27,12,-6,5,4,-2)) |
|
||||
pattern(List(-30,-29,27,-25,12,-6,5,4,-2)) | pattern(List(29,14,-13,12,-6,4,-2))
|
||||
|
||||
io.out.crc32_b := pattern(List(30,-27,24,-23,-21,-20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.crc32_h := pattern(List(30,-27,24,-23,20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.crc32_w := pattern(List(30,-27,24,-23,21,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.crc32c_b := pattern(List(30,-27,23,-21,-20,-14,-13,12,-5 ,4,-2))
|
||||
|
||||
io.out.crc32c_h := pattern(List(30,-27,23,20,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.crc32c_w := pattern(List(30,-27,23,21,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.zbr := pattern(List(30,-27,24,-14,-13,12,-5,4,-2))
|
||||
|
||||
io.out.bfp := pattern(List(30,27,13,12,-6,5,-2))
|
||||
|
||||
io.out.zbf := pattern(List(30,27,13,12,-6,5,-2))
|
||||
|
||||
io.out.sh1add := pattern(List(29,-14,-12,-6,5,4,-2))
|
||||
|
||||
io.out.sh2add := pattern(List(29,14,-13,-12,5,4,-2))
|
||||
|
||||
io.out.sh3add := pattern(List(29,14,13,-6,5,-2))
|
||||
|
||||
io.out.zba := pattern(List(29,-12,-6,5,4,-2))
|
||||
|
||||
io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(-30,-29,-27,-25,-6,4)) |
|
||||
pattern(List(-29,-27,-25,-13,12,-6,4)) | pattern(List(-29,-27,-25,-14,-6,4)) |
|
||||
pattern(List(13,-5,4)) | pattern(List(4,2)) | pattern(List(-12,-5,4))
|
||||
|
||||
|
||||
io.out.legal := pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)) |
|
||||
pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)) |
|
||||
pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) |
|
||||
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) |
|
||||
pattern(List(14,6,5,-4,-3,-2,1,0)) |
|
||||
pattern(List(-12,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-14,-13,5,-4,-3,-2,1,0)) |
|
||||
pattern(List(12,6,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-31,29,-28,-26,-25,24,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,24,-22,-21,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-31,29,-28,-26,-25,-23,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,-24,-23,-21,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-26,25,13,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-26,-25,-24,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-31,-30,-28,-27,-26,-25,14,-12,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-27,-26,-25,13,-12,-6,4,-3,1,0)) |
|
||||
pattern(List(-31,-29,-28,-27,-26,-25,-13,-12,-6,4,-3,1,0)) | pattern(List(-31,-28,-27,-26,-25,14,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-26,-13,12,5,4,-3,-2,1,0)) | pattern(List(-31,-30,-29,-28,-26,14,-6,5,4,-3,1,0)) |
|
||||
pattern(List(-31,30,-28,27,-26,-25,-13,12,-6,4,-3,1,0)) | pattern(List(-31,29,-28,27,-26,-25 ,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-31,-30,-28,-27,-26,-25,-6,-5,4,-3,1,0)) | pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) |
|
||||
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) | pattern(List(-31,-29,-28,-26,-25,14,-6,5,4,-3,1,0)) |
|
||||
pattern(List(-31,29,-28,-26,-25,-13,12,5,4,-3,-2,1,0)) | pattern(List(14,6,5,-4,-3,-2,1,0)) |
|
||||
pattern(List(-14,-13,5,-4,-3,-2,1,0)) | pattern(List(-12,-6,-5,4,-3,1,0)) | pattern(List(-13,12,6,5,-3,-2,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
|
||||
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
|
||||
pattern(List(13,6,5,4,-3,-2,1,0)) |
|
||||
pattern(List(-13,-6,-5,-4,-3,-2,1,0)) |
|
||||
pattern(List(6,5,-4,3,2,1,0)) |
|
||||
pattern(List(13,-6,-5,4,-3,1,0)) |
|
||||
pattern(List(-14,-12,-6,-4,-3,-2,1,0)) |
|
||||
pattern(List(-6,4,-3,2,1,0))
|
||||
pattern(List(13,6,5,4,-3,-2,1,0)) | pattern(List(6,5,-4,3,2,1,0)) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)) |
|
||||
pattern(List(-13,-6,-5,-4,-3,-2,1,0)) | pattern(List(13,-6,-5,4,-3,1,0)) | pattern(List(-6,4,-3,2,1,0))
|
||||
|
||||
}
|
||||
object dec_dec extends App {
|
||||
(new chisel3.stage.ChiselStage).emitVerilog(new dec_dec_ctl())
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -10,6 +10,8 @@ class dec_ib_ctl_IO extends Bundle with param{
|
|||
val ifu_ib = Flipped(new aln_ib)
|
||||
val ib_exu = Flipped(new ib_exu)
|
||||
val dbg_ib = new dbg_ib
|
||||
val dec_debug_valid_d =Output(UInt(1.W))
|
||||
|
||||
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
|
||||
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
|
||||
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
||||
|
|
@ -18,15 +20,18 @@ class dec_ib_ctl_IO extends Bundle with param{
|
|||
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
val ifu_i0_fa_index =Input(UInt(log2Ceil(BTB_SIZE).W))
|
||||
val dec_i0_bp_fa_index =Output(UInt(log2Ceil(BTB_SIZE).W))
|
||||
|
||||
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
|
||||
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_icaf_second_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
|
||||
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
|
||||
}
|
||||
|
||||
class dec_ib_ctl extends Module with param{
|
||||
val io=IO(new dec_ib_ctl_IO)
|
||||
io.dec_i0_icaf_f1_d :=io.ifu_ib.ifu_i0_icaf_f1
|
||||
io.dec_i0_icaf_second_d :=io.ifu_ib.ifu_i0_icaf_second
|
||||
io.dec_i0_dbecc_d :=io.ifu_ib.ifu_i0_dbecc
|
||||
io.dec_i0_icaf_d :=io.ifu_ib.ifu_i0_icaf
|
||||
io.ib_exu.dec_i0_pc_d :=io.ifu_ib.ifu_i0_pc
|
||||
|
|
@ -36,6 +41,7 @@ class dec_ib_ctl extends Module with param{
|
|||
io.dec_i0_bp_index :=io.ifu_ib.ifu_i0_bp_index
|
||||
io.dec_i0_bp_fghr :=io.ifu_ib.ifu_i0_bp_fghr
|
||||
io.dec_i0_bp_btag :=io.ifu_ib.ifu_i0_bp_btag
|
||||
io.dec_i0_bp_fa_index := io.ifu_i0_fa_index
|
||||
|
||||
// GPR accesses
|
||||
// put reg to read on rs1
|
||||
|
|
@ -52,7 +58,7 @@ class dec_ib_ctl extends Module with param{
|
|||
val debug_valid =io.dbg_ib.dbg_cmd_valid & (io.dbg_ib.dbg_cmd_type =/= 2.U)
|
||||
val debug_read =debug_valid & !io.dbg_ib.dbg_cmd_write
|
||||
val debug_write =debug_valid & io.dbg_ib.dbg_cmd_write
|
||||
|
||||
io.dec_debug_valid_d := debug_valid
|
||||
val debug_read_gpr = debug_read & (io.dbg_ib.dbg_cmd_type===0.U)
|
||||
val debug_write_gpr = debug_write & (io.dbg_ib.dbg_cmd_type===0.U)
|
||||
val debug_read_csr = debug_read & (io.dbg_ib.dbg_cmd_type===1.U)
|
||||
|
|
@ -77,5 +83,4 @@ class dec_ib_ctl extends Module with param{
|
|||
io.dec_ib0_valid_d := io.ifu_ib.ifu_i0_valid | debug_valid
|
||||
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_ib.ifu_i0_instr)
|
||||
|
||||
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,12 +21,11 @@ class exu extends Module with lib with RequireAsyncReset{
|
|||
val exu_div_wren = Output(UInt(1.W)) // Divide write enable to GPR
|
||||
//debug
|
||||
val dbg_cmd_wrdata = Input(UInt(32.W)) // Debug data to primary I0 RS1
|
||||
val dec_csr_rddata_d = Input(UInt(32.W))
|
||||
//lsu
|
||||
val lsu_exu = Flipped(new lsu_exu())
|
||||
//ifu_ifc
|
||||
val exu_flush_path_final = Output(UInt(31.W)) // Target for the oldest flush source
|
||||
val dec_qual_lsu_d = Input(Bool())
|
||||
|
||||
})
|
||||
|
||||
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
|
||||
|
|
@ -112,14 +111,14 @@ class exu extends Module with lib with RequireAsyncReset{
|
|||
dontTouch(i0_rs2_d)
|
||||
|
||||
io.lsu_exu.exu_lsu_rs1_d:=Mux1H(Seq(
|
||||
(!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
|
||||
(i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs1_bypass_data_d,
|
||||
(io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W))
|
||||
(!i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs1_en_d & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs1_d,
|
||||
(i0_rs1_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> i0_rs1_bypass_data_d,
|
||||
(io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> Cat(io.dec_exu.tlu_exu.dec_tlu_meihap,0.U(2.W))
|
||||
))
|
||||
|
||||
io.lsu_exu.exu_lsu_rs2_d:=Mux1H(Seq(
|
||||
(!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d & io.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
|
||||
(i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_qual_lsu_d).asBool -> i0_rs2_bypass_data_d
|
||||
(!i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_i0_rs2_en_d & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> io.dec_exu.gpr_exu.gpr_i0_rs2_d,
|
||||
(i0_rs2_bypass_en_d & !io.dec_exu.decode_exu.dec_extint_stall & io.dec_exu.decode_exu.dec_qual_lsu_d).asBool -> i0_rs2_bypass_data_d
|
||||
))
|
||||
|
||||
val muldiv_rs1_d=Mux1H(Seq(
|
||||
|
|
@ -129,10 +128,12 @@ class exu extends Module with lib with RequireAsyncReset{
|
|||
|
||||
val i_alu=Module(new exu_alu_ctl())
|
||||
i_alu.io.dec_alu <> io.dec_exu.dec_alu
|
||||
|
||||
i_alu.io.scan_mode :=io.scan_mode
|
||||
i_alu.io.enable :=x_data_en
|
||||
i_alu.io.pp_in :=i0_predict_newp_d
|
||||
i_alu.io.flush_upper_x :=i0_flush_upper_x
|
||||
i_alu.io.csr_rddata_in :=io.dec_csr_rddata_d
|
||||
i_alu.io.dec_tlu_flush_lower_r :=io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
i_alu.io.a_in :=i0_rs1_d.asSInt
|
||||
i_alu.io.b_in :=i0_rs2_d
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
|
|||
val io = IO(new Bundle{
|
||||
val dec_alu = new dec_alu()
|
||||
|
||||
//val csr_rddata_in = Input(UInt(32.W)) // CSR data
|
||||
val csr_rddata_in = Input(UInt(32.W)) // CSR data
|
||||
val dec_i0_pc_d = Input(UInt(31.W)) // for pc=pc+2,4 calculations
|
||||
val scan_mode = Input(UInt(1.W)) // Scan control
|
||||
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
|
||||
|
|
@ -156,7 +156,7 @@ class exu_alu_ctl extends Module with lib with RequireAsyncReset{
|
|||
|
||||
|
||||
val lout = Mux1H(Seq(
|
||||
io.dec_alu.dec_csr_ren_d -> io.dec_alu.dec_csr_rddata_d.asSInt ,
|
||||
io.dec_alu.dec_csr_ren_d -> io.csr_rddata_in.asSInt ,
|
||||
(io.i0_ap.land & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt & io.b_in.asSInt) ,
|
||||
(io.i0_ap.lor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt | io.b_in.asSInt) ,
|
||||
(io.i0_ap.lxor & !ap_zbb).asBool -> (Cat(0.U(1.W),io.a_in).asSInt ^ io.b_in.asSInt) ,
|
||||
|
|
|
|||
|
|
@ -343,7 +343,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
|
|||
|
||||
val icaf_eff = alignicaf(1) | aligndbecc(1)
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1
|
||||
io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
|
||||
|
||||
io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
|
||||
|
||||
|
|
|
|||
|
|
@ -205,7 +205,6 @@ class dctl_busbuff extends Bundle with lib{
|
|||
val lsu_nonblock_load_data_valid = Output(Bool())
|
||||
val lsu_nonblock_load_data_error = Output(Bool())
|
||||
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||
val lsu_nonblock_load_data = Output(UInt(32.W))
|
||||
}
|
||||
class lsu_tlu extends Bundle {
|
||||
val lsu_pmu_load_external_m = Output(Bool())
|
||||
|
|
@ -247,7 +246,7 @@ class ic_mem extends Bundle with lib {
|
|||
class aln_ib extends Bundle with lib{
|
||||
val ifu_i0_icaf = Output(Bool())
|
||||
val ifu_i0_icaf_type = Output(UInt(2.W))
|
||||
val ifu_i0_icaf_f1 = Output(Bool())
|
||||
val ifu_i0_icaf_second = Output(Bool())
|
||||
val ifu_i0_dbecc = Output(Bool())
|
||||
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
|
||||
|
|
@ -298,12 +297,12 @@ class dma_ifc extends Bundle{
|
|||
}
|
||||
|
||||
class trace_pkt_t extends Bundle{
|
||||
val rv_i_valid_ip = Output(UInt(2.W) )
|
||||
val rv_i_valid_ip = Output(UInt(1.W) )
|
||||
val rv_i_insn_ip = Output(UInt(32.W) )
|
||||
val rv_i_address_ip = Output(UInt(32.W) )
|
||||
val rv_i_exception_ip = Output(UInt(2.W) )
|
||||
val rv_i_exception_ip = Output(UInt(1.W) )
|
||||
val rv_i_ecause_ip = Output(UInt(5.W) )
|
||||
val rv_i_interrupt_ip = Output(UInt(2.W) )
|
||||
val rv_i_interrupt_ip = Output(UInt(1.W) )
|
||||
val rv_i_tval_ip = Output(UInt(32.W) )
|
||||
}
|
||||
|
||||
|
|
@ -326,7 +325,7 @@ class dbg_dctl extends Bundle{
|
|||
class dec_alu extends Bundle {
|
||||
val dec_i0_alu_decode_d = Input(UInt(1.W)) // Valid
|
||||
val dec_csr_ren_d = Input(Bool()) // extra decode
|
||||
val dec_csr_rddata_d = Input(UInt(32.W))
|
||||
// val dec_csr_rddata_d = Input(UInt(32.W))
|
||||
val dec_i0_br_immed_d = Input(UInt(12.W)) // Branch offset
|
||||
val exu_i0_pc_x = Output(UInt(31.W)) // flopped PC
|
||||
}
|
||||
|
|
@ -372,6 +371,7 @@ class decode_exu extends Bundle with lib{
|
|||
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
|
||||
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
|
||||
val dec_i0_result_r =Input(UInt(32.W)) // DEC result in R-stage
|
||||
val dec_qual_lsu_d = Input(Bool())
|
||||
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
|
||||
val dec_i0_rs1_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
val dec_i0_rs2_bypass_en_d =Input(UInt(4.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
|
|
@ -469,7 +469,7 @@ class predict_pkt_t extends Bundle {
|
|||
class trap_pkt_t extends Bundle {
|
||||
val legal = UInt(1.W)
|
||||
val icaf = UInt(1.W)
|
||||
val icaf_f1 = UInt(1.W)
|
||||
val icaf_second = UInt(1.W)
|
||||
val icaf_type = UInt(2.W)
|
||||
val fence_i = UInt(1.W)
|
||||
val i0trigger = UInt(4.W)
|
||||
|
|
@ -478,7 +478,6 @@ class trap_pkt_t extends Bundle {
|
|||
val pmu_divide = UInt(1.W)
|
||||
val pmu_lsu_misaligned = UInt(1.W)
|
||||
}
|
||||
|
||||
class dest_pkt_t extends Bundle {
|
||||
val i0rd = UInt(5.W)
|
||||
val i0load = UInt(1.W)
|
||||
|
|
@ -819,9 +818,9 @@ class dec_tlu_csr_pkt extends Bundle{
|
|||
val csr_mitcnt0 =UInt(1.W)
|
||||
val csr_mitcnt1 =UInt(1.W)
|
||||
val csr_mpmc =UInt(1.W)
|
||||
val csr_mcpc =UInt(1.W)
|
||||
// val csr_mcpc =UInt(1.W)
|
||||
val csr_meicpct =UInt(1.W)
|
||||
val csr_mdeau =UInt(1.W)
|
||||
// val csr_mdeau =UInt(1.W)
|
||||
val csr_micect =UInt(1.W)
|
||||
val csr_miccmect =UInt(1.W)
|
||||
val csr_mdccmect =UInt(1.W)
|
||||
|
|
|
|||
|
|
@ -1,358 +1,358 @@
|
|||
package lsu
|
||||
|
||||
import lib._
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import mem._
|
||||
|
||||
class lsu extends Module with RequireAsyncReset with param with lib {
|
||||
val io = IO (new Bundle {
|
||||
val clk_override = Input(Bool())
|
||||
val lsu_dma = new lsu_dma
|
||||
val lsu_pic = new lsu_pic
|
||||
val lsu_exu = new lsu_exu
|
||||
val lsu_dec = new lsu_dec
|
||||
val dccm = Flipped(new mem_lsu)
|
||||
val lsu_tlu = new lsu_tlu
|
||||
val axi = new axi_channels(LSU_BUS_TAG)
|
||||
|
||||
val dec_tlu_flush_lower_r = Input(Bool())
|
||||
val dec_tlu_i0_kill_writeb_r = Input(Bool())
|
||||
val dec_tlu_force_halt = Input(Bool())
|
||||
|
||||
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||
|
||||
val dec_lsu_offset_d = Input(UInt(12.W))
|
||||
val lsu_p = Flipped(Valid(new lsu_pkt_t()))
|
||||
val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t()))
|
||||
|
||||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
val dec_tlu_mrac_ff = Input(UInt(32.W))
|
||||
|
||||
//Outputs
|
||||
val lsu_result_m = Output(UInt(32.W))
|
||||
val lsu_result_corr_r = Output(UInt(32.W))
|
||||
val lsu_load_stall_any = Output(Bool())
|
||||
val lsu_store_stall_any = Output(Bool())
|
||||
val lsu_fastint_stall_any = Output(Bool())
|
||||
val lsu_idle_any = Output(Bool())
|
||||
val lsu_active = Output(Bool())
|
||||
val lsu_fir_addr = Output(UInt(31.W))
|
||||
val lsu_fir_error = Output(UInt(2.W))
|
||||
val lsu_single_ecc_error_incr = Output(Bool())
|
||||
val lsu_error_pkt_r = Valid(new lsu_error_pkt_t())
|
||||
val lsu_pmu_misaligned_m = Output(Bool())
|
||||
val lsu_trigger_match_m = Output(UInt(4.W))
|
||||
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
|
||||
val scan_mode = Input(Bool())
|
||||
val active_clk = Input(Clock())
|
||||
|
||||
})
|
||||
val dma_dccm_wdata = WireInit(0.U(64.W))
|
||||
val dma_dccm_wdata_lo = WireInit(0.U(32.W))
|
||||
val dma_dccm_wdata_hi = WireInit(0.U(32.W))
|
||||
val dma_mem_tag_m = WireInit(0.U(3.W))
|
||||
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
|
||||
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
|
||||
val lsu_busm_clken = WireInit(0.U(1.W))
|
||||
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
|
||||
val lsu_addr_d = WireInit(0.U(32.W))
|
||||
val lsu_addr_m = WireInit(0.U(32.W))
|
||||
val lsu_addr_r = WireInit(0.U(32.W))
|
||||
val end_addr_d = WireInit(0.U(32.W))
|
||||
val end_addr_m = WireInit(0.U(32.W))
|
||||
val end_addr_r = WireInit(0.U(32.W))
|
||||
val lsu_busreq_r = WireInit(Bool(),false.B)
|
||||
|
||||
val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
|
||||
io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
|
||||
io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
|
||||
val dccm_ctl = Module(new lsu_dccm_ctl())
|
||||
val stbuf = Module(new lsu_stbuf())
|
||||
val ecc = Module(new lsu_ecc())
|
||||
val trigger = Module(new lsu_trigger())
|
||||
val clkdomain = Module(new lsu_clkdomain())
|
||||
val bus_intf = Module(new lsu_bus_intf())
|
||||
|
||||
val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR
|
||||
val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR
|
||||
|
||||
// block stores in decode - for either bus or stbuf reasons
|
||||
io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
|
||||
|
||||
// Ready to accept dma trxns
|
||||
// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
|
||||
val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
|
||||
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
|
||||
io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||
val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
|
||||
val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||
dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
|
||||
dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
|
||||
|
||||
val flush_m_up = io.dec_tlu_flush_lower_r
|
||||
val flush_r = io.dec_tlu_i0_kill_writeb_r
|
||||
|
||||
// lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
|
||||
// Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
|
||||
// Store buffer now have only non-dma dccm stores
|
||||
// stbuf_empty not needed since it has only dccm stores
|
||||
|
||||
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
|
||||
io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
|
||||
// Instantiate the store buffer
|
||||
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r))
|
||||
// Disable Forwarding for now
|
||||
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
// Bus signals
|
||||
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
|
||||
// Dual signals
|
||||
val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2)
|
||||
val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2)
|
||||
val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2)
|
||||
// PMU signals
|
||||
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
|
||||
io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
|
||||
|
||||
//LSU_LSC_Control
|
||||
//Inputs
|
||||
lsu_lsc_ctl.io.clk_override := io.clk_override
|
||||
lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
|
||||
lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk
|
||||
lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r
|
||||
lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r
|
||||
lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r
|
||||
lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||
lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m
|
||||
lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m
|
||||
lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||
lsu_lsc_ctl.io.flush_m_up := flush_m_up
|
||||
lsu_lsc_ctl.io.flush_r := flush_r
|
||||
lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d
|
||||
lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
|
||||
lsu_lsc_ctl.io.lsu_p <> io.lsu_p
|
||||
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
|
||||
lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
|
||||
lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m
|
||||
lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl
|
||||
lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
|
||||
lsu_lsc_ctl.io.scan_mode := io.scan_mode
|
||||
//Outputs
|
||||
lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
end_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
end_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
end_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
|
||||
io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||
io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr
|
||||
io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error
|
||||
// DCCM Control
|
||||
//Inputs
|
||||
dccm_ctl.io.clk_override := io.clk_override
|
||||
dccm_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
dccm_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk
|
||||
dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d
|
||||
dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d
|
||||
dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m
|
||||
dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r
|
||||
dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r
|
||||
dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r
|
||||
dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
dccm_ctl.io.lsu_addr_d := lsu_addr_d
|
||||
dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0)
|
||||
dccm_ctl.io.lsu_addr_r := lsu_addr_r
|
||||
dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0)
|
||||
dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0)
|
||||
dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0)
|
||||
dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||
dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any
|
||||
dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||
dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any
|
||||
dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m
|
||||
dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m
|
||||
dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m
|
||||
dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m
|
||||
dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||
dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r
|
||||
dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r
|
||||
dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r
|
||||
dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r
|
||||
dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff
|
||||
dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff
|
||||
dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff
|
||||
dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff
|
||||
dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||
dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m
|
||||
dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m
|
||||
dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||
dccm_ctl.io.dma_dccm_wen := dma_dccm_wen
|
||||
dccm_ctl.io.dma_pic_wen := dma_pic_wen
|
||||
dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m
|
||||
dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||
dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||
dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi
|
||||
dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo
|
||||
dccm_ctl.io.scan_mode := io.scan_mode
|
||||
//Outputs
|
||||
io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl
|
||||
io.dccm <> dccm_ctl.io.dccm
|
||||
io.lsu_pic <> dccm_ctl.io.lsu_pic
|
||||
//Store Buffer
|
||||
//Inputs
|
||||
stbuf.io.ldst_dual_d := ldst_dual_d
|
||||
stbuf.io.ldst_dual_m := ldst_dual_m
|
||||
stbuf.io.ldst_dual_r := ldst_dual_r
|
||||
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||
stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r
|
||||
stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r
|
||||
stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
|
||||
stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
|
||||
stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
|
||||
stbuf.io.lsu_addr_d := lsu_addr_d
|
||||
stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
stbuf.io.end_addr_d := end_addr_d
|
||||
stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||
stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||
stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
stbuf.io.lsu_cmpen_m := lsu_cmpen_m
|
||||
stbuf.io.scan_mode := io.scan_mode
|
||||
|
||||
// ECC
|
||||
//Inputs
|
||||
ecc.io.clk_override := io.clk_override
|
||||
ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||
ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
|
||||
ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
|
||||
ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
ecc.io.lsu_addr_r := lsu_addr_r
|
||||
ecc.io.end_addr_r := end_addr_r
|
||||
ecc.io.lsu_addr_m := lsu_addr_m
|
||||
ecc.io.end_addr_m := end_addr_m
|
||||
ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r
|
||||
ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r
|
||||
ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m
|
||||
ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m
|
||||
ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r
|
||||
ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r
|
||||
ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m
|
||||
ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m
|
||||
ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r
|
||||
ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m
|
||||
ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
ecc.io.dma_dccm_wen := dma_dccm_wen
|
||||
ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||
ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||
ecc.io.scan_mode := io.scan_mode
|
||||
|
||||
//Trigger
|
||||
//Inputs
|
||||
trigger.io.trigger_pkt_any <> io.trigger_pkt_any
|
||||
trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||
//Outputs
|
||||
io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m
|
||||
|
||||
//Clock Domain
|
||||
//Inputs
|
||||
clkdomain.io.active_clk := io.active_clk
|
||||
clkdomain.io.clk_override := io.clk_override
|
||||
clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req
|
||||
clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
|
||||
clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||
clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any
|
||||
clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any
|
||||
clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any
|
||||
clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any
|
||||
clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
clkdomain.io.lsu_p := io.lsu_p
|
||||
clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
clkdomain.io.scan_mode := io.scan_mode
|
||||
|
||||
//Bus Interface
|
||||
//Inputs
|
||||
bus_intf.io.scan_mode := io.scan_mode
|
||||
io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
|
||||
bus_intf.io.clk_override := io.clk_override
|
||||
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
bus_intf.io.lsu_busm_clken := lsu_busm_clken
|
||||
bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken
|
||||
bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
|
||||
bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
|
||||
bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk
|
||||
bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
bus_intf.io.active_clk := io.active_clk
|
||||
bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
|
||||
bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
bus_intf.io.lsu_busreq_m := lsu_busreq_m
|
||||
bus_intf.io.ldst_dual_d := ldst_dual_d
|
||||
bus_intf.io.ldst_dual_m := ldst_dual_m
|
||||
bus_intf.io.ldst_dual_r := ldst_dual_r
|
||||
bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r)
|
||||
bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r)
|
||||
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r)
|
||||
bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m
|
||||
bus_intf.io.flush_m_up := flush_m_up
|
||||
bus_intf.io.flush_r := flush_r
|
||||
//Outputs
|
||||
io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
|
||||
lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
io.axi <> bus_intf.io.axi
|
||||
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
|
||||
withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}
|
||||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
|
||||
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
|
||||
|
||||
}
|
||||
object lsu_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
|
||||
}
|
||||
//package lsu
|
||||
//
|
||||
//import lib._
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//import mem._
|
||||
//
|
||||
//class lsu extends Module with RequireAsyncReset with param with lib {
|
||||
// val io = IO (new Bundle {
|
||||
// val clk_override = Input(Bool())
|
||||
// val lsu_dma = new lsu_dma
|
||||
// val lsu_pic = new lsu_pic
|
||||
// val lsu_exu = new lsu_exu
|
||||
// val lsu_dec = new lsu_dec
|
||||
// val dccm = Flipped(new mem_lsu)
|
||||
// val lsu_tlu = new lsu_tlu
|
||||
// val axi = new axi_channels(LSU_BUS_TAG)
|
||||
//
|
||||
// val dec_tlu_flush_lower_r = Input(Bool())
|
||||
// val dec_tlu_i0_kill_writeb_r = Input(Bool())
|
||||
// val dec_tlu_force_halt = Input(Bool())
|
||||
//
|
||||
// val dec_tlu_core_ecc_disable = Input(Bool())
|
||||
//
|
||||
// val dec_lsu_offset_d = Input(UInt(12.W))
|
||||
// val lsu_p = Flipped(Valid(new lsu_pkt_t()))
|
||||
// val trigger_pkt_any = Input(Vec(4, new trigger_pkt_t()))
|
||||
//
|
||||
// val dec_lsu_valid_raw_d = Input(Bool())
|
||||
// val dec_tlu_mrac_ff = Input(UInt(32.W))
|
||||
//
|
||||
// //Outputs
|
||||
// val lsu_result_m = Output(UInt(32.W))
|
||||
// val lsu_result_corr_r = Output(UInt(32.W))
|
||||
// val lsu_load_stall_any = Output(Bool())
|
||||
// val lsu_store_stall_any = Output(Bool())
|
||||
// val lsu_fastint_stall_any = Output(Bool())
|
||||
// val lsu_idle_any = Output(Bool())
|
||||
// val lsu_active = Output(Bool())
|
||||
// val lsu_fir_addr = Output(UInt(31.W))
|
||||
// val lsu_fir_error = Output(UInt(2.W))
|
||||
// val lsu_single_ecc_error_incr = Output(Bool())
|
||||
// val lsu_error_pkt_r = Valid(new lsu_error_pkt_t())
|
||||
// val lsu_pmu_misaligned_m = Output(Bool())
|
||||
// val lsu_trigger_match_m = Output(UInt(4.W))
|
||||
//
|
||||
// val lsu_bus_clk_en = Input(Bool())
|
||||
//
|
||||
// val scan_mode = Input(Bool())
|
||||
// val active_clk = Input(Clock())
|
||||
//
|
||||
// })
|
||||
// val dma_dccm_wdata = WireInit(0.U(64.W))
|
||||
// val dma_dccm_wdata_lo = WireInit(0.U(32.W))
|
||||
// val dma_dccm_wdata_hi = WireInit(0.U(32.W))
|
||||
// val dma_mem_tag_m = WireInit(0.U(3.W))
|
||||
// val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
|
||||
// val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
|
||||
// val lsu_busm_clken = WireInit(0.U(1.W))
|
||||
// val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
|
||||
// val lsu_addr_d = WireInit(0.U(32.W))
|
||||
// val lsu_addr_m = WireInit(0.U(32.W))
|
||||
// val lsu_addr_r = WireInit(0.U(32.W))
|
||||
// val end_addr_d = WireInit(0.U(32.W))
|
||||
// val end_addr_m = WireInit(0.U(32.W))
|
||||
// val end_addr_r = WireInit(0.U(32.W))
|
||||
// val lsu_busreq_r = WireInit(Bool(),false.B)
|
||||
//
|
||||
// val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
|
||||
// io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
|
||||
// io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
|
||||
// val dccm_ctl = Module(new lsu_dccm_ctl())
|
||||
// val stbuf = Module(new lsu_stbuf())
|
||||
// val ecc = Module(new lsu_ecc())
|
||||
// val trigger = Module(new lsu_trigger())
|
||||
// val clkdomain = Module(new lsu_clkdomain())
|
||||
// val bus_intf = Module(new lsu_bus_intf())
|
||||
//
|
||||
// val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR
|
||||
// val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR
|
||||
//
|
||||
// // block stores in decode - for either bus or stbuf reasons
|
||||
// io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
// io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
// io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
|
||||
//
|
||||
// // Ready to accept dma trxns
|
||||
// // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
|
||||
// val dma_mem_tag_d = io.lsu_dma.dma_mem_tag
|
||||
// val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
|
||||
// io.lsu_dma.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||
// val dma_dccm_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d & io.lsu_dma.dma_lsc_ctl.dma_mem_sz(1)
|
||||
// val dma_pic_wen = io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||
// dma_dccm_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata >> Cat(io.lsu_dma.dma_lsc_ctl.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
// dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
|
||||
// dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
|
||||
//
|
||||
// val flush_m_up = io.dec_tlu_flush_lower_r
|
||||
// val flush_r = io.dec_tlu_i0_kill_writeb_r
|
||||
//
|
||||
// // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
|
||||
// // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
|
||||
// // Store buffer now have only non-dma dccm stores
|
||||
// // stbuf_empty not needed since it has only dccm stores
|
||||
//
|
||||
// io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any
|
||||
// io.lsu_active := (lsu_lsc_ctl.io.lsu_pkt_m.valid | lsu_lsc_ctl.io.lsu_pkt_r.valid | dccm_ctl.io.ld_single_ecc_error_r_ff) | !bus_intf.io.lsu_bus_buffer_empty_any // This includes DMA. Used for gating top clock
|
||||
// // Instantiate the store buffer
|
||||
// val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & (!lsu_lsc_ctl.io.lsu_pkt_r.bits.dma | ((lsu_lsc_ctl.io.lsu_pkt_r.bits.by | lsu_lsc_ctl.io.lsu_pkt_r.bits.half) & !ecc.io.lsu_double_ecc_error_r))
|
||||
// // Disable Forwarding for now
|
||||
// val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
// // Bus signals
|
||||
// val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
|
||||
// // Dual signals
|
||||
// val ldst_dual_d = lsu_addr_d(2) =/= end_addr_d(2)
|
||||
// val ldst_dual_m = lsu_addr_m(2) =/= end_addr_m(2)
|
||||
// val ldst_dual_r = lsu_addr_r(2) =/= end_addr_r(2)
|
||||
// // PMU signals
|
||||
// io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
// io.lsu_tlu.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
|
||||
// io.lsu_tlu.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
|
||||
//
|
||||
// //LSU_LSC_Control
|
||||
// //Inputs
|
||||
// lsu_lsc_ctl.io.clk_override := io.clk_override
|
||||
// lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
|
||||
// lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
// lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
// lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
// lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk
|
||||
// lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r
|
||||
// lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r
|
||||
// lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r
|
||||
// lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||
// lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m
|
||||
// lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m
|
||||
// lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||
// lsu_lsc_ctl.io.flush_m_up := flush_m_up
|
||||
// lsu_lsc_ctl.io.flush_r := flush_r
|
||||
// lsu_lsc_ctl.io.ldst_dual_d := ldst_dual_d
|
||||
// lsu_lsc_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
// lsu_lsc_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
// lsu_lsc_ctl.io.lsu_exu <> io.lsu_exu
|
||||
// lsu_lsc_ctl.io.lsu_p <> io.lsu_p
|
||||
// lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
// lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
|
||||
// lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
|
||||
// lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m
|
||||
// lsu_lsc_ctl.io.dma_lsc_ctl <> io.lsu_dma.dma_lsc_ctl
|
||||
// lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
|
||||
// lsu_lsc_ctl.io.scan_mode := io.scan_mode
|
||||
// //Outputs
|
||||
// lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
// lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
// lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
// end_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||
// end_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
// end_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
// io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
|
||||
// io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||
// io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr
|
||||
// io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error
|
||||
// // DCCM Control
|
||||
// //Inputs
|
||||
// dccm_ctl.io.clk_override := io.clk_override
|
||||
// dccm_ctl.io.ldst_dual_m := ldst_dual_m
|
||||
// dccm_ctl.io.ldst_dual_r := ldst_dual_r
|
||||
// dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
// dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
// dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
// dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
// dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_store_c1_r_clk
|
||||
// dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
// dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
// dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d
|
||||
// dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
// dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
// dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d
|
||||
// dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m
|
||||
// dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r
|
||||
// dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r
|
||||
// dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r
|
||||
// dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
// dccm_ctl.io.lsu_addr_d := lsu_addr_d
|
||||
// dccm_ctl.io.lsu_addr_m := lsu_addr_m(DCCM_BITS-1,0)
|
||||
// dccm_ctl.io.lsu_addr_r := lsu_addr_r
|
||||
// dccm_ctl.io.end_addr_d := end_addr_d(DCCM_BITS-1,0)
|
||||
// dccm_ctl.io.end_addr_m := end_addr_m(DCCM_BITS-1,0)
|
||||
// dccm_ctl.io.end_addr_r := end_addr_r(DCCM_BITS-1,0)
|
||||
// dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||
// dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any
|
||||
// dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||
// dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any
|
||||
// dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m
|
||||
// dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m
|
||||
// dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m
|
||||
// dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m
|
||||
// dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||
// dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r
|
||||
// dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r
|
||||
// dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r
|
||||
// dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r
|
||||
// dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff
|
||||
// dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff
|
||||
// dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff
|
||||
// dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff
|
||||
// dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||
// dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m
|
||||
// dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m
|
||||
// dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||
// dccm_ctl.io.dma_dccm_wen := dma_dccm_wen
|
||||
// dccm_ctl.io.dma_pic_wen := dma_pic_wen
|
||||
// dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m
|
||||
// dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||
// dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||
// dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi
|
||||
// dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo
|
||||
// dccm_ctl.io.scan_mode := io.scan_mode
|
||||
// //Outputs
|
||||
// io.lsu_dma.dma_dccm_ctl <> dccm_ctl.io.dma_dccm_ctl
|
||||
// io.dccm <> dccm_ctl.io.dccm
|
||||
// io.lsu_pic <> dccm_ctl.io.lsu_pic
|
||||
// //Store Buffer
|
||||
// //Inputs
|
||||
// stbuf.io.ldst_dual_d := ldst_dual_d
|
||||
// stbuf.io.ldst_dual_m := ldst_dual_m
|
||||
// stbuf.io.ldst_dual_r := ldst_dual_r
|
||||
// stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||
// stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
// stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
// stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||
// stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
// stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
// stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r
|
||||
// stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r
|
||||
// stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
|
||||
// stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
|
||||
// stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
|
||||
// stbuf.io.lsu_addr_d := lsu_addr_d
|
||||
// stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
// stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||
// stbuf.io.end_addr_d := end_addr_d
|
||||
// stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||
// stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||
// stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
// stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
// stbuf.io.lsu_cmpen_m := lsu_cmpen_m
|
||||
// stbuf.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// // ECC
|
||||
// //Inputs
|
||||
// ecc.io.clk_override := io.clk_override
|
||||
// ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
// ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
// ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||
// ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
|
||||
// ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
|
||||
// ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
// ecc.io.lsu_addr_r := lsu_addr_r
|
||||
// ecc.io.end_addr_r := end_addr_r
|
||||
// ecc.io.lsu_addr_m := lsu_addr_m
|
||||
// ecc.io.end_addr_m := end_addr_m
|
||||
// ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r
|
||||
// ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r
|
||||
// ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m
|
||||
// ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m
|
||||
// ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r
|
||||
// ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r
|
||||
// ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m
|
||||
// ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m
|
||||
// ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r
|
||||
// ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||
// ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m
|
||||
// ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
// ecc.io.dma_dccm_wen := dma_dccm_wen
|
||||
// ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||
// ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||
// ecc.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// //Trigger
|
||||
// //Inputs
|
||||
// trigger.io.trigger_pkt_any <> io.trigger_pkt_any
|
||||
// trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
// trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||
// //Outputs
|
||||
// io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m
|
||||
//
|
||||
// //Clock Domain
|
||||
// //Inputs
|
||||
// clkdomain.io.active_clk := io.active_clk
|
||||
// clkdomain.io.clk_override := io.clk_override
|
||||
// clkdomain.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
// clkdomain.io.dma_dccm_req := io.lsu_dma.dma_lsc_ctl.dma_dccm_req
|
||||
// clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
|
||||
// clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||
// clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any
|
||||
// clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
// clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any
|
||||
// clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any
|
||||
// clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any
|
||||
// clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
// clkdomain.io.lsu_p := io.lsu_p
|
||||
// clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
// clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
// clkdomain.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// //Bus Interface
|
||||
// //Inputs
|
||||
// bus_intf.io.scan_mode := io.scan_mode
|
||||
// io.lsu_dec.tlu_busbuff <> bus_intf.io.tlu_busbuff
|
||||
// bus_intf.io.clk_override := io.clk_override
|
||||
// bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
// bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
// bus_intf.io.lsu_busm_clken := lsu_busm_clken
|
||||
// bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken
|
||||
// bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
|
||||
// bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
|
||||
// bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk
|
||||
// bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
// bus_intf.io.active_clk := io.active_clk
|
||||
// bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
|
||||
// bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
// bus_intf.io.lsu_busreq_m := lsu_busreq_m
|
||||
// bus_intf.io.ldst_dual_d := ldst_dual_d
|
||||
// bus_intf.io.ldst_dual_m := ldst_dual_m
|
||||
// bus_intf.io.ldst_dual_r := ldst_dual_r
|
||||
// bus_intf.io.lsu_addr_m := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
// bus_intf.io.lsu_addr_r := lsu_addr_r & Fill(32,lsu_busreq_r)
|
||||
// bus_intf.io.end_addr_m := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
|
||||
// bus_intf.io.end_addr_r := end_addr_r & Fill(32,lsu_busreq_r)
|
||||
// bus_intf.io.store_data_r := dccm_ctl.io.store_data_r & Fill(32,lsu_busreq_r)
|
||||
// bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
// bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
// bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
// bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
// bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m
|
||||
// bus_intf.io.flush_m_up := flush_m_up
|
||||
// bus_intf.io.flush_r := flush_r
|
||||
// //Outputs
|
||||
// io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
|
||||
// lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||
// io.axi <> bus_intf.io.axi
|
||||
// bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
//
|
||||
// withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}
|
||||
// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
|
||||
// withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
|
||||
//
|
||||
//}
|
||||
//object lsu_main extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
|
||||
//}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,205 +1,205 @@
|
|||
package lsu
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
|
||||
class lsu_bus_intf extends Module with RequireAsyncReset with lib {
|
||||
val io = IO (new Bundle {
|
||||
val scan_mode = Input(Bool())
|
||||
val clk_override = Input(Bool())
|
||||
val tlu_busbuff = new tlu_busbuff()
|
||||
val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable
|
||||
val lsu_busm_clken = Input(Bool())
|
||||
val lsu_c1_r_clk = Input(Clock())
|
||||
val lsu_c2_r_clk = Input(Clock())
|
||||
val lsu_bus_ibuf_c1_clk = Input(Clock())
|
||||
val lsu_bus_obuf_c1_clk = Input(Clock())
|
||||
val lsu_bus_buf_c1_clk = Input(Clock())
|
||||
val lsu_free_c2_clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val lsu_busm_clk = Input(Clock())
|
||||
val axi = new axi_channels(LSU_BUS_TAG)
|
||||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
val lsu_busreq_m = Input(Bool())
|
||||
|
||||
val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t()))
|
||||
val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t()))
|
||||
|
||||
val lsu_addr_m = Input(UInt(32.W))
|
||||
val lsu_addr_r = Input(UInt(32.W))
|
||||
|
||||
val end_addr_m = Input(UInt(32.W))
|
||||
val end_addr_r = Input(UInt(32.W))
|
||||
val ldst_dual_d = Input(Bool())
|
||||
val ldst_dual_m = Input(Bool())
|
||||
val ldst_dual_r = Input(Bool())
|
||||
|
||||
val store_data_r = Input(UInt(32.W))
|
||||
val dec_tlu_force_halt = Input(Bool())
|
||||
|
||||
val lsu_commit_r = Input(Bool())
|
||||
val is_sideeffects_m = Input(Bool())
|
||||
val flush_m_up = Input(Bool())
|
||||
val flush_r = Input(Bool())
|
||||
|
||||
val lsu_busreq_r = Output(Bool())
|
||||
val lsu_bus_buffer_pend_any = Output(Bool())
|
||||
val lsu_bus_buffer_full_any = Output(Bool())
|
||||
val lsu_bus_buffer_empty_any = Output(Bool())
|
||||
//val lsu_bus_idle_any = Output(Bool())
|
||||
val bus_read_data_m = Output(UInt(32.W))
|
||||
|
||||
val dctl_busbuff = new dctl_busbuff()
|
||||
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
})
|
||||
|
||||
val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B)
|
||||
val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U)
|
||||
val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U)
|
||||
val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
|
||||
val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U)
|
||||
val is_sideeffects_r = WireInit(Bool(), init = false.B)
|
||||
val store_data_ext_r = WireInit(UInt(64.W), init = 0.U)
|
||||
val store_data_hi_r = WireInit(UInt(32.W), init = 0.U)
|
||||
val store_data_lo_r = WireInit(UInt(32.W), init = 0.U)
|
||||
val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B)
|
||||
val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B)
|
||||
val no_word_merge_r = WireInit(Bool(), init = false.B)
|
||||
val no_dword_merge_r = WireInit(Bool(), init = false.B)
|
||||
val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B)
|
||||
val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B)
|
||||
val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B)
|
||||
val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B)
|
||||
val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U)
|
||||
val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U)
|
||||
val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U)
|
||||
val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U)
|
||||
val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U)
|
||||
val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U)
|
||||
val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U)
|
||||
val ld_full_hit_hi_m = WireInit(Bool(), init = true.B)
|
||||
val ld_full_hit_lo_m = WireInit(Bool(), init = true.B)
|
||||
val ld_full_hit_m = WireInit(Bool(), init = false.B)
|
||||
|
||||
val bus_buffer = Module(new lsu_bus_buffer)
|
||||
|
||||
bus_buffer.io.scan_mode := io.scan_mode
|
||||
io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
|
||||
bus_buffer.io.clk_override := io.clk_override
|
||||
bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken
|
||||
bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken
|
||||
bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
|
||||
bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
|
||||
bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk
|
||||
bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk
|
||||
bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk
|
||||
bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
|
||||
bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
|
||||
//package lsu
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import lib._
|
||||
//import include._
|
||||
//
|
||||
bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m
|
||||
bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
|
||||
//class lsu_bus_intf extends Module with RequireAsyncReset with lib {
|
||||
// val io = IO (new Bundle {
|
||||
// val scan_mode = Input(Bool())
|
||||
// val clk_override = Input(Bool())
|
||||
// val tlu_busbuff = new tlu_busbuff()
|
||||
// val lsu_bus_obuf_c1_clken = Input(Bool())// obuf clock enable
|
||||
// val lsu_busm_clken = Input(Bool())
|
||||
// val lsu_c1_r_clk = Input(Clock())
|
||||
// val lsu_c2_r_clk = Input(Clock())
|
||||
// val lsu_bus_ibuf_c1_clk = Input(Clock())
|
||||
// val lsu_bus_obuf_c1_clk = Input(Clock())
|
||||
// val lsu_bus_buf_c1_clk = Input(Clock())
|
||||
// val lsu_free_c2_clk = Input(Clock())
|
||||
// val active_clk = Input(Clock())
|
||||
// val lsu_busm_clk = Input(Clock())
|
||||
// val axi = new axi_channels(LSU_BUS_TAG)
|
||||
// val dec_lsu_valid_raw_d = Input(Bool())
|
||||
// val lsu_busreq_m = Input(Bool())
|
||||
//
|
||||
|
||||
bus_buffer.io.lsu_addr_m := io.lsu_addr_m
|
||||
bus_buffer.io.end_addr_m := io.end_addr_m
|
||||
bus_buffer.io.lsu_addr_r := io.lsu_addr_r
|
||||
bus_buffer.io.end_addr_r := io.end_addr_r
|
||||
bus_buffer.io.store_data_r := io.store_data_r
|
||||
|
||||
bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
|
||||
bus_buffer.io.flush_m_up := io.flush_m_up
|
||||
bus_buffer.io.flush_r := io.flush_r
|
||||
bus_buffer.io.lsu_commit_r := io.lsu_commit_r
|
||||
bus_buffer.io.lsu_axi <> io.axi
|
||||
bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
|
||||
io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
|
||||
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
|
||||
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
|
||||
io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
|
||||
//io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
|
||||
ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
|
||||
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
|
||||
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
|
||||
ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
|
||||
io.dctl_busbuff <> bus_buffer.io.dctl_busbuff
|
||||
bus_buffer.io.no_word_merge_r := no_word_merge_r
|
||||
bus_buffer.io.no_dword_merge_r := no_dword_merge_r
|
||||
bus_buffer.io.is_sideeffects_r := is_sideeffects_r
|
||||
bus_buffer.io.ldst_dual_d := io.ldst_dual_d
|
||||
bus_buffer.io.ldst_dual_m := io.ldst_dual_m
|
||||
bus_buffer.io.ldst_dual_r := io.ldst_dual_r
|
||||
bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
|
||||
bus_buffer.io.ld_full_hit_m := ld_full_hit_m
|
||||
bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
|
||||
|
||||
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
|
||||
addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
|
||||
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||
no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
|
||||
no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
|
||||
|
||||
ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
|
||||
ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
|
||||
store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
|
||||
ldst_byteen_hi_m := ldst_byteen_ext_m(7,4)
|
||||
ldst_byteen_lo_m := ldst_byteen_ext_m(3,0)
|
||||
ldst_byteen_hi_r := ldst_byteen_ext_r(7,4)
|
||||
ldst_byteen_lo_r := ldst_byteen_ext_r(3,0)
|
||||
|
||||
store_data_hi_r := store_data_ext_r(63,32)
|
||||
store_data_lo_r := store_data_ext_r(31,0)
|
||||
ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
|
||||
ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m
|
||||
ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
|
||||
io.bus_read_data_m := ld_fwddata_m(31,0)
|
||||
|
||||
withClock(io.active_clk) {
|
||||
lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||
}
|
||||
|
||||
withClock(io.lsu_c1_r_clk) {
|
||||
is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U)
|
||||
ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
|
||||
}
|
||||
}
|
||||
object bus_intf extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
|
||||
}
|
||||
// val lsu_pkt_m = Flipped(Valid(new lsu_pkt_t()))
|
||||
// val lsu_pkt_r = Flipped(Valid(new lsu_pkt_t()))
|
||||
//
|
||||
// val lsu_addr_m = Input(UInt(32.W))
|
||||
// val lsu_addr_r = Input(UInt(32.W))
|
||||
//
|
||||
// val end_addr_m = Input(UInt(32.W))
|
||||
// val end_addr_r = Input(UInt(32.W))
|
||||
// val ldst_dual_d = Input(Bool())
|
||||
// val ldst_dual_m = Input(Bool())
|
||||
// val ldst_dual_r = Input(Bool())
|
||||
//
|
||||
// val store_data_r = Input(UInt(32.W))
|
||||
// val dec_tlu_force_halt = Input(Bool())
|
||||
//
|
||||
// val lsu_commit_r = Input(Bool())
|
||||
// val is_sideeffects_m = Input(Bool())
|
||||
// val flush_m_up = Input(Bool())
|
||||
// val flush_r = Input(Bool())
|
||||
//
|
||||
// val lsu_busreq_r = Output(Bool())
|
||||
// val lsu_bus_buffer_pend_any = Output(Bool())
|
||||
// val lsu_bus_buffer_full_any = Output(Bool())
|
||||
// val lsu_bus_buffer_empty_any = Output(Bool())
|
||||
// //val lsu_bus_idle_any = Output(Bool())
|
||||
// val bus_read_data_m = Output(UInt(32.W))
|
||||
//
|
||||
// val dctl_busbuff = new dctl_busbuff()
|
||||
//
|
||||
// val lsu_bus_clk_en = Input(Bool())
|
||||
// })
|
||||
//
|
||||
// val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B)
|
||||
// val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U)
|
||||
// val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U)
|
||||
// val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U)
|
||||
// val is_sideeffects_r = WireInit(Bool(), init = false.B)
|
||||
// val store_data_ext_r = WireInit(UInt(64.W), init = 0.U)
|
||||
// val store_data_hi_r = WireInit(UInt(32.W), init = 0.U)
|
||||
// val store_data_lo_r = WireInit(UInt(32.W), init = 0.U)
|
||||
// val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B)
|
||||
// val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B)
|
||||
// val no_word_merge_r = WireInit(Bool(), init = false.B)
|
||||
// val no_dword_merge_r = WireInit(Bool(), init = false.B)
|
||||
// val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B)
|
||||
// val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B)
|
||||
// val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B)
|
||||
// val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B)
|
||||
// val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U)
|
||||
// val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U)
|
||||
// val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U)
|
||||
// val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U)
|
||||
// val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U)
|
||||
// val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U)
|
||||
// val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U)
|
||||
// val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U)
|
||||
// val ld_full_hit_hi_m = WireInit(Bool(), init = true.B)
|
||||
// val ld_full_hit_lo_m = WireInit(Bool(), init = true.B)
|
||||
// val ld_full_hit_m = WireInit(Bool(), init = false.B)
|
||||
//
|
||||
// val bus_buffer = Module(new lsu_bus_buffer)
|
||||
//
|
||||
// bus_buffer.io.scan_mode := io.scan_mode
|
||||
// io.tlu_busbuff <> bus_buffer.io.tlu_busbuff
|
||||
// bus_buffer.io.clk_override := io.clk_override
|
||||
// bus_buffer.io.lsu_bus_obuf_c1_clken := io.lsu_bus_obuf_c1_clken
|
||||
// bus_buffer.io.lsu_busm_clken := io.lsu_busm_clken
|
||||
// bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||
// bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
|
||||
// bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
|
||||
// bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk
|
||||
// bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk
|
||||
// bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk
|
||||
// bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
|
||||
// bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
//
|
||||
// //
|
||||
// bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m
|
||||
// bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
|
||||
// //
|
||||
//
|
||||
// bus_buffer.io.lsu_addr_m := io.lsu_addr_m
|
||||
// bus_buffer.io.end_addr_m := io.end_addr_m
|
||||
// bus_buffer.io.lsu_addr_r := io.lsu_addr_r
|
||||
// bus_buffer.io.end_addr_r := io.end_addr_r
|
||||
// bus_buffer.io.store_data_r := io.store_data_r
|
||||
//
|
||||
// bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
|
||||
// bus_buffer.io.flush_m_up := io.flush_m_up
|
||||
// bus_buffer.io.flush_r := io.flush_r
|
||||
// bus_buffer.io.lsu_commit_r := io.lsu_commit_r
|
||||
// bus_buffer.io.lsu_axi <> io.axi
|
||||
// bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
//
|
||||
// io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
|
||||
// io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
|
||||
// io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
|
||||
// io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
|
||||
// //io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
|
||||
// ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
|
||||
// ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
|
||||
// ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
|
||||
// ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
|
||||
// io.dctl_busbuff <> bus_buffer.io.dctl_busbuff
|
||||
// bus_buffer.io.no_word_merge_r := no_word_merge_r
|
||||
// bus_buffer.io.no_dword_merge_r := no_dword_merge_r
|
||||
// bus_buffer.io.is_sideeffects_r := is_sideeffects_r
|
||||
// bus_buffer.io.ldst_dual_d := io.ldst_dual_d
|
||||
// bus_buffer.io.ldst_dual_m := io.ldst_dual_m
|
||||
// bus_buffer.io.ldst_dual_r := io.ldst_dual_r
|
||||
// bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
|
||||
// bus_buffer.io.ld_full_hit_m := ld_full_hit_m
|
||||
// bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
|
||||
//
|
||||
// ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
|
||||
// addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
|
||||
// addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||
// no_word_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
|
||||
// no_dword_merge_r := io.lsu_busreq_r & !io.ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
|
||||
//
|
||||
// ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
|
||||
// ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
|
||||
// store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
|
||||
// ldst_byteen_hi_m := ldst_byteen_ext_m(7,4)
|
||||
// ldst_byteen_lo_m := ldst_byteen_ext_m(3,0)
|
||||
// ldst_byteen_hi_r := ldst_byteen_ext_r(7,4)
|
||||
// ldst_byteen_lo_r := ldst_byteen_ext_r(3,0)
|
||||
//
|
||||
// store_data_hi_r := store_data_ext_r(63,32)
|
||||
// store_data_lo_r := store_data_ext_r(31,0)
|
||||
// ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
// ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
// ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
// ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
//
|
||||
// ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||
// ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||
// ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m
|
||||
// ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
|
||||
// io.bus_read_data_m := ld_fwddata_m(31,0)
|
||||
//
|
||||
// withClock(io.active_clk) {
|
||||
// lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||
// }
|
||||
//
|
||||
// withClock(io.lsu_c1_r_clk) {
|
||||
// is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U)
|
||||
// ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W))
|
||||
// }
|
||||
//}
|
||||
//object bus_intf extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
|
||||
//}
|
||||
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