snapshot removed
This commit is contained in:
waleed-lm
parent
73aab54974
commit
f59510b304
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@ -1 +1,3 @@
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/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
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/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
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/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
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/home/waleedbinehsan/Desktop/Quasar/mem.sv
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1106
quasar_wrapper.fir
1106
quasar_wrapper.fir
File diff suppressed because it is too large
Load Diff
708
quasar_wrapper.v
708
quasar_wrapper.v
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@ -67840,33 +67840,33 @@ module lsu_clkdomain(
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wire rvclkhdr_11_io_clk; // @[lib.scala 327:22]
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wire rvclkhdr_11_io_en; // @[lib.scala 327:22]
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wire rvclkhdr_11_io_scan_mode; // @[lib.scala 327:22]
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wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 63:51]
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reg lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 82:67]
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wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 64:51]
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wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[lsu_clkdomain.scala 64:70]
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reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 83:67]
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wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 65:51]
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wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[lsu_clkdomain.scala 65:70]
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wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 67:47]
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reg lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 84:67]
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wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 68:47]
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wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[lsu_clkdomain.scala 70:49]
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wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[lsu_clkdomain.scala 71:49]
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wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[lsu_clkdomain.scala 72:55]
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wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[lsu_clkdomain.scala 72:77]
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wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:61]
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wire _T_10 = _T_9 | io_clk_override; // @[lsu_clkdomain.scala 74:79]
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wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 75:32]
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wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 75:61]
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wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[lsu_clkdomain.scala 77:48]
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wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[lsu_clkdomain.scala 77:69]
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wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[lsu_clkdomain.scala 77:90]
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wire _T_17 = _T_15 | _T_11; // @[lsu_clkdomain.scala 77:112]
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wire _T_18 = ~io_lsu_stbuf_empty_any; // @[lsu_clkdomain.scala 77:145]
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wire _T_19 = _T_17 | _T_18; // @[lsu_clkdomain.scala 77:143]
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wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[lsu_clkdomain.scala 77:169]
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reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 81:60]
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wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
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wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 62:51]
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reg lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 81:67]
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wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 63:51]
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wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[lsu_clkdomain.scala 63:70]
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reg lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 82:67]
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wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 64:51]
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wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[lsu_clkdomain.scala 64:70]
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wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 66:47]
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reg lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 83:67]
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wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[lsu_clkdomain.scala 67:47]
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wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_bits_store; // @[lsu_clkdomain.scala 69:49]
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wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_bits_store; // @[lsu_clkdomain.scala 70:49]
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wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[lsu_clkdomain.scala 71:55]
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wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[lsu_clkdomain.scala 71:77]
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wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[lsu_clkdomain.scala 73:61]
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wire _T_10 = _T_9 | io_clk_override; // @[lsu_clkdomain.scala 73:79]
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wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[lsu_clkdomain.scala 74:32]
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wire _T_12 = _T_11 | io_lsu_busreq_r; // @[lsu_clkdomain.scala 74:61]
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wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[lsu_clkdomain.scala 76:48]
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wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[lsu_clkdomain.scala 76:69]
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wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[lsu_clkdomain.scala 76:90]
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wire _T_17 = _T_15 | _T_11; // @[lsu_clkdomain.scala 76:112]
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wire _T_18 = ~io_lsu_stbuf_empty_any; // @[lsu_clkdomain.scala 76:145]
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wire _T_19 = _T_17 | _T_18; // @[lsu_clkdomain.scala 76:143]
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wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[lsu_clkdomain.scala 76:169]
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reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 80:60]
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wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 77:50]
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rvclkhdr rvclkhdr ( // @[lib.scala 327:22]
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.io_l1clk(rvclkhdr_io_l1clk),
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.io_clk(rvclkhdr_io_clk),
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@ -67939,18 +67939,18 @@ module lsu_clkdomain(
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.io_en(rvclkhdr_11_io_en),
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.io_scan_mode(rvclkhdr_11_io_scan_mode)
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);
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assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[lsu_clkdomain.scala 86:26]
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assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[lsu_clkdomain.scala 87:26]
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assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[lsu_clkdomain.scala 88:26]
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assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[lsu_clkdomain.scala 89:26]
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assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 90:26]
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assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 91:26]
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assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 92:26]
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assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 94:26]
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assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 93:26]
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assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 95:26]
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assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 96:26]
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assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 97:26]
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assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[lsu_clkdomain.scala 85:26]
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assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[lsu_clkdomain.scala 86:26]
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assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[lsu_clkdomain.scala 87:26]
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assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[lsu_clkdomain.scala 88:26]
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assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 89:26]
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assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 90:26]
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assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 91:26]
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assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 93:26]
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assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 92:26]
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assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 94:26]
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assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 95:26]
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assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 96:26]
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assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
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assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[lib.scala 329:16]
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assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
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@ -72739,202 +72739,202 @@ module lsu_bus_intf(
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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`endif // RANDOMIZE_REG_INIT
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wire bus_buffer_clock; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_reset; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 102:39]
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wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 102:39]
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wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 102:39]
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wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 102:39]
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wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 102:39]
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wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 102:39]
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wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 102:39]
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wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 102:39]
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wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 102:39]
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wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 102:39]
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wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 102:39]
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wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 102:39]
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wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 102:39]
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wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 102:39]
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wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 102:39]
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wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 102:39]
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wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 102:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 102:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 102:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 102:39]
|
||||
wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 102:39]
|
||||
wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 102:39]
|
||||
wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 102:39]
|
||||
wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 102:39]
|
||||
wire bus_buffer_clock; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_reset; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [1:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_lsu_addr_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_end_addr_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_lsu_addr_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_end_addr_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_store_data_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_no_word_merge_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_no_dword_merge_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_busreq_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_ld_full_hit_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_flush_m_up; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_flush_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_commit_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_is_sideeffects_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_ldst_dual_d; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_ldst_dual_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_ldst_dual_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [63:0] bus_buffer_io_lsu_axi_r_bits_data; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [1:0] bus_buffer_io_lsu_axi_r_bits_resp; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 101:39]
|
||||
wire [3:0] _T_3 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_4 = io_lsu_pkt_m_bits_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_5 = io_lsu_pkt_m_bits_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72]
|
||||
wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72]
|
||||
wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 156:51]
|
||||
wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 157:71]
|
||||
wire _T_18 = ~_T_17; // @[lsu_bus_intf.scala 157:53]
|
||||
wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[lsu_bus_intf.scala 157:51]
|
||||
reg ldst_dual_r; // @[lsu_bus_intf.scala 202:33]
|
||||
wire _T_20 = ~ldst_dual_r; // @[lsu_bus_intf.scala 158:48]
|
||||
wire _T_21 = io_lsu_busreq_r & _T_20; // @[lsu_bus_intf.scala 158:46]
|
||||
wire _T_22 = _T_21 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 158:61]
|
||||
wire _T_23 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 158:107]
|
||||
wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[lsu_bus_intf.scala 158:105]
|
||||
wire _T_29 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 159:107]
|
||||
wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[lsu_bus_intf.scala 159:105]
|
||||
wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 161:49]
|
||||
wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 161:49]
|
||||
reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 204:33]
|
||||
wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 162:49]
|
||||
wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 162:49]
|
||||
wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[lsu_bus_intf.scala 155:51]
|
||||
wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[lsu_bus_intf.scala 156:71]
|
||||
wire _T_18 = ~_T_17; // @[lsu_bus_intf.scala 156:53]
|
||||
wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[lsu_bus_intf.scala 156:51]
|
||||
reg ldst_dual_r; // @[lsu_bus_intf.scala 201:33]
|
||||
wire _T_20 = ~ldst_dual_r; // @[lsu_bus_intf.scala 157:48]
|
||||
wire _T_21 = io_lsu_busreq_r & _T_20; // @[lsu_bus_intf.scala 157:46]
|
||||
wire _T_22 = _T_21 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 157:61]
|
||||
wire _T_23 = ~addr_match_word_lo_r_m; // @[lsu_bus_intf.scala 157:107]
|
||||
wire _T_24 = io_lsu_pkt_m_bits_load | _T_23; // @[lsu_bus_intf.scala 157:105]
|
||||
wire _T_29 = ~addr_match_dw_lo_r_m; // @[lsu_bus_intf.scala 158:107]
|
||||
wire _T_30 = io_lsu_pkt_m_bits_load | _T_29; // @[lsu_bus_intf.scala 158:105]
|
||||
wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[lsu_bus_intf.scala 160:49]
|
||||
wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[lsu_bus_intf.scala 160:49]
|
||||
reg [3:0] ldst_byteen_r; // @[lsu_bus_intf.scala 203:33]
|
||||
wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[lsu_bus_intf.scala 161:49]
|
||||
wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[lsu_bus_intf.scala 161:49]
|
||||
wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 163:52]
|
||||
wire [62:0] _T_41 = _GEN_2 << _T_40; // @[lsu_bus_intf.scala 163:52]
|
||||
wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 161:27]
|
||||
wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 164:47]
|
||||
wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 165:47]
|
||||
wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[lsu_bus_intf.scala 162:27]
|
||||
wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 166:47]
|
||||
wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 167:47]
|
||||
wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[lsu_bus_intf.scala 163:27]
|
||||
wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 169:46]
|
||||
wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 170:46]
|
||||
wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51]
|
||||
wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76]
|
||||
wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97]
|
||||
wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123]
|
||||
wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51]
|
||||
wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76]
|
||||
wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97]
|
||||
wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123]
|
||||
wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51]
|
||||
wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76]
|
||||
wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97]
|
||||
wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123]
|
||||
wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 174:51]
|
||||
wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 174:76]
|
||||
wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 174:97]
|
||||
wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 174:123]
|
||||
wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[lsu_bus_intf.scala 162:52]
|
||||
wire [62:0] _T_41 = _GEN_2 << _T_40; // @[lsu_bus_intf.scala 162:52]
|
||||
wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 160:27]
|
||||
wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[lsu_bus_intf.scala 163:47]
|
||||
wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[lsu_bus_intf.scala 164:47]
|
||||
wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[lsu_bus_intf.scala 161:27]
|
||||
wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[lsu_bus_intf.scala 165:47]
|
||||
wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[lsu_bus_intf.scala 166:47]
|
||||
wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[lsu_bus_intf.scala 162:27]
|
||||
wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[lsu_bus_intf.scala 168:46]
|
||||
wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[lsu_bus_intf.scala 169:46]
|
||||
wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 170:51]
|
||||
wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 170:76]
|
||||
wire _T_52 = _T_51 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 170:97]
|
||||
wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 170:123]
|
||||
wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[lsu_bus_intf.scala 171:51]
|
||||
wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 171:76]
|
||||
wire _T_58 = _T_57 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 171:97]
|
||||
wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 171:123]
|
||||
wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 172:51]
|
||||
wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 172:76]
|
||||
wire _T_64 = _T_63 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 172:97]
|
||||
wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 172:123]
|
||||
wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[lsu_bus_intf.scala 173:51]
|
||||
wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[lsu_bus_intf.scala 173:76]
|
||||
wire _T_70 = _T_69 & io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 173:97]
|
||||
wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 173:123]
|
||||
wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 175:70]
|
||||
wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 175:92]
|
||||
wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 175:70]
|
||||
wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 175:92]
|
||||
wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 175:70]
|
||||
wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 175:92]
|
||||
wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 175:70]
|
||||
wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 175:92]
|
||||
wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58]
|
||||
wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[lsu_bus_intf.scala 176:70]
|
||||
wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 176:92]
|
||||
wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58]
|
||||
wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 177:70]
|
||||
wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 177:92]
|
||||
wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58]
|
||||
wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 179:70]
|
||||
wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 179:92]
|
||||
wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 179:70]
|
||||
wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 179:92]
|
||||
wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 179:70]
|
||||
wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 179:92]
|
||||
wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 179:70]
|
||||
wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 179:92]
|
||||
wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[lsu_bus_intf.scala 178:70]
|
||||
wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 178:92]
|
||||
wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58]
|
||||
wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 139:38]
|
||||
wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[lsu_bus_intf.scala 180:73]
|
||||
wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[lsu_bus_intf.scala 138:38]
|
||||
wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[lsu_bus_intf.scala 180:97]
|
||||
wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[lsu_bus_intf.scala 180:73]
|
||||
wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[lsu_bus_intf.scala 180:97]
|
||||
wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[lsu_bus_intf.scala 180:73]
|
||||
wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[lsu_bus_intf.scala 180:97]
|
||||
wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[lsu_bus_intf.scala 180:73]
|
||||
wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[lsu_bus_intf.scala 180:97]
|
||||
wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58]
|
||||
wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 182:73]
|
||||
wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 140:38]
|
||||
wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 182:97]
|
||||
wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 182:73]
|
||||
wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 182:97]
|
||||
wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 182:73]
|
||||
wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 182:97]
|
||||
wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 182:73]
|
||||
wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 182:97]
|
||||
wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[lsu_bus_intf.scala 139:38]
|
||||
wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[lsu_bus_intf.scala 181:73]
|
||||
wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[lsu_bus_intf.scala 181:97]
|
||||
wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58]
|
||||
wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58]
|
||||
wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58]
|
||||
|
|
@ -72964,54 +72964,54 @@ module lsu_bus_intf(
|
|||
wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72]
|
||||
wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58]
|
||||
wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 141:38]
|
||||
wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[lsu_bus_intf.scala 140:38]
|
||||
wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[lsu_bus_intf.scala 186:54]
|
||||
wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[lsu_bus_intf.scala 186:54]
|
||||
wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[lsu_bus_intf.scala 186:54]
|
||||
wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[lsu_bus_intf.scala 186:54]
|
||||
wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58]
|
||||
wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 142:38]
|
||||
wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 188:54]
|
||||
wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 188:54]
|
||||
wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 188:54]
|
||||
wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 188:54]
|
||||
wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[lsu_bus_intf.scala 141:38]
|
||||
wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[lsu_bus_intf.scala 187:54]
|
||||
wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58]
|
||||
wire _T_334 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_338 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_342 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_346 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_348 = _T_335 & _T_339; // @[lsu_bus_intf.scala 189:111]
|
||||
wire _T_349 = _T_348 & _T_343; // @[lsu_bus_intf.scala 189:111]
|
||||
wire ld_full_hit_lo_m = _T_349 & _T_347; // @[lsu_bus_intf.scala 189:111]
|
||||
wire _T_353 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 190:72]
|
||||
wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[lsu_bus_intf.scala 190:70]
|
||||
wire _T_357 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 190:72]
|
||||
wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[lsu_bus_intf.scala 190:70]
|
||||
wire _T_361 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 190:72]
|
||||
wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[lsu_bus_intf.scala 190:70]
|
||||
wire _T_365 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 190:72]
|
||||
wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[lsu_bus_intf.scala 190:70]
|
||||
wire _T_367 = _T_354 & _T_358; // @[lsu_bus_intf.scala 190:111]
|
||||
wire _T_368 = _T_367 & _T_362; // @[lsu_bus_intf.scala 190:111]
|
||||
wire ld_full_hit_hi_m = _T_368 & _T_366; // @[lsu_bus_intf.scala 190:111]
|
||||
wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 191:47]
|
||||
wire _T_371 = _T_370 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 191:66]
|
||||
wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 191:84]
|
||||
wire _T_373 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 191:111]
|
||||
wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[lsu_bus_intf.scala 188:27]
|
||||
wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[lsu_bus_intf.scala 187:27]
|
||||
wire _T_334 = ~ldst_byteen_lo_m[0]; // @[lsu_bus_intf.scala 188:72]
|
||||
wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[lsu_bus_intf.scala 188:70]
|
||||
wire _T_338 = ~ldst_byteen_lo_m[1]; // @[lsu_bus_intf.scala 188:72]
|
||||
wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[lsu_bus_intf.scala 188:70]
|
||||
wire _T_342 = ~ldst_byteen_lo_m[2]; // @[lsu_bus_intf.scala 188:72]
|
||||
wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[lsu_bus_intf.scala 188:70]
|
||||
wire _T_346 = ~ldst_byteen_lo_m[3]; // @[lsu_bus_intf.scala 188:72]
|
||||
wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[lsu_bus_intf.scala 188:70]
|
||||
wire _T_348 = _T_335 & _T_339; // @[lsu_bus_intf.scala 188:111]
|
||||
wire _T_349 = _T_348 & _T_343; // @[lsu_bus_intf.scala 188:111]
|
||||
wire ld_full_hit_lo_m = _T_349 & _T_347; // @[lsu_bus_intf.scala 188:111]
|
||||
wire _T_353 = ~ldst_byteen_hi_m[0]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_357 = ~ldst_byteen_hi_m[1]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_361 = ~ldst_byteen_hi_m[2]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_365 = ~ldst_byteen_hi_m[3]; // @[lsu_bus_intf.scala 189:72]
|
||||
wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[lsu_bus_intf.scala 189:70]
|
||||
wire _T_367 = _T_354 & _T_358; // @[lsu_bus_intf.scala 189:111]
|
||||
wire _T_368 = _T_367 & _T_362; // @[lsu_bus_intf.scala 189:111]
|
||||
wire ld_full_hit_hi_m = _T_368 & _T_366; // @[lsu_bus_intf.scala 189:111]
|
||||
wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[lsu_bus_intf.scala 190:47]
|
||||
wire _T_371 = _T_370 & io_lsu_busreq_m; // @[lsu_bus_intf.scala 190:66]
|
||||
wire _T_372 = _T_371 & io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 190:84]
|
||||
wire _T_373 = ~io_is_sideeffects_m; // @[lsu_bus_intf.scala 190:111]
|
||||
wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[lsu_bus_intf.scala 187:27]
|
||||
wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[lsu_bus_intf.scala 186:27]
|
||||
wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 192:83]
|
||||
wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 192:83]
|
||||
wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[lsu_bus_intf.scala 192:76]
|
||||
reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 196:32]
|
||||
reg ldst_dual_m; // @[lsu_bus_intf.scala 199:27]
|
||||
reg is_sideeffects_r; // @[lsu_bus_intf.scala 203:33]
|
||||
lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 102:39]
|
||||
wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_bus_intf.scala 191:83]
|
||||
wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[lsu_bus_intf.scala 191:83]
|
||||
wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[lsu_bus_intf.scala 191:76]
|
||||
reg lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 195:32]
|
||||
reg ldst_dual_m; // @[lsu_bus_intf.scala 198:27]
|
||||
reg is_sideeffects_r; // @[lsu_bus_intf.scala 202:33]
|
||||
lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 101:39]
|
||||
.clock(bus_buffer_clock),
|
||||
.reset(bus_buffer_reset),
|
||||
.io_scan_mode(bus_buffer_io_scan_mode),
|
||||
|
|
@ -73104,92 +73104,92 @@ module lsu_bus_intf(
|
|||
.io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo),
|
||||
.io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi)
|
||||
);
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 105:18]
|
||||
assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 131:43]
|
||||
assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38]
|
||||
assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38]
|
||||
assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38]
|
||||
assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 137:38]
|
||||
assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 193:27]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 143:19]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_trxn = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_misaligned = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_error = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_pmu_bus_busy = bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 104:18]
|
||||
assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 130:43]
|
||||
assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 133:38]
|
||||
assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 134:38]
|
||||
assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 135:38]
|
||||
assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[lsu_bus_intf.scala 136:38]
|
||||
assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[lsu_bus_intf.scala 192:27]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_valid_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_tag_m = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_inv_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_valid = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_error = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data_tag = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu_bus_intf.scala 142:19]
|
||||
assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 142:19]
|
||||
assign bus_buffer_clock = clock;
|
||||
assign bus_buffer_reset = reset;
|
||||
assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 104:29]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 105:18]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 105:18]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 105:18]
|
||||
assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51]
|
||||
assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51]
|
||||
assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51]
|
||||
assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 110:51]
|
||||
assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51]
|
||||
assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51]
|
||||
assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 113:51]
|
||||
assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51]
|
||||
assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 118:27]
|
||||
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 121:51]
|
||||
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 122:51]
|
||||
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 123:51]
|
||||
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 124:51]
|
||||
assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 125:51]
|
||||
assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[lsu_bus_intf.scala 144:51]
|
||||
assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[lsu_bus_intf.scala 145:51]
|
||||
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 127:51]
|
||||
assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[lsu_bus_intf.scala 151:51]
|
||||
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 128:51]
|
||||
assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 129:51]
|
||||
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 130:51]
|
||||
assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 146:51]
|
||||
assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_bus_intf.scala 147:51]
|
||||
assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 148:51]
|
||||
assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 149:51]
|
||||
assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 150:51]
|
||||
assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 131:43]
|
||||
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 132:51]
|
||||
assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 152:51]
|
||||
assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 103:29]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 104:18]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 104:18]
|
||||
assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 104:18]
|
||||
assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 106:51]
|
||||
assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 107:51]
|
||||
assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 108:51]
|
||||
assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 109:51]
|
||||
assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 110:51]
|
||||
assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 111:51]
|
||||
assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 112:51]
|
||||
assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 113:51]
|
||||
assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 116:27]
|
||||
assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 116:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_by = io_lsu_pkt_r_bits_by; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_half = io_lsu_pkt_r_bits_half; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_word = io_lsu_pkt_r_bits_word; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_load = io_lsu_pkt_r_bits_load; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_store = io_lsu_pkt_r_bits_store; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_pkt_r_bits_unsign = io_lsu_pkt_r_bits_unsign; // @[lsu_bus_intf.scala 117:27]
|
||||
assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[lsu_bus_intf.scala 120:51]
|
||||
assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[lsu_bus_intf.scala 121:51]
|
||||
assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[lsu_bus_intf.scala 122:51]
|
||||
assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[lsu_bus_intf.scala 123:51]
|
||||
assign bus_buffer_io_store_data_r = io_store_data_r; // @[lsu_bus_intf.scala 124:51]
|
||||
assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[lsu_bus_intf.scala 143:51]
|
||||
assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[lsu_bus_intf.scala 144:51]
|
||||
assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[lsu_bus_intf.scala 126:51]
|
||||
assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[lsu_bus_intf.scala 150:51]
|
||||
assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[lsu_bus_intf.scala 127:51]
|
||||
assign bus_buffer_io_flush_r = io_flush_r; // @[lsu_bus_intf.scala 128:51]
|
||||
assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[lsu_bus_intf.scala 129:51]
|
||||
assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[lsu_bus_intf.scala 145:51]
|
||||
assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[lsu_bus_intf.scala 146:51]
|
||||
assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[lsu_bus_intf.scala 147:51]
|
||||
assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[lsu_bus_intf.scala 148:51]
|
||||
assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[lsu_bus_intf.scala 149:51]
|
||||
assign bus_buffer_io_lsu_axi_aw_ready = io_axi_aw_ready; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_w_ready = io_axi_w_ready; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_b_valid = io_axi_b_valid; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_b_bits_id = io_axi_b_bits_id; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_ar_ready = io_axi_ar_ready; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_r_valid = io_axi_r_valid; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_id = io_axi_r_bits_id; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_data = io_axi_r_bits_data; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu_bus_intf.scala 130:43]
|
||||
assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu_bus_intf.scala 131:51]
|
||||
assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[lsu_bus_intf.scala 151:51]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -74539,7 +74539,7 @@ module lsu(
|
|||
assign stbuf_clock = clock;
|
||||
assign stbuf_reset = reset;
|
||||
assign stbuf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 199:49]
|
||||
assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 200:48]
|
||||
assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 200:48]
|
||||
assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 201:54]
|
||||
assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 202:54]
|
||||
assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 203:48]
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@ import chisel3._
|
|||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
import snapshot._
|
||||
import ifu._
|
||||
|
||||
class lsu_bus_intf extends Module with RequireAsyncReset with lib {
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@ import chisel3.experimental.chiselName
|
|||
import chisel3.util._
|
||||
import lib._
|
||||
import include._
|
||||
import snapshot._
|
||||
|
||||
@chiselName
|
||||
class lsu_clkdomain extends Module with RequireAsyncReset with lib{
|
||||
|
|
|
|||
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Reference in New Issue