LSU clock domain skeleton

src/main/scala/lsu/el2_lsu_bus_intf.scala

@@ -1,7 +1,11 @@
+
+package lsu
 import chisel3._
 import chisel3.util._
-
+import lib._
-class  el2_lsu_bus_intf extends Module
+import include._
+import snapshot._
+class  el2_lsu_lsc_ctl extends Module
 {
    val io = IO (new Bundle {
    //val clk         = Input(Clock()) //implicit
@@ -108,10 +112,10 @@ class  el2_lsu_bus_intf extends Module
    val lsu_axi_rready      = Output(UInt(1.W))
    val lsu_axi_rid         = Input(UInt(pt1.LSU_BUS_TAG.W))
    val lsu_axi_rdata       = Input(UInt(64.W))
-   val lsu_axi_rresp       = Input(UInt(2.W))
+   val lsu_axi_rresp       = Intput(UInt(2.W))
-   val lsu_axi_rlast       = Input(UInt(1.W))
+   val lsu_axi_rlast       = Intput(UInt(1.W))
 
-   val lsu_bus_clk_en      = Input(UInt(1.W))
+   val lsu_bus_clk_en      = Intput(UInt(1.W))
    })
    
    val lsu_pkt_m = new el2_lsu_pkt_t()
@@ -178,6 +182,3 @@ class  el2_lsu_bus_intf extends Module
    
     
 }
-object busIntfMain extends App {
-   println(chisel3.Driver.emitVerilog(new el2_lsu_bus_intf))
-}

src/main/scala/lsu/el2_lsu_clkdomain.scala

@@ -1,3 +1,5 @@
+
+package lsu
 import chisel3._
 import chisel3.util._
 import lib._
@@ -86,16 +88,32 @@ class el2_lsu_clkdomain extends Module {
 
    lsu_store_c1_m_clken    := ((lsu_c1_m_clken & lsu_pkt_d.store) | io.clk_override)  
    lsu_store_c1_r_clken    := ((lsu_c1_r_clken & lsu_pkt_m.store) | io.clk_override)  
-
+   lsu_stbuf_c1_clken      := st_stbu_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
-   lsu_stbuf_c1_clken      := io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override 
    lsu_bus_ibuf_c1_clken   := io.lsu_busreq_r  | io.clk_override
    lsu_bus_obuf_c1_clken   := (io.lsu_bus_buffer_pend_any  | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
    lsu_bus_buf_c1_clken    := ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override
 
    lsu_free_c1_clken := (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override 
    lsu_free_c2_clken := lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
-/*
+
-    // Flops
+   io.lsu_c1_m_clk              := 0.U          // m pipe single pulse clock
+   io.lsu_c1_r_clk              := 0.U          // r pipe single pulse clock
+
+   io.lsu_c2_m_clk              := 0.U          // m pipe double pulse clock
+   io.lsu_c2_r_clk              := 0.U          // r pipe double pulse clock
+
+   io.lsu_store_c1_m_clk        := 0.U          // store in m
+   io.lsu_store_c1_r_clk        := 0.U          // store in r
+
+   io.lsu_stbuf_c1_clk          := 0.U
+   io.lsu_bus_obuf_c1_clk       := 0.U          // ibuf clock
+   io.lsu_bus_ibuf_c1_clk       := 0.U          // ibuf clock
+   io.lsu_bus_buf_c1_clk        := 0.U          // ibuf clock
+   io.lsu_busm_clk              := 0.U          // bus clock
+
+   io.lsu_free_c2_clk           := 0.U
+
+   /*0.U      // Flops
       rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), dout(lsu_free_c1_clken_q), clk(free_clk), *)
 
       rvdff #(1) lsu_c1_d_clkenff (.din(lsu_c1_d_clken), dout(lsu_c1_d_clken_q), clk(lsu_free_c2_clk), *)
@@ -122,6 +140,6 @@ class el2_lsu_clkdomain extends Module {
 
       rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), l1clk(lsu_free_c2_clk), *)
 
-*/
+   */
 }