IMC clock gating

el2_ifu_ifc_ctl.anno.json

@@ -107,6 +107,11 @@
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"
   },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_ifu_ifc_ctl.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."

el2_ifu_ifc_ctl.fir

@@ -1,5 +1,29 @@
 ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
 circuit el2_ifu_ifc_ctl : 
+  extmodule TEC_RV_ICG : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG @[el2_lib.scala 452:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 454:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 455:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18]
+    
   module el2_ifu_ifc_ctl : 
     input clock : Clock
     input reset : AsyncReset
@@ -228,10 +252,10 @@ circuit el2_ifu_ifc_ctl :
     node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctl.scala 126:33]
     io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctl.scala 126:26]
     node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 216:25]
+    node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 219:25]
-    node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 216:47]
+    node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 219:47]
-    node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 219:14]
+    node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 222:14]
-    node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 219:29]
+    node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 222:29]
     io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 132:25]
     node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 133:30]
     node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 134:39]
@@ -258,10 +282,14 @@ circuit el2_ifu_ifc_ctl :
     reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 140:57]
     _T_164 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 140:57]
     io.ifc_fetch_req_f <= _T_164 @[el2_ifu_ifc_ctl.scala 140:22]
-    node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:88]
+    node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 142:73]
-    reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    inst rvclkhdr of rvclkhdr @[el2_lib.scala 472:23]
-    when _T_165 : @[Reg.scala 28:19]
+    rvclkhdr.clock <= clock
-      _T_166 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
+    rvclkhdr.reset <= reset
-      skip @[Reg.scala 28:19]
+    rvclkhdr.io.clk <= clock @[el2_lib.scala 474:18]
+    rvclkhdr.io.en <= _T_165 @[el2_lib.scala 475:17]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24]
+    reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16]
+    _T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 478:16]
     io.ifc_fetch_addr_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:23]
     

el2_ifu_ifc_ctl.v

@@ -1,3 +1,24 @@
+module rvclkhdr(
+  output  io_l1clk,
+  input   io_clk,
+  input   io_en,
+  input   io_scan_mode
+);
+  wire  clkhdr_Q; // @[el2_lib.scala 452:26]
+  wire  clkhdr_CK; // @[el2_lib.scala 452:26]
+  wire  clkhdr_EN; // @[el2_lib.scala 452:26]
+  wire  clkhdr_SE; // @[el2_lib.scala 452:26]
+  TEC_RV_ICG clkhdr ( // @[el2_lib.scala 452:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 453:14]
+  assign clkhdr_CK = io_clk; // @[el2_lib.scala 454:18]
+  assign clkhdr_EN = io_en; // @[el2_lib.scala 455:18]
+  assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 456:18]
+endmodule
 module el2_ifu_ifc_ctl(
   input         clock,
   input         reset,
@@ -37,6 +58,10 @@ module el2_ifu_ifc_ctl(
   reg [31:0] _RAND_5;
   reg [31:0] _RAND_6;
 `endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_l1clk; // @[el2_lib.scala 472:23]
+  wire  rvclkhdr_io_clk; // @[el2_lib.scala 472:23]
+  wire  rvclkhdr_io_en; // @[el2_lib.scala 472:23]
+  wire  rvclkhdr_io_scan_mode; // @[el2_lib.scala 472:23]
   reg  dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 63:58]
   wire  dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 62:36]
   reg  miss_a; // @[el2_ifu_ifc_ctl.scala 65:44]
@@ -54,7 +79,7 @@ module el2_ifu_ifc_ctl(
   wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
-  wire [29:0] address_upper = {io_ifc_fetch_addr_f[30:1]} + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
+  wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
   wire  _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
   wire  _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
   wire  fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
@@ -111,7 +136,6 @@ module el2_ifu_ifc_ctl(
   wire  _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
   wire  _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
   wire  _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
-  wire  fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
   wire  _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
   wire  _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
   wire  _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
@@ -140,8 +164,8 @@ module el2_ifu_ifc_ctl(
   wire  _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctl.scala 127:84]
   wire  _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctl.scala 126:60]
   wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
-  wire  iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 216:47]
+  wire  iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 219:47]
-  wire  iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 219:29]
+  wire  iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 222:29]
   wire  _T_145 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 133:30]
   wire  _T_148 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 134:16]
   wire  _T_149 = _T_145 | _T_148; // @[el2_ifu_ifc_ctl.scala 133:53]
@@ -154,7 +178,13 @@ module el2_ifu_ifc_ctl(
   wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
   wire [31:0] _T_161 = io_dec_tlu_mrac_ff >> _T_160; // @[el2_ifu_ifc_ctl.scala 138:53]
   reg  _T_164; // @[el2_ifu_ifc_ctl.scala 140:57]
-  reg [30:0] _T_166; // @[Reg.scala 27:20]
+  reg [30:0] _T_166; // @[el2_lib.scala 478:16]
+  rvclkhdr rvclkhdr ( // @[el2_lib.scala 472:23]
+    .io_l1clk(rvclkhdr_io_l1clk),
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en),
+    .io_scan_mode(rvclkhdr_io_scan_mode)
+  );
   assign io_ifc_fetch_addr_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:23]
   assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
   assign io_ifc_fetch_req_f = _T_164; // @[el2_ifu_ifc_ctl.scala 140:22]
@@ -165,6 +195,9 @@ module el2_ifu_ifc_ctl(
   assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 132:25]
   assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 137:30]
   assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 133:24]
+  assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 474:18]
+  assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 475:17]
+  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -284,10 +317,10 @@ end // initial
       _T_164 <= io_ifc_fetch_req_bf;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
     if (reset) begin
       _T_166 <= 31'h0;
-    end else if (fetch_bf_en) begin
+    end else begin
       _T_166 <= io_ifc_fetch_addr_bf;
     end
   end

el2_ifu_mem_ctl.anno.json

@@ -350,6 +350,11 @@
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"
   },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_ifu_mem_ctl.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."

el2_lsu_addrcheck.anno.json

@@ -0,0 +1,105 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_exc_mscause_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_misaligned_fault_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_external_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_store",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_load",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_by",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_half",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_dec_tlu_mrac_ff"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_dccm_access_error_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_fir_nondccm_access_error_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_fast_int",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_lsu_addrcheck|el2_lsu_addrcheck>io_access_fault_d",
+    "sources":[
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_valid",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_dma",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_addr_in_pic_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_lsu_pkt_d_word",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_rs1_region_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_start_addr_d",
+      "~el2_lsu_addrcheck|el2_lsu_addrcheck>io_end_addr_d"
+    ]
+  },
+  {
+    "class":"logger.LogLevelAnnotation",
+    "globalLogLevel":{
+      
+    }
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_lsu_addrcheck"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_lsu_addrcheck.fir

@@ -0,0 +1,280 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_lsu_addrcheck : 
+  module rvrangecheck : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
+    
+    wire start_addr : UInt<32> @[beh_lib.scala 139:25]
+    start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
+    node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
+    node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
+    node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
+    node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
+    io.in_region <= _T_2 @[beh_lib.scala 143:17]
+    node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
+    node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
+    node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
+    io.in_range <= _T_5 @[beh_lib.scala 147:17]
+    
+  module rvrangecheck_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
+    
+    wire start_addr : UInt<32> @[beh_lib.scala 139:25]
+    start_addr <= UInt<6>("h020") @[beh_lib.scala 140:15]
+    node region = bits(start_addr, 31, 28) @[beh_lib.scala 141:27]
+    node _T = bits(io.addr, 31, 28) @[beh_lib.scala 143:28]
+    node _T_1 = bits(region, 3, 0) @[beh_lib.scala 143:60]
+    node _T_2 = eq(_T, _T_1) @[beh_lib.scala 143:50]
+    io.in_region <= _T_2 @[beh_lib.scala 143:17]
+    node _T_3 = bits(io.addr, 31, 15) @[beh_lib.scala 147:28]
+    node _T_4 = bits(start_addr, 31, 15) @[beh_lib.scala 147:57]
+    node _T_5 = eq(_T_3, _T_4) @[beh_lib.scala 147:43]
+    io.in_range <= _T_5 @[beh_lib.scala 147:17]
+    
+  module el2_lsu_addrcheck : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
+    
+    wire start_addr_in_dccm_d : UInt<1>
+    start_addr_in_dccm_d <= UInt<1>("h00")
+    wire start_addr_in_dccm_region_d : UInt<1>
+    start_addr_in_dccm_region_d <= UInt<1>("h00")
+    wire end_addr_in_dccm_d : UInt<1>
+    end_addr_in_dccm_d <= UInt<1>("h00")
+    wire end_addr_in_dccm_region_d : UInt<1>
+    end_addr_in_dccm_region_d <= UInt<1>("h00")
+    start_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 61:36]
+    start_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 62:36]
+    end_addr_in_dccm_d <= UInt<1>("h00") @[w.scala 63:36]
+    end_addr_in_dccm_region_d <= UInt<1>("h00") @[w.scala 64:36]
+    wire addr_in_iccm : UInt<1>
+    addr_in_iccm <= UInt<1>("h00")
+    addr_in_iccm <= UInt<1>("h01") @[w.scala 72:18]
+    inst start_addr_pic_rangecheck of rvrangecheck @[w.scala 78:41]
+    start_addr_pic_rangecheck.clock <= clock
+    start_addr_pic_rangecheck.reset <= reset
+    node _T = bits(io.start_addr_d, 31, 0) @[w.scala 79:55]
+    start_addr_pic_rangecheck.io.addr <= _T @[w.scala 79:37]
+    inst end_addr_pic_rangecheck of rvrangecheck_1 @[w.scala 84:39]
+    end_addr_pic_rangecheck.clock <= clock
+    end_addr_pic_rangecheck.reset <= reset
+    node _T_1 = bits(io.end_addr_d, 31, 0) @[w.scala 85:51]
+    end_addr_pic_rangecheck.io.addr <= _T_1 @[w.scala 85:35]
+    node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 89:60]
+    node _T_2 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:48]
+    node _T_3 = eq(_T_2, UInt<4>("h0f")) @[w.scala 90:54]
+    node _T_4 = bits(io.rs1_region_d, 3, 0) @[w.scala 90:91]
+    node _T_5 = eq(_T_4, UInt<4>("h0f")) @[w.scala 90:97]
+    node base_reg_dccm_or_pic = or(_T_3, _T_5) @[w.scala 90:73]
+    node _T_6 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[w.scala 91:57]
+    io.addr_in_dccm_d <= _T_6 @[w.scala 91:32]
+    node _T_7 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[w.scala 92:56]
+    io.addr_in_pic_d <= _T_7 @[w.scala 92:32]
+    node _T_8 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 94:63]
+    node _T_9 = not(_T_8) @[w.scala 94:33]
+    io.addr_external_d <= _T_9 @[w.scala 94:30]
+    node _T_10 = bits(io.start_addr_d, 31, 28) @[w.scala 95:51]
+    node csr_idx = cat(_T_10, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_11 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[w.scala 96:50]
+    node _T_12 = bits(_T_11, 0, 0) @[w.scala 96:50]
+    node _T_13 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[w.scala 96:92]
+    node _T_14 = or(_T_13, addr_in_iccm) @[w.scala 96:121]
+    node _T_15 = not(_T_14) @[w.scala 96:62]
+    node _T_16 = and(_T_12, _T_15) @[w.scala 96:60]
+    node _T_17 = and(_T_16, io.lsu_pkt_d.valid) @[w.scala 96:137]
+    node _T_18 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[w.scala 96:180]
+    node is_sideeffects_d = and(_T_17, _T_18) @[w.scala 96:158]
+    node _T_19 = bits(io.start_addr_d, 1, 0) @[w.scala 97:69]
+    node _T_20 = eq(_T_19, UInt<1>("h00")) @[w.scala 97:75]
+    node _T_21 = and(io.lsu_pkt_d.word, _T_20) @[w.scala 97:51]
+    node _T_22 = bits(io.start_addr_d, 0, 0) @[w.scala 97:124]
+    node _T_23 = eq(_T_22, UInt<1>("h00")) @[w.scala 97:128]
+    node _T_24 = and(io.lsu_pkt_d.half, _T_23) @[w.scala 97:106]
+    node _T_25 = or(_T_21, _T_24) @[w.scala 97:85]
+    node is_aligned_d = or(_T_25, io.lsu_pkt_d.by) @[w.scala 97:138]
+    node _T_26 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_27 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_28 = cat(_T_27, _T_26) @[Cat.scala 29:58]
+    node _T_29 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_30 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_31 = cat(_T_30, _T_29) @[Cat.scala 29:58]
+    node _T_32 = cat(_T_31, _T_28) @[Cat.scala 29:58]
+    node _T_33 = orr(_T_32) @[w.scala 101:98]
+    node _T_34 = not(_T_33) @[w.scala 100:33]
+    node _T_35 = bits(io.start_addr_d, 31, 0) @[w.scala 102:49]
+    node _T_36 = or(_T_35, UInt<31>("h07fffffff")) @[w.scala 102:56]
+    node _T_37 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 102:105]
+    node _T_38 = eq(_T_36, _T_37) @[w.scala 102:80]
+    node _T_39 = and(UInt<1>("h01"), _T_38) @[w.scala 102:30]
+    node _T_40 = bits(io.start_addr_d, 31, 0) @[w.scala 103:49]
+    node _T_41 = or(_T_40, UInt<30>("h03fffffff")) @[w.scala 103:56]
+    node _T_42 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 103:105]
+    node _T_43 = eq(_T_41, _T_42) @[w.scala 103:80]
+    node _T_44 = and(UInt<1>("h01"), _T_43) @[w.scala 103:30]
+    node _T_45 = or(_T_39, _T_44) @[w.scala 102:129]
+    node _T_46 = bits(io.start_addr_d, 31, 0) @[w.scala 104:49]
+    node _T_47 = or(_T_46, UInt<29>("h01fffffff")) @[w.scala 104:56]
+    node _T_48 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 104:105]
+    node _T_49 = eq(_T_47, _T_48) @[w.scala 104:80]
+    node _T_50 = and(UInt<1>("h01"), _T_49) @[w.scala 104:30]
+    node _T_51 = or(_T_45, _T_50) @[w.scala 103:129]
+    node _T_52 = bits(io.start_addr_d, 31, 0) @[w.scala 105:49]
+    node _T_53 = or(_T_52, UInt<28>("h0fffffff")) @[w.scala 105:56]
+    node _T_54 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 105:105]
+    node _T_55 = eq(_T_53, _T_54) @[w.scala 105:80]
+    node _T_56 = and(UInt<1>("h01"), _T_55) @[w.scala 105:30]
+    node _T_57 = or(_T_51, _T_56) @[w.scala 104:129]
+    node _T_58 = bits(io.start_addr_d, 31, 0) @[w.scala 106:49]
+    node _T_59 = or(_T_58, UInt<32>("h0ffffffff")) @[w.scala 106:56]
+    node _T_60 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 106:105]
+    node _T_61 = eq(_T_59, _T_60) @[w.scala 106:80]
+    node _T_62 = and(UInt<1>("h00"), _T_61) @[w.scala 106:30]
+    node _T_63 = or(_T_57, _T_62) @[w.scala 105:129]
+    node _T_64 = bits(io.start_addr_d, 31, 0) @[w.scala 107:49]
+    node _T_65 = or(_T_64, UInt<32>("h0ffffffff")) @[w.scala 107:56]
+    node _T_66 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 107:105]
+    node _T_67 = eq(_T_65, _T_66) @[w.scala 107:80]
+    node _T_68 = and(UInt<1>("h00"), _T_67) @[w.scala 107:30]
+    node _T_69 = or(_T_63, _T_68) @[w.scala 106:129]
+    node _T_70 = bits(io.start_addr_d, 31, 0) @[w.scala 108:49]
+    node _T_71 = or(_T_70, UInt<32>("h0ffffffff")) @[w.scala 108:56]
+    node _T_72 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 108:105]
+    node _T_73 = eq(_T_71, _T_72) @[w.scala 108:80]
+    node _T_74 = and(UInt<1>("h00"), _T_73) @[w.scala 108:30]
+    node _T_75 = or(_T_69, _T_74) @[w.scala 107:129]
+    node _T_76 = bits(io.start_addr_d, 31, 0) @[w.scala 109:49]
+    node _T_77 = or(_T_76, UInt<32>("h0ffffffff")) @[w.scala 109:56]
+    node _T_78 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 109:105]
+    node _T_79 = eq(_T_77, _T_78) @[w.scala 109:80]
+    node _T_80 = and(UInt<1>("h00"), _T_79) @[w.scala 109:30]
+    node _T_81 = or(_T_75, _T_80) @[w.scala 108:129]
+    node _T_82 = bits(io.end_addr_d, 31, 0) @[w.scala 111:48]
+    node _T_83 = or(_T_82, UInt<31>("h07fffffff")) @[w.scala 111:57]
+    node _T_84 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[w.scala 111:106]
+    node _T_85 = eq(_T_83, _T_84) @[w.scala 111:81]
+    node _T_86 = and(UInt<1>("h01"), _T_85) @[w.scala 111:31]
+    node _T_87 = bits(io.end_addr_d, 31, 0) @[w.scala 112:49]
+    node _T_88 = or(_T_87, UInt<30>("h03fffffff")) @[w.scala 112:58]
+    node _T_89 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[w.scala 112:107]
+    node _T_90 = eq(_T_88, _T_89) @[w.scala 112:82]
+    node _T_91 = and(UInt<1>("h01"), _T_90) @[w.scala 112:32]
+    node _T_92 = or(_T_86, _T_91) @[w.scala 111:130]
+    node _T_93 = bits(io.end_addr_d, 31, 0) @[w.scala 113:49]
+    node _T_94 = or(_T_93, UInt<29>("h01fffffff")) @[w.scala 113:58]
+    node _T_95 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[w.scala 113:107]
+    node _T_96 = eq(_T_94, _T_95) @[w.scala 113:82]
+    node _T_97 = and(UInt<1>("h01"), _T_96) @[w.scala 113:32]
+    node _T_98 = or(_T_92, _T_97) @[w.scala 112:131]
+    node _T_99 = bits(io.end_addr_d, 31, 0) @[w.scala 114:49]
+    node _T_100 = or(_T_99, UInt<28>("h0fffffff")) @[w.scala 114:58]
+    node _T_101 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[w.scala 114:107]
+    node _T_102 = eq(_T_100, _T_101) @[w.scala 114:82]
+    node _T_103 = and(UInt<1>("h01"), _T_102) @[w.scala 114:32]
+    node _T_104 = or(_T_98, _T_103) @[w.scala 113:131]
+    node _T_105 = bits(io.end_addr_d, 31, 0) @[w.scala 115:49]
+    node _T_106 = or(_T_105, UInt<32>("h0ffffffff")) @[w.scala 115:58]
+    node _T_107 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 115:107]
+    node _T_108 = eq(_T_106, _T_107) @[w.scala 115:82]
+    node _T_109 = and(UInt<1>("h00"), _T_108) @[w.scala 115:32]
+    node _T_110 = or(_T_104, _T_109) @[w.scala 114:131]
+    node _T_111 = bits(io.end_addr_d, 31, 0) @[w.scala 116:49]
+    node _T_112 = or(_T_111, UInt<32>("h0ffffffff")) @[w.scala 116:58]
+    node _T_113 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 116:107]
+    node _T_114 = eq(_T_112, _T_113) @[w.scala 116:82]
+    node _T_115 = and(UInt<1>("h00"), _T_114) @[w.scala 116:32]
+    node _T_116 = or(_T_110, _T_115) @[w.scala 115:131]
+    node _T_117 = bits(io.end_addr_d, 31, 0) @[w.scala 117:49]
+    node _T_118 = or(_T_117, UInt<32>("h0ffffffff")) @[w.scala 117:58]
+    node _T_119 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 117:107]
+    node _T_120 = eq(_T_118, _T_119) @[w.scala 117:82]
+    node _T_121 = and(UInt<1>("h00"), _T_120) @[w.scala 117:32]
+    node _T_122 = or(_T_116, _T_121) @[w.scala 116:131]
+    node _T_123 = bits(io.end_addr_d, 31, 0) @[w.scala 118:49]
+    node _T_124 = or(_T_123, UInt<32>("h0ffffffff")) @[w.scala 118:58]
+    node _T_125 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[w.scala 118:107]
+    node _T_126 = eq(_T_124, _T_125) @[w.scala 118:82]
+    node _T_127 = and(UInt<1>("h00"), _T_126) @[w.scala 118:32]
+    node _T_128 = or(_T_122, _T_127) @[w.scala 117:131]
+    node _T_129 = and(_T_81, _T_128) @[w.scala 110:7]
+    node non_dccm_access_ok = or(_T_34, _T_129) @[w.scala 101:103]
+    node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[w.scala 120:57]
+    node _T_130 = bits(io.start_addr_d, 1, 0) @[w.scala 121:70]
+    node _T_131 = neq(_T_130, UInt<2>("h00")) @[w.scala 121:76]
+    node _T_132 = not(io.lsu_pkt_d.word) @[w.scala 121:92]
+    node _T_133 = or(_T_131, _T_132) @[w.scala 121:90]
+    node picm_access_fault_d = and(io.addr_in_pic_d, _T_133) @[w.scala 121:51]
+    wire unmapped_access_fault_d : UInt<1>
+    unmapped_access_fault_d <= UInt<1>("h01")
+    wire mpu_access_fault_d : UInt<1>
+    mpu_access_fault_d <= UInt<1>("h01")
+    node _T_134 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[w.scala 126:87]
+    node _T_135 = not(_T_134) @[w.scala 126:64]
+    node _T_136 = and(start_addr_in_dccm_region_d, _T_135) @[w.scala 126:62]
+    node _T_137 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 128:57]
+    node _T_138 = not(_T_137) @[w.scala 128:36]
+    node _T_139 = and(end_addr_in_dccm_region_d, _T_138) @[w.scala 128:34]
+    node _T_140 = or(_T_136, _T_139) @[w.scala 126:112]
+    node _T_141 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[w.scala 130:29]
+    node _T_142 = or(_T_140, _T_141) @[w.scala 128:85]
+    node _T_143 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[w.scala 132:29]
+    node _T_144 = or(_T_142, _T_143) @[w.scala 130:85]
+    unmapped_access_fault_d <= _T_144 @[w.scala 126:29]
+    node _T_145 = not(start_addr_in_dccm_region_d) @[w.scala 134:33]
+    node _T_146 = not(non_dccm_access_ok) @[w.scala 134:64]
+    node _T_147 = and(_T_145, _T_146) @[w.scala 134:62]
+    mpu_access_fault_d <= _T_147 @[w.scala 134:29]
+    node _T_148 = or(unmapped_access_fault_d, mpu_access_fault_d) @[w.scala 146:49]
+    node _T_149 = or(_T_148, picm_access_fault_d) @[w.scala 146:70]
+    node _T_150 = or(_T_149, regpred_access_fault_d) @[w.scala 146:92]
+    node _T_151 = and(_T_150, io.lsu_pkt_d.valid) @[w.scala 146:118]
+    node _T_152 = not(io.lsu_pkt_d.dma) @[w.scala 146:141]
+    node _T_153 = and(_T_151, _T_152) @[w.scala 146:139]
+    io.access_fault_d <= _T_153 @[w.scala 146:21]
+    node _T_154 = bits(unmapped_access_fault_d, 0, 0) @[w.scala 147:60]
+    node _T_155 = bits(mpu_access_fault_d, 0, 0) @[w.scala 147:100]
+    node _T_156 = bits(regpred_access_fault_d, 0, 0) @[w.scala 147:144]
+    node _T_157 = bits(picm_access_fault_d, 0, 0) @[w.scala 147:185]
+    node _T_158 = mux(_T_157, UInt<4>("h06"), UInt<4>("h00")) @[w.scala 147:164]
+    node _T_159 = mux(_T_156, UInt<4>("h05"), _T_158) @[w.scala 147:120]
+    node _T_160 = mux(_T_155, UInt<4>("h03"), _T_159) @[w.scala 147:80]
+    node access_fault_mscause_d = mux(_T_154, UInt<4>("h02"), _T_160) @[w.scala 147:35]
+    node _T_161 = bits(io.start_addr_d, 31, 28) @[w.scala 148:53]
+    node _T_162 = bits(io.end_addr_d, 31, 28) @[w.scala 148:78]
+    node regcross_misaligned_fault_d = neq(_T_161, _T_162) @[w.scala 148:61]
+    node _T_163 = not(is_aligned_d) @[w.scala 149:59]
+    node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_163) @[w.scala 149:57]
+    node _T_164 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[w.scala 150:90]
+    node _T_165 = or(regcross_misaligned_fault_d, _T_164) @[w.scala 150:57]
+    node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[w.scala 150:113]
+    node _T_167 = not(io.lsu_pkt_d.dma) @[w.scala 150:136]
+    node _T_168 = and(_T_166, _T_167) @[w.scala 150:134]
+    io.misaligned_fault_d <= _T_168 @[w.scala 150:25]
+    node _T_169 = bits(sideeffect_misaligned_fault_d, 0, 0) @[w.scala 151:111]
+    node _T_170 = mux(_T_169, UInt<4>("h01"), UInt<4>("h00")) @[w.scala 151:80]
+    node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_170) @[w.scala 151:39]
+    node _T_171 = bits(io.misaligned_fault_d, 0, 0) @[w.scala 152:50]
+    node _T_172 = bits(misaligned_fault_mscause_d, 3, 0) @[w.scala 152:84]
+    node _T_173 = bits(access_fault_mscause_d, 3, 0) @[w.scala 152:113]
+    node _T_174 = mux(_T_171, _T_172, _T_173) @[w.scala 152:27]
+    io.exc_mscause_d <= _T_174 @[w.scala 152:21]
+    node _T_175 = not(start_addr_in_dccm_d) @[w.scala 153:66]
+    node _T_176 = and(start_addr_in_dccm_region_d, _T_175) @[w.scala 153:64]
+    node _T_177 = not(end_addr_in_dccm_d) @[w.scala 153:120]
+    node _T_178 = and(end_addr_in_dccm_region_d, _T_177) @[w.scala 153:118]
+    node _T_179 = or(_T_176, _T_178) @[w.scala 153:88]
+    node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[w.scala 153:142]
+    node _T_181 = and(_T_180, io.lsu_pkt_d.fast_int) @[w.scala 153:163]
+    io.fir_dccm_access_error_d <= _T_181 @[w.scala 153:31]
+    node _T_182 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[w.scala 154:66]
+    node _T_183 = not(_T_182) @[w.scala 154:36]
+    node _T_184 = and(_T_183, io.lsu_pkt_d.valid) @[w.scala 154:95]
+    node _T_185 = and(_T_184, io.lsu_pkt_d.fast_int) @[w.scala 154:116]
+    io.fir_nondccm_access_error_d <= _T_185 @[w.scala 154:33]
+    reg _T_186 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[w.scala 156:60]
+    _T_186 <= is_sideeffects_d @[w.scala 156:60]
+    io.is_sideeffects_m <= _T_186 @[w.scala 156:50]
+    

el2_lsu_addrcheck.v

@@ -0,0 +1,111 @@
+module rvrangecheck(
+  input  [31:0] io_addr,
+  output        io_in_range,
+  output        io_in_region
+);
+  assign io_in_range = io_addr[31:15] == 17'h0; // @[beh_lib.scala 147:17]
+  assign io_in_region = io_addr[31:28] == 4'h0; // @[beh_lib.scala 143:17]
+endmodule
+module el2_lsu_addrcheck(
+  input         clock,
+  input         reset,
+  input         io_lsu_c2_m_clk,
+  input  [31:0] io_start_addr_d,
+  input  [31:0] io_end_addr_d,
+  input         io_lsu_pkt_d_fast_int,
+  input         io_lsu_pkt_d_by,
+  input         io_lsu_pkt_d_half,
+  input         io_lsu_pkt_d_word,
+  input         io_lsu_pkt_d_dword,
+  input         io_lsu_pkt_d_load,
+  input         io_lsu_pkt_d_store,
+  input         io_lsu_pkt_d_unsign,
+  input         io_lsu_pkt_d_dma,
+  input         io_lsu_pkt_d_store_data_bypass_d,
+  input         io_lsu_pkt_d_load_ldst_bypass_d,
+  input         io_lsu_pkt_d_store_data_bypass_m,
+  input         io_lsu_pkt_d_valid,
+  input  [31:0] io_dec_tlu_mrac_ff,
+  input  [3:0]  io_rs1_region_d,
+  input  [31:0] io_rs1_d,
+  output        io_is_sideeffects_m,
+  output        io_addr_in_dccm_d,
+  output        io_addr_in_pic_d,
+  output        io_addr_external_d,
+  output        io_access_fault_d,
+  output        io_misaligned_fault_d,
+  output [3:0]  io_exc_mscause_d,
+  output        io_fir_dccm_access_error_d,
+  output        io_fir_nondccm_access_error_d,
+  input         io_scan_mode
+);
+  wire [31:0] start_addr_pic_rangecheck_io_addr; // @[w.scala 78:41]
+  wire  start_addr_pic_rangecheck_io_in_range; // @[w.scala 78:41]
+  wire  start_addr_pic_rangecheck_io_in_region; // @[w.scala 78:41]
+  wire [31:0] end_addr_pic_rangecheck_io_addr; // @[w.scala 84:39]
+  wire  end_addr_pic_rangecheck_io_in_range; // @[w.scala 84:39]
+  wire  end_addr_pic_rangecheck_io_in_region; // @[w.scala 84:39]
+  wire  start_addr_dccm_or_pic = start_addr_pic_rangecheck_io_in_region; // @[w.scala 89:60]
+  wire  _T_3 = io_rs1_region_d == 4'hf; // @[w.scala 90:54]
+  wire  base_reg_dccm_or_pic = _T_3 | _T_3; // @[w.scala 90:73]
+  wire [31:0] _T_36 = io_start_addr_d | 32'h7fffffff; // @[w.scala 102:56]
+  wire  _T_38 = _T_36 == 32'h7fffffff; // @[w.scala 102:80]
+  wire [31:0] _T_41 = io_start_addr_d | 32'h3fffffff; // @[w.scala 103:56]
+  wire  _T_43 = _T_41 == 32'hffffffff; // @[w.scala 103:80]
+  wire  _T_45 = _T_38 | _T_43; // @[w.scala 102:129]
+  wire [31:0] _T_47 = io_start_addr_d | 32'h1fffffff; // @[w.scala 104:56]
+  wire  _T_49 = _T_47 == 32'hbfffffff; // @[w.scala 104:80]
+  wire  _T_51 = _T_45 | _T_49; // @[w.scala 103:129]
+  wire [31:0] _T_53 = io_start_addr_d | 32'hfffffff; // @[w.scala 105:56]
+  wire  _T_55 = _T_53 == 32'h8fffffff; // @[w.scala 105:80]
+  wire  _T_57 = _T_51 | _T_55; // @[w.scala 104:129]
+  wire [31:0] _T_83 = io_end_addr_d | 32'h7fffffff; // @[w.scala 111:57]
+  wire  _T_85 = _T_83 == 32'h7fffffff; // @[w.scala 111:81]
+  wire [31:0] _T_88 = io_end_addr_d | 32'h3fffffff; // @[w.scala 112:58]
+  wire  _T_90 = _T_88 == 32'hffffffff; // @[w.scala 112:82]
+  wire  _T_92 = _T_85 | _T_90; // @[w.scala 111:130]
+  wire [31:0] _T_94 = io_end_addr_d | 32'h1fffffff; // @[w.scala 113:58]
+  wire  _T_96 = _T_94 == 32'hbfffffff; // @[w.scala 113:82]
+  wire  _T_98 = _T_92 | _T_96; // @[w.scala 112:131]
+  wire [31:0] _T_100 = io_end_addr_d | 32'hfffffff; // @[w.scala 114:58]
+  wire  _T_102 = _T_100 == 32'h8fffffff; // @[w.scala 114:82]
+  wire  _T_104 = _T_98 | _T_102; // @[w.scala 113:131]
+  wire  non_dccm_access_ok = _T_57 & _T_104; // @[w.scala 110:7]
+  wire  regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[w.scala 120:57]
+  wire  _T_131 = io_start_addr_d[1:0] != 2'h0; // @[w.scala 121:76]
+  wire  _T_132 = ~io_lsu_pkt_d_word; // @[w.scala 121:92]
+  wire  _T_133 = _T_131 | _T_132; // @[w.scala 121:90]
+  wire  picm_access_fault_d = io_addr_in_pic_d & _T_133; // @[w.scala 121:51]
+  wire  mpu_access_fault_d = ~non_dccm_access_ok; // @[w.scala 134:64]
+  wire  _T_149 = mpu_access_fault_d | picm_access_fault_d; // @[w.scala 146:70]
+  wire  _T_150 = _T_149 | regpred_access_fault_d; // @[w.scala 146:92]
+  wire  _T_151 = _T_150 & io_lsu_pkt_d_valid; // @[w.scala 146:118]
+  wire  _T_152 = ~io_lsu_pkt_d_dma; // @[w.scala 146:141]
+  wire [3:0] _T_158 = picm_access_fault_d ? 4'h6 : 4'h0; // @[w.scala 147:164]
+  wire [3:0] _T_159 = regpred_access_fault_d ? 4'h5 : _T_158; // @[w.scala 147:120]
+  wire [3:0] access_fault_mscause_d = mpu_access_fault_d ? 4'h3 : _T_159; // @[w.scala 147:80]
+  wire  regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[w.scala 148:61]
+  wire  _T_166 = regcross_misaligned_fault_d & io_lsu_pkt_d_valid; // @[w.scala 150:113]
+  wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : 4'h0; // @[w.scala 151:39]
+  rvrangecheck start_addr_pic_rangecheck ( // @[w.scala 78:41]
+    .io_addr(start_addr_pic_rangecheck_io_addr),
+    .io_in_range(start_addr_pic_rangecheck_io_in_range),
+    .io_in_region(start_addr_pic_rangecheck_io_in_region)
+  );
+  rvrangecheck end_addr_pic_rangecheck ( // @[w.scala 84:39]
+    .io_addr(end_addr_pic_rangecheck_io_addr),
+    .io_in_range(end_addr_pic_rangecheck_io_in_range),
+    .io_in_region(end_addr_pic_rangecheck_io_in_region)
+  );
+  assign io_is_sideeffects_m = 1'h0; // @[w.scala 156:50]
+  assign io_addr_in_dccm_d = 1'h0; // @[w.scala 91:32]
+  assign io_addr_in_pic_d = start_addr_pic_rangecheck_io_in_range & end_addr_pic_rangecheck_io_in_range; // @[w.scala 92:32]
+  assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[w.scala 94:30]
+  assign io_access_fault_d = _T_151 & _T_152; // @[w.scala 146:21]
+  assign io_misaligned_fault_d = _T_166 & _T_152; // @[w.scala 150:25]
+  assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[w.scala 152:21]
+  assign io_fir_dccm_access_error_d = 1'h0; // @[w.scala 153:31]
+  assign io_fir_nondccm_access_error_d = io_lsu_pkt_d_valid & io_lsu_pkt_d_fast_int; // @[w.scala 154:33]
+  assign start_addr_pic_rangecheck_io_addr = io_start_addr_d; // @[w.scala 79:37]
+  assign end_addr_pic_rangecheck_io_addr = io_end_addr_d; // @[w.scala 85:35]
+endmodule

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -155,7 +155,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5)
 
   val iccm_single_ecc_error = WireInit(UInt(2.W), 0.U)
-  val ifc_fetch_req_f = WireInit(Bool(), 0.U)
+  val ifc_fetch_req_f = WireInit(Bool(), false.B)
   val miss_pending = WireInit(Bool(), false.B)
   val scnd_miss_req = WireInit(Bool(), false.B)
   val dma_iccm_req_f = WireInit(Bool(), false.B)
@@ -185,8 +185,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val flush_final_f = RegNext(io.exu_flush_final, 0.U)
   val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
   val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
-  //val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
+  val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
-  //val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken.asBool, io.scan_mode)
+  val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode)
   io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool()
   io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start
   io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb
@@ -261,11 +261,11 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
 
   val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & io.ic_tag_valid)
   val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf)
-  uncacheable_miss_scnd_ff := RegNext(uncacheable_miss_scnd_in, 0.U)
+  uncacheable_miss_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_scnd_in, 0.U)}
   val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf)
-  imb_scnd_ff := RegNext(imb_scnd_in, 0.U)
+  imb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_scnd_in, 0.U)}
-  way_status_mb_scnd_ff := RegNext(way_status_mb_scnd_in, 0.U)
+  way_status_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_scnd_in, 0.U)}
-  tagv_mb_scnd_ff := RegNext(tagv_mb_scnd_in, 0.U)
+  tagv_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_scnd_in, 0.U)}
 
   val ic_req_addr_bits_hi_3 = bus_rd_addr_count
   val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff)
@@ -305,24 +305,24 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val reset_ic_in = miss_pending & !scnd_miss_req_q &  (reset_all_tags |  reset_ic_ff)
   reset_ic_ff := RegNext(reset_ic_in)
   val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
-  ifu_fetch_addr_int_f := RegNext(io.ifc_fetch_addr_bf, 0.U)
+  ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)}
   val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0)
-  uncacheable_miss_ff := RegNext(uncacheable_miss_in, 0.U)
+  uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)}
-  imb_ff := RegNext(imb_in)
+  imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in)}
   val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
   val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
     Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
   miss_addr := RegNext(miss_addr_in, 0.U)
-  way_status_mb_ff := RegNext(way_status_mb_in, 0.U)
+  way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)}
-  tagv_mb_ff := RegNext(tagv_mb_in, 0.U)
+  tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)}
   val stream_miss_f = WireInit(Bool(), 0.U)
   val ifc_fetch_req_qual_bf  = io.ifc_fetch_req_bf  & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
   val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U)
   ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
-  ifc_iccm_access_f := RegNext(io.ifc_iccm_access_bf, 0.U)
+  ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)}
   val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
-  ifc_region_acc_fault_final_f := RegNext(ifc_region_acc_fault_final_bf, 0.U)
+  ifc_region_acc_fault_final_f := withClock(fetch_bf_f_c1_clk){RegNext(ifc_region_acc_fault_final_bf, 0.U)}
-  val ifc_region_acc_fault_f = RegNext(io.ifc_region_acc_fault_bf, 0.U)
+  val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)}
   val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
   io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
   io.ifu_miss_state_idle := miss_state === idle_C

src/main/scala/lib/el2_lib.scala

@@ -25,14 +25,14 @@ trait param {
   val BUILD_AXI4             = true
   val BUILD_AXI_NATIVE       = true
   val BUS_PRTY_DEFAULT       = 3
-  val DATA_ACCESS_ADDR0      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR0      = 0x00000000L //.U(32.W)
-  val DATA_ACCESS_ADDR1      = 0xC0000000 //.U(32.W)
+  val DATA_ACCESS_ADDR1      = 0xC0000000L //.U(32.W)
-  val DATA_ACCESS_ADDR2      = 0xA0000000 //.U(32.W)
+  val DATA_ACCESS_ADDR2      = 0xA0000000L //.U(32.W)
-  val DATA_ACCESS_ADDR3      = 0x80000000 //.U(32.W)
+  val DATA_ACCESS_ADDR3      = 0x80000000L //.U(32.W)
-  val DATA_ACCESS_ADDR4      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR4      = 0x00000000L //.U(32.W)
-  val DATA_ACCESS_ADDR5      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR5      = 0x00000000L //.U(32.W)
-  val DATA_ACCESS_ADDR6      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR6      = 0x00000000L //.U(32.W)
-  val DATA_ACCESS_ADDR7      = 0x00000000 //.U(32.W)
+  val DATA_ACCESS_ADDR7      = 0x00000000L //.U(32.W)
   val DATA_ACCESS_ENABLE0    = true //.U(1.W)
   val DATA_ACCESS_ENABLE1    = true //.U(1.W)
   val DATA_ACCESS_ENABLE2    = true //.U(1.W)
@@ -41,14 +41,14 @@ trait param {
   val DATA_ACCESS_ENABLE5    = false //.U(1.W)
   val DATA_ACCESS_ENABLE6    = false //.U(1.W)
   val DATA_ACCESS_ENABLE7    = false //.U(1.W)
-  val DATA_ACCESS_MASK0      = 0x7FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK0      = 0x7FFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK1      = 0x3FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK1      = 0x3FFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK2      = 0x1FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK2      = 0x1FFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK3      = 0x0FFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK3      = 0x0FFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK4      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK4      = 0xFFFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK5      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK5      = 0xFFFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK6      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK6      = 0xFFFFFFFFL //.U(32.W)
-  val DATA_ACCESS_MASK7      = 0xFFFFFFFF //.U(32.W)
+  val DATA_ACCESS_MASK7      = 0xFFFFFFFFL //.U(32.W)
   val DCCM_BANK_BITS         = 2  //.U(3.W)
   val DCCM_BITS              = 16 //.U(5.W)
   val DCCM_BYTE_WIDTH        = 4  //.U(3.W)
@@ -465,11 +465,8 @@ trait el2_lib extends param{
       cg.io.l1clk
     }
   }
- class rvdffe extends Module{
-   val io = IO(new Bundle{
 
-   })
+  ////rvdffe ///////////////////////////////////////////////////////////////////////
- }
   object rvdffe {
     def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
       val obj = Module(new rvclkhdr())

src/main/scala/lsu/w.scala

@@ -0,0 +1,163 @@
+package lsu
+
+import include._
+import lib._
+import snapshot._
+
+import chisel3._
+import chisel3.util._
+import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
+import chisel3.experimental.ChiselEnum
+import chisel3.experimental.{withClock, withReset, withClockAndReset}
+import chisel3.experimental.BundleLiterals._
+import chisel3.tester._
+import chisel3.tester.RawTester.test
+import chisel3.util.HasBlackBoxResource
+import chisel3.experimental.chiselName
+@chiselName
+class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib {
+  val io = IO(new Bundle{
+  val lsu_c2_m_clk        = Input(Clock())
+
+  val start_addr_d        = Input(UInt(32.W))
+  val end_addr_d          = Input(UInt(32.W))
+  val lsu_pkt_d           = Input(new el2_lsu_pkt_t)
+  val dec_tlu_mrac_ff     = Input(UInt(32.W))
+  val rs1_region_d        = Input(UInt(4.W))
+  val rs1_d               = Input(UInt(32.W))
+
+
+  val is_sideeffects_m    = Output(UInt(1.W))
+  val addr_in_dccm_d      = Output(UInt(1.W))
+  val addr_in_pic_d       = Output(UInt(1.W))
+  val addr_external_d     = Output(UInt(1.W))
+  val access_fault_d      = Output(UInt(1.W))
+  val misaligned_fault_d  = Output(UInt(1.W))
+  val exc_mscause_d       = Output(UInt(4.W))
+  val fir_dccm_access_error_d     = Output(UInt(1.W))
+  val fir_nondccm_access_error_d  = Output(UInt(1.W))
+  val scan_mode                   = Input(UInt(1.W))})
+
+  val start_addr_in_dccm_d         = WireInit(0.U(1.W))
+  val start_addr_in_dccm_region_d  = WireInit(0.U(1.W))
+  val end_addr_in_dccm_d           = WireInit(0.U(1.W))
+  val end_addr_in_dccm_region_d    = WireInit(0.U(1.W))
+
+  //DCCM check
+  // Start address check
+  if(DCCM_ENABLE==1){  // Gen_dccm_enable
+    val start_addr_dccm_rangecheck = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE))
+    start_addr_dccm_rangecheck.io.addr  := io.start_addr_d
+    start_addr_in_dccm_d                := start_addr_dccm_rangecheck.io.in_range
+    start_addr_in_dccm_region_d         := start_addr_dccm_rangecheck.io.in_region
+
+    // End address check
+    val end_addr_dccm_rangecheck   = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE))
+    end_addr_dccm_rangecheck.io.addr    := io.end_addr_d
+    end_addr_in_dccm_d                  := end_addr_dccm_rangecheck.io.in_range
+    end_addr_in_dccm_region_d           := end_addr_dccm_rangecheck.io.in_region
+  }
+  else{  //Gen_dccm_disable
+    start_addr_in_dccm_d           := 0.U
+    start_addr_in_dccm_region_d    := 0.U
+    end_addr_in_dccm_d             := 0.U
+    end_addr_in_dccm_region_d      := 0.U
+  }
+
+  val addr_in_iccm  = WireInit(0.U(1.W))
+  if(ICCM_ENABLE == 1){  //check_iccm
+    addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION)
+  }
+  else{
+    addr_in_iccm := 1.U
+  }
+
+
+  //PIC memory check
+  //start address check
+  val start_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE))
+  start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0)
+  val start_addr_in_pic_d            = start_addr_pic_rangecheck.io.in_range
+  val start_addr_in_pic_region_d     = start_addr_pic_rangecheck.io.in_region
+
+  //End address check
+  val end_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE))
+  end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0)
+  val end_addr_in_pic_d            = end_addr_pic_rangecheck.io.in_range
+  val end_addr_in_pic_region_d     = end_addr_pic_rangecheck.io.in_region
+
+  val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
+  val base_reg_dccm_or_pic   = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region
+  io.addr_in_dccm_d            := (start_addr_in_dccm_d & end_addr_in_dccm_d)
+  io.addr_in_pic_d             := (start_addr_in_pic_d & end_addr_in_pic_d)
+
+  io.addr_external_d         := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
+  val csr_idx                = Cat(io.start_addr_d(31,28),1.U)
+  val is_sideeffects_d       = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load)  //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
+  val is_aligned_d           = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
+
+
+  val non_dccm_access_ok     = (~(Cat(DATA_ACCESS_ENABLE0.B, DATA_ACCESS_ENABLE1.B, DATA_ACCESS_ENABLE2.B, DATA_ACCESS_ENABLE3.B,
+    DATA_ACCESS_ENABLE4.B, DATA_ACCESS_ENABLE5.B, DATA_ACCESS_ENABLE6.B, DATA_ACCESS_ENABLE7.B)).orR) |
+    (((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) | //0111
+      (DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) | //1111
+      (DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) | //1011
+      (DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) | //1000
+      (DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
+      (DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
+      (DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
+      (DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U)))
+      &
+      ((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) |
+        (DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) |
+        (DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) |
+        (DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) |
+        (DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
+        (DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
+        (DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
+        (DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0)   | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U))))
+
+  val regpred_access_fault_d  = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
+  val picm_access_fault_d     = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | ~io.lsu_pkt_d.word))
+
+  val unmapped_access_fault_d = WireInit(1.U(1.W))
+  val mpu_access_fault_d      = WireInit(1.U(1.W))
+  if(DCCM_REGION == PIC_REGION){
+    unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d))  |
+      // 0. Addr in dccm/pic region but not in dccm/pic offset
+      (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))       |
+      // 0. Addr in dccm/pic region but not in dccm/pic offset
+      (start_addr_in_dccm_d & end_addr_in_pic_d)                                    |
+      // 0. DCCM -> PIC cross when DCCM/PIC in same region
+      (start_addr_in_pic_d  & end_addr_in_dccm_d))
+    // 0. DCCM -> PIC cross when DCCM/PIC in same region
+    mpu_access_fault_d      := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
+    // 3. Address is not in a populated non-dccm region
+  }
+
+  else{
+    unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)   |
+      (start_addr_in_pic_region_d  & ~start_addr_in_pic_d)  | (end_addr_in_pic_region_d & ~end_addr_in_pic_d))
+    mpu_access_fault_d      := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
+    // 3. Address is not in a populated non-dccm region
+  }
+
+  //check width of  access_fault_mscause_d
+  io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
+  val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
+  val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
+  val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
+  io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma
+  val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
+  io.exc_mscause_d  := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
+  io.fir_dccm_access_error_d  := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d   & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
+  io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
+
+  withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
+}
+//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck))
+
+object address_checker extends App{
+  println("Generate Verilog")
+  chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck)
+}