Commit Graph

23 Commits

Author SHA1 Message Date
​Laraib Khan 65d5369d1e 2 bit divider 2021-01-06 09:32:46 +05:00
​Laraib Khan a4474e1299 bus_rst updated 2020-12-30 11:06:59 +05:00
​Laraib Khan 2527f455ca bus_rst updated 2020-12-30 09:50:45 +05:00
​Laraib Khan 119a9ad388 buf_error corrected 2020-12-29 11:26:56 +05:00
​Laraib Khan 45fac8e01d buf_error corrected 2020-12-29 10:47:27 +05:00
​Laraib Khan 1119469d76 buf_rst corrected 2020-12-29 10:36:06 +05:00
​Laraib Khan adce90c0e9 buf_rst corrected 2020-12-29 10:02:46 +05:00
​Laraib Khan c52c6324d9 buf_rst corrected 2020-12-28 18:01:06 +05:00
​Laraib Khan e5b9988491 buf_rst corrected 2020-12-28 17:08:01 +05:00
​Laraib Khan e1c566dae9 rvdffe registers updated 2020-12-28 16:41:59 +05:00
​Laraib Khan bb89af4b68 fpga registers updated 2020-12-28 14:17:13 +05:00
​Laraib Khan 57f1b66c15 bus buffer with buf_nextstate in resp updated 2020-12-28 12:49:43 +05:00
​Laraib Khan 0cd4180d83 bus buffer with buf_nextstate in resp updated 2020-12-28 11:51:11 +05:00
​Laraib Khan 17fe416e15 bus buffer with reg_fpga updated 2020-12-28 10:41:40 +05:00
​Laraib Khan c438fae14a bus buffer added 2020-12-24 16:51:11 +05:00
​Laraib Khan 46ffb7c24f bus buffer added 2020-12-24 16:34:10 +05:00
​Laraib Khan 309087b854 bus buffer added 2020-12-24 15:53:17 +05:00
​Laraib Khan b8b042faa8 lsu with newer release 2020-12-22 15:24:39 +05:00
​Laraib Khan 1c41a85c25 Master updated 2020-12-18 10:14:48 +05:00
​Laraib Khan 15483fd532 Master updated with vsrc 2020-12-17 18:21:54 +05:00
​Laraib Khan c80dac6075 PIC,param,lib,mem.scala added 2020-12-17 09:38:45 +05:00
​Laraib Khan 8616219c43 Bus Buffer Update 2020-12-10 12:09:34 +05:00
​Laraib Khan 3a1fa4fbd7 LSU with Bundling 2020-12-10 09:50:49 +05:00