119 lines
3.9 KiB
Markdown
119 lines
3.9 KiB
Markdown
# EL2 SweRV RISC-V Core Chiselified Version from LAMPRO MELLON
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This repository contains the SweRV-EL2 Core design in CHISEL
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## Background
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Enter here
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## Directory Structure
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├── .idea #
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│ ├── codeStyles #
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│ ├── libraries #
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│ └── modules #
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├── project #
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│ ├── project/target/config-classes #
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│ └── target #
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├── src
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│ ├── main #
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│ ├── resource/vsrc #
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│ └── scala #
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│ ├── dbg #
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│ ├── dec #
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│ ├── dmi #
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│ ├── exu #
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│ ├── ifu #
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│ ├── include #
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│ ├── lib #
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│ ├── lsu #
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│ ├── snapshot #
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│ ├── el2_dma_ctrl.scala #
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│ ├── el2_pic_ctl.scala #
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│ └── el2_swerv.scala #
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│ └── test/scala/lib #
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├── target #
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├── scala-2.12 #
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└── streams #
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└── test_run_dir #
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## Dependencies
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- Verilator **(4.020 or later)** must be installed on the system if running with verilator
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- If adding/removing instructions, espresso must be installed (used by *tools/coredecode*)
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- RISCV tool chain (based on gcc version 7.3 or higher) must be
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installed so that it can be used to prepare RISCV binaries to run.
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## Quickstart guide
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1. Clone the repository
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2. Setup RV_ROOT to point to the path in your local filesystem
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3. Determine your configuration {optional}
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4. Run make with tools/Makefile
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### Configurations
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This script derives the following consistent set of include files :
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### Building a model
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while in a work directory:
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1. Set the RV_ROOT environment variable to the root of the SweRV directory structure.
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Example for bash shell:
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`export RV_ROOT=/path/to/swerv`
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Example for csh or its derivatives:
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`setenv RV_ROOT /path/to/swerv
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2. Create your specific configuration
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Enter here
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3. Running a simple Hello World program (verilator)
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Enter here
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The simulation produces output on the screen like:
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Enter here
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The simulation generates following files:
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Enter here
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You can re-execute simulation using:
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Enter here
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The simulation run/build command has following generic form:
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Enter here
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where,
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Enter here
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If you want to compile a test only, you can run:
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Enter here
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The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
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```
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hello_world - default tes to run, prints Hello World message to screen and console.log
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hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
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hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
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it from there. Runs on EL2 with AXI4 buses only.
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cmark - coremark benchmark running with code and data in external memories
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cmark_dccm - the same as above, running data and stack from DCCM (faster)
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cmark_iccm - the same as above with preloaded code to ICCM.
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```
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**Building an FPGA speed optimized model:**
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Use ``-set=fpga_optimize=1`` option to ``swerv.config`` to build a model that is removes clock gating logic from flop model so that the FPGA builds can run a higher speeds.
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