2018-09-11 00:44:54 +08:00
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/*!
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2018-09-21 19:05:42 +08:00
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\file Execute.h
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2018-09-11 00:44:54 +08:00
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\brief RISC-V ISA implementation
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\author Màrius Montón
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\date August 2018
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*/
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2018-09-21 19:05:42 +08:00
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#ifndef Execute_H
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#define Execute_H
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2018-09-11 00:44:54 +08:00
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "memory.h"
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#include "Instruction.h"
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#include "Registers.h"
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#include "Log.h"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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/**
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* @brief Risc_V execute module
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*/
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2018-09-21 19:05:42 +08:00
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class Execute : sc_module {
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2018-09-11 00:44:54 +08:00
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public:
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/**
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* @brief Constructor
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* @param name module name
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* @param register_bank pointer to register bank to use
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*/
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2018-09-21 19:05:42 +08:00
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Execute(sc_module_name name,
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2018-09-11 00:44:54 +08:00
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Registers *register_bank);
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2018-09-17 18:21:26 +08:00
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/* Quick & dirty way to publish a socket though modules */
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2018-09-21 19:05:42 +08:00
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tlm_utils::simple_initiator_socket<Execute> data_bus;
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2018-09-11 00:44:54 +08:00
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void LUI(Instruction &inst);
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void AUIPC(Instruction &inst);
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void JAL(Instruction &inst);
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void JALR(Instruction &inst);
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void BEQ(Instruction &inst);
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void BNE(Instruction &inst);
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void BLT(Instruction &inst);
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void BGE(Instruction &inst);
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void BLTU(Instruction &inst);
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void BGEU(Instruction &inst);
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void LB(Instruction &inst);
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void LH(Instruction &inst);
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void LW(Instruction &inst);
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void LBU(Instruction &inst);
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void LHU(Instruction &inst);
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void SB(Instruction &inst);
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void SH(Instruction &inst);
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void SW(Instruction &inst);
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void SBU(Instruction &inst);
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void SHU(Instruction &inst);
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void ADDI(Instruction &inst);
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void SLTI(Instruction &inst);
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void SLTIU(Instruction &inst);
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void XORI(Instruction &inst);
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void ORI(Instruction &inst);
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void ANDI(Instruction &inst);
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void SLLI(Instruction &inst);
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void SRLI(Instruction &inst);
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void SRAI(Instruction &inst);
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void ADD(Instruction &inst);
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void SUB(Instruction &inst);
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void SLL(Instruction &inst);
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void SLT(Instruction &inst);
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void SLTU(Instruction &inst);
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void XOR(Instruction &inst);
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void SRL(Instruction &inst);
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void SRA(Instruction &inst);
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void OR(Instruction &inst);
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void AND(Instruction &inst);
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void CSRRW(Instruction &inst);
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void CSRRS(Instruction &inst);
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void CSRRC(Instruction &inst);
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void CSRRWI(Instruction &inst);
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void CSRRSI(Instruction &inst);
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void CSRRCI(Instruction &inst);
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void NOP(Instruction &inst);
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2018-09-17 18:21:26 +08:00
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private:
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uint32_t readDataMem(uint32_t addr, int size);
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void writeDataMem(uint32_t addr, uint32_t data, int size);
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2018-09-11 00:44:54 +08:00
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Registers *regs;
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Performance *perf;
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Log *log;
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};
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#endif
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