risc-v-tlm/inc/CPU.h

65 lines
1.1 KiB
C
Raw Normal View History

2018-09-11 00:44:54 +08:00
/*!
\file CPU.h
\brief Main CPU class
\author Màrius Montón
\date August 2018
*/
#ifndef CPU_BASE_H
#define CPU_BASE_H
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "systemc"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "memory.h"
2018-09-21 19:05:42 +08:00
#include "Execute.h"
2018-09-11 00:44:54 +08:00
#include "Registers.h"
#include "Log.h"
2018-10-15 19:51:41 +08:00
#include "Instruction.h"
#include "C_Instruction.h"
2018-09-11 00:44:54 +08:00
using namespace sc_core;
using namespace sc_dt;
using namespace std;
/**
* @brief ISC_V CPU model
* @param name name of the module
*/
class CPU: sc_module {
public:
tlm_utils::simple_initiator_socket<CPU> instr_bus;
//tlm_utils::simple_initiator_socket<cpu_base> data_bus;
//sc_in<sc_signal<bool> > interrupt;
CPU(sc_module_name name, uint32_t PC);
2018-09-11 00:44:54 +08:00
~CPU();
2018-09-21 19:05:42 +08:00
Execute *exec;
2018-09-11 00:44:54 +08:00
private:
Registers *register_bank;
Performance *perf;
Log *log;
/**
* @brief Executes default ISA instruction
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
2018-10-15 19:51:41 +08:00
bool process_base_instruction(Instruction &inst);
bool process_c_instruction(Instruction &inst);
2018-09-11 00:44:54 +08:00
void CPU_thread(void);
};
#endif