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risc-v-tlm
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If write to HOST, stop simulation

This commit is contained in:
Màrius Montón 2021-11-08 09:21:59 +01:00
parent 24c593e715
commit 08d699d34e
2 changed files with 12 additions and 0 deletions
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4
inc/BusCtrl.h
View File

@ -32,6 +32,8 @@
#define TIMERCMP_MEMORY_ADDRESS_LO 0x40004008
#define TIMERCMP_MEMORY_ADDRESS_HI 0x4000400C
#define TO_HOST_ADDRESS 0x90000000
/**
* @brief Simple bus controller
*
@ -87,6 +89,8 @@ private:
bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
tlm::tlm_dmi &dmi_data);
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
Log *log;
};
#endif

8
src/BusCtrl.cpp
View File

@ -19,6 +19,7 @@ BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
&BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this,
&BusCtrl::invalidate_direct_mem_ptr);
log = Log::getInstance();
}
void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
@ -26,6 +27,13 @@ void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
sc_dt::uint64 adr = trans.get_address() / 4;
if (adr >= TO_HOST_ADDRESS / 4) {
std::cout << "To host\n" << std::flush;
log->SC_log(Log::ERROR) << std::flush;
sc_core::sc_stop();
return;
}
switch (adr) {
case TIMER_MEMORY_ADDRESS_HI / 4:
case TIMER_MEMORY_ADDRESS_LO / 4: