fixed CSRRS and CSRRC bug
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9cd354b822
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0cd34f9f3b
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@ -16,6 +16,21 @@
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#include "Performance.h"
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#include "Performance.h"
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#include "Memory.h"
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#include "Memory.h"
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#define WARL_M_EXTENSION (1 << 12)
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#define WARL_C_EXTENSION (1 << 2)
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#define WARL_I_BASE (1 << 8)
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#define WARL_MXL (1 << 29)
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#define CSR_MSTATUS (0x300)
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#define CSR_MISA (0x301)
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#define CSR_MEDELEG (0x302)
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#define CSR_MIDELEG (0x303)
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#define CSR_MIE (0x304)
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#define CSR_MTVEC (0x305)
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#define CSR_MCOUNTEREN (0x306)
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using namespace sc_core;
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using namespace sc_core;
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using namespace sc_dt;
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using namespace sc_dt;
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using namespace std;
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using namespace std;
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@ -141,18 +156,14 @@ public:
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* @param csr CSR number to access
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* @param csr CSR number to access
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* @return CSR value
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* @return CSR value
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*/
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*/
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inline uint32_t getCSR(int csr) {
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uint32_t getCSR(int csr);
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return CSR[csr];
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}
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/**
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/**
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* @brief Set CSR value
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* @brief Set CSR value
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* @param csr CSR number to access
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* @param csr CSR number to access
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* @param value new value to register
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* @param value new value to register
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*/
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*/
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inline void setCSR(int csr, uint32_t value) {
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void setCSR(int csr, uint32_t value);
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CSR[csr] = value;
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}
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/**
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/**
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* Dump register data to console
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* Dump register data to console
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@ -174,6 +185,8 @@ private:
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*/
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*/
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uint32_t CSR[4096];
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uint32_t CSR[4096];
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Performance *perf;
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Performance *perf;
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void initCSR(void);
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};
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};
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#endif
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#endif
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@ -829,21 +829,23 @@ void Execute::CSRRS(Instruction &inst) {
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/* These operations must be atomical */
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/* These operations must be atomical */
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aux = regs->getCSR(csr);
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aux = regs->getCSR(csr);
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bitmask = regs->getValue(rs1);
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regs->setValue(rd, aux);
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regs->setValue(rd, aux);
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bitmask = regs->getValue(rs1);
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aux2 = aux | bitmask;
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aux2 = aux | bitmask;
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regs->setCSR(csr, aux2);
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regs->setCSR(csr, aux2);
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log->SC_log(Log::INFO) << "CSRRS: CSR #"
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log->SC_log(Log::INFO) << "CSRRS: CSR #"
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<< csr << "(" << aux << ") -> x" << dec << rd
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<< csr << "(0x" << hex << aux << ") -> x" << dec << rd
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<< ". x" << rs1 << " & CSR #" << csr << endl;
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<< ". x" << rs1 << " & CSR #" << csr
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<< " <- 0x" << hex << aux2 << endl;
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}
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}
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void Execute::CSRRC(Instruction &inst) {
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void Execute::CSRRC(Instruction &inst) {
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int rd, rs1;
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int rd, rs1;
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int csr;
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int csr;
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uint32_t bitmask, aux;
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uint32_t bitmask, aux, aux2;
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rd = inst.get_rd();
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rd = inst.get_rd();
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rs1 = inst.get_rs1();
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rs1 = inst.get_rs1();
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@ -855,15 +857,17 @@ void Execute::CSRRC(Instruction &inst) {
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/* These operations must be atomical */
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/* These operations must be atomical */
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aux = regs->getCSR(csr);
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aux = regs->getCSR(csr);
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bitmask = regs->getValue(rs1);
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regs->setValue(rd, aux);
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regs->setValue(rd, aux);
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bitmask = regs->getValue(rs1);
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aux2 = aux & ~bitmask;
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aux = aux & ~bitmask;
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regs->setCSR(csr, aux2);
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regs->setCSR(csr, aux);
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log->SC_log(Log::INFO) << "CSRRC: CSR #"
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log->SC_log(Log::INFO) << "CSRRC: CSR #"
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<< csr << " -> x" << rd
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<< csr << "(0x" << hex << aux << ") -> x" << dec << rd
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<< ". x" << rs1 << " & CSR #" << csr << endl;
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<< ". x" << rs1 << " & CSR #" << csr
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<< " <- 0x" << hex << aux2 << endl;
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}
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}
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void Execute::CSRRWI(Instruction &inst) {
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void Execute::CSRRWI(Instruction &inst) {
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@ -6,6 +6,7 @@ Registers::Registers() {
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memset(CSR, 0, sizeof(uint32_t)*4096);
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memset(CSR, 0, sizeof(uint32_t)*4096);
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perf = Performance::getInstance();
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perf = Performance::getInstance();
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initCSR();
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//register_bank[sp] = 1024-1; // SP points to end of memory
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//register_bank[sp] = 1024-1; // SP points to end of memory
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register_bank[sp] = Memory::SIZE-4;
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register_bank[sp] = Memory::SIZE-4;
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register_PC = 0x10000; // default _start address
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register_PC = 0x10000; // default _start address
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@ -82,3 +83,17 @@ uint32_t Registers::getPC() {
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void Registers::setPC(uint32_t new_pc) {
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void Registers::setPC(uint32_t new_pc) {
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register_PC = new_pc;
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register_PC = new_pc;
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}
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}
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uint32_t Registers::getCSR(int csr) {
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return CSR[csr];
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}
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void Registers::setCSR(int csr, uint32_t value) {
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CSR[csr] = value;
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}
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void Registers::initCSR() {
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CSR[0x301] = WARL_MXL | WARL_M_EXTENSION | WARL_C_EXTENSION | WARL_I_BASE;
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}
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