code clean-up (using clang-tidy)
This commit is contained in:
parent
3b3813bd07
commit
1777a3bc9a
|
@ -64,7 +64,7 @@ public:
|
||||||
* @return return opcode field
|
* @return return opcode field
|
||||||
*/
|
*/
|
||||||
inline int32_t opcode() const override {
|
inline int32_t opcode() const override {
|
||||||
return m_instr.range(31, 27);
|
return static_cast<int32_t>(m_instr.range(31, 27));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -244,7 +244,7 @@ public:
|
||||||
* @return value corresponding to inst(25:20)
|
* @return value corresponding to inst(25:20)
|
||||||
*/
|
*/
|
||||||
inline int32_t get_shamt() const {
|
inline int32_t get_shamt() const {
|
||||||
return m_instr.range(25, 20);
|
return static_cast<int32_t>(m_instr.range(25, 20));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -254,7 +254,7 @@ public:
|
||||||
inline int32_t get_csr() const {
|
inline int32_t get_csr() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr.range(31, 20);
|
aux = static_cast<int32_t>(m_instr.range(31, 20));
|
||||||
|
|
||||||
return aux;
|
return aux;
|
||||||
}
|
}
|
||||||
|
@ -264,7 +264,7 @@ public:
|
||||||
* @return return opcode field
|
* @return return opcode field
|
||||||
*/
|
*/
|
||||||
inline int32_t opcode() const override {
|
inline int32_t opcode() const override {
|
||||||
return m_instr.range(6, 0);
|
return static_cast<int32_t>(m_instr.range(6, 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
bool Exec_LUI() const;
|
bool Exec_LUI() const;
|
||||||
|
|
|
@ -106,11 +106,11 @@ public:
|
||||||
* @return return opcode field
|
* @return return opcode field
|
||||||
*/
|
*/
|
||||||
inline int32_t opcode() const override {
|
inline int32_t opcode() const override {
|
||||||
return m_instr.range(1, 0);
|
return static_cast<int32_t>(m_instr.range(1, 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
inline int32_t get_rdp() const {
|
inline int32_t get_rdp() const {
|
||||||
return m_instr.range(4, 2) + 8;
|
return static_cast<int32_t>(m_instr.range(4, 2) + 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -118,7 +118,7 @@ public:
|
||||||
* @return rs1 field
|
* @return rs1 field
|
||||||
*/
|
*/
|
||||||
inline int32_t get_rs1() const override {
|
inline int32_t get_rs1() const override {
|
||||||
return m_instr.range(11, 7);
|
return static_cast<int32_t>(m_instr.range(11, 7));
|
||||||
}
|
}
|
||||||
|
|
||||||
inline void set_rs1(int32_t value) override {
|
inline void set_rs1(int32_t value) override {
|
||||||
|
@ -126,7 +126,7 @@ public:
|
||||||
}
|
}
|
||||||
|
|
||||||
inline int32_t get_rs1p() const {
|
inline int32_t get_rs1p() const {
|
||||||
return m_instr.range(9, 7) + 8;
|
return static_cast<int32_t>(m_instr.range(9, 7) + 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -134,7 +134,7 @@ public:
|
||||||
* @return rs2 field
|
* @return rs2 field
|
||||||
*/
|
*/
|
||||||
inline int32_t get_rs2() const override {
|
inline int32_t get_rs2() const override {
|
||||||
return m_instr.range(6, 2);
|
return static_cast<int32_t>(m_instr.range(6, 2));
|
||||||
}
|
}
|
||||||
|
|
||||||
inline void set_rs2(int32_t value) override {
|
inline void set_rs2(int32_t value) override {
|
||||||
|
@ -142,11 +142,11 @@ public:
|
||||||
}
|
}
|
||||||
|
|
||||||
inline int32_t get_rs2p() const {
|
inline int32_t get_rs2p() const {
|
||||||
return m_instr.range(4, 2) + 8;
|
return static_cast<int32_t>(m_instr.range(4, 2) + 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
inline int32_t get_funct3() const override {
|
inline int32_t get_funct3() const override {
|
||||||
return m_instr.range(15, 13);
|
return static_cast<int32_t>(m_instr.range(15, 13));
|
||||||
}
|
}
|
||||||
|
|
||||||
inline void set_funct3(int32_t value) override {
|
inline void set_funct3(int32_t value) override {
|
||||||
|
@ -160,7 +160,7 @@ public:
|
||||||
inline int32_t get_imm_I() const {
|
inline int32_t get_imm_I() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr.range(31, 20);
|
aux = static_cast<int32_t>(m_instr.range(31, 20));
|
||||||
|
|
||||||
/* sign extension (optimize) */
|
/* sign extension (optimize) */
|
||||||
if (m_instr[31] == 1) {
|
if (m_instr[31] == 1) {
|
||||||
|
@ -181,8 +181,8 @@ public:
|
||||||
inline int32_t get_imm_S() const {
|
inline int32_t get_imm_S() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr.range(31, 25) << 5;
|
aux = static_cast<int32_t>(m_instr.range(31, 25) << 5);
|
||||||
aux |= m_instr.range(11, 7);
|
aux |= static_cast<int32_t>(m_instr.range(11, 7));
|
||||||
|
|
||||||
if (m_instr[31] == 1) {
|
if (m_instr[31] == 1) {
|
||||||
aux |= (0b11111111111111111111) << 12;
|
aux |= (0b11111111111111111111) << 12;
|
||||||
|
@ -203,7 +203,7 @@ public:
|
||||||
* @return immediate_U field
|
* @return immediate_U field
|
||||||
*/
|
*/
|
||||||
inline int32_t get_imm_U() const {
|
inline int32_t get_imm_U() const {
|
||||||
return m_instr.range(31, 12);
|
return static_cast<int32_t>(m_instr.range(31, 12));
|
||||||
}
|
}
|
||||||
|
|
||||||
inline void set_imm_U(int32_t value) {
|
inline void set_imm_U(int32_t value) {
|
||||||
|
@ -217,10 +217,10 @@ public:
|
||||||
inline int32_t get_imm_B() const {
|
inline int32_t get_imm_B() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux |= m_instr[7] << 11;
|
aux |= static_cast<int32_t>(m_instr[7] << 11);
|
||||||
aux |= m_instr.range(30, 25) << 5;
|
aux |= static_cast<int32_t>(m_instr.range(30, 25) << 5);
|
||||||
aux |= m_instr[31] << 12;
|
aux |= static_cast<int32_t>(m_instr[31] << 12);
|
||||||
aux |= m_instr.range(11, 8) << 1;
|
aux |= static_cast<int32_t>(m_instr.range(11, 8) << 1);
|
||||||
|
|
||||||
if (m_instr[31] == 1) {
|
if (m_instr[31] == 1) {
|
||||||
aux |= (0b11111111111111111111) << 12;
|
aux |= (0b11111111111111111111) << 12;
|
||||||
|
@ -244,15 +244,15 @@ public:
|
||||||
inline int32_t get_imm_J() const {
|
inline int32_t get_imm_J() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 11;
|
aux = static_cast<int32_t>(m_instr[12] << 11);
|
||||||
aux |= m_instr[11] << 4;
|
aux |= static_cast<int32_t>(m_instr[11] << 4);
|
||||||
aux |= m_instr[10] << 9;
|
aux |= static_cast<int32_t>(m_instr[10] << 9);
|
||||||
aux |= m_instr[9] << 8;
|
aux |= static_cast<int32_t>(m_instr[9] << 8);
|
||||||
aux |= m_instr[8] << 10;
|
aux |= static_cast<int32_t>(m_instr[8] << 10);
|
||||||
aux |= m_instr[7] << 6;
|
aux |= static_cast<int32_t>(m_instr[7] << 6);
|
||||||
aux |= m_instr[6] << 7;
|
aux |= static_cast<int32_t>(m_instr[6] << 7);
|
||||||
aux |= m_instr.range(5, 3) << 1;
|
aux |= static_cast<int32_t>(m_instr.range(5, 3) << 1);
|
||||||
aux |= m_instr[2] << 5;
|
aux |= static_cast<int32_t>(m_instr[2] << 5);
|
||||||
|
|
||||||
if (m_instr[12] == 1) {
|
if (m_instr[12] == 1) {
|
||||||
aux |= 0b11111111111111111111 << 12;
|
aux |= 0b11111111111111111111 << 12;
|
||||||
|
@ -273,9 +273,9 @@ public:
|
||||||
inline int32_t get_imm_L() const {
|
inline int32_t get_imm_L() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr.range(12, 10) << 3;
|
aux = static_cast<int32_t>(m_instr.range(12, 10) << 3);
|
||||||
aux |= m_instr[6] << 2;
|
aux |= static_cast<int32_t>(m_instr[6] << 2);
|
||||||
aux |= m_instr[5] << 6;
|
aux |= static_cast<int32_t>(m_instr[5] << 6);
|
||||||
|
|
||||||
return aux;
|
return aux;
|
||||||
}
|
}
|
||||||
|
@ -283,9 +283,9 @@ public:
|
||||||
inline int32_t get_imm_LWSP() const {
|
inline int32_t get_imm_LWSP() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 5;
|
aux = static_cast<int32_t>(m_instr[12] << 5);
|
||||||
aux |= m_instr.range(6, 4) << 2;
|
aux |= static_cast<int32_t>(m_instr.range(6, 4) << 2);
|
||||||
aux |= m_instr.range(3, 2) << 6;
|
aux |= static_cast<int32_t>(m_instr.range(3, 2) << 6);
|
||||||
|
|
||||||
return aux;
|
return aux;
|
||||||
}
|
}
|
||||||
|
@ -293,8 +293,8 @@ public:
|
||||||
inline int32_t get_imm_ADDI () const {
|
inline int32_t get_imm_ADDI () const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 5;
|
aux = static_cast<int32_t>(m_instr[12] << 5);
|
||||||
aux |= m_instr.range(6, 2);
|
aux |= static_cast<int32_t>(m_instr.range(6, 2));
|
||||||
|
|
||||||
if (m_instr[12] == 1) {
|
if (m_instr[12] == 1) {
|
||||||
aux |= 0b11111111111111111111111111 << 6;
|
aux |= 0b11111111111111111111111111 << 6;
|
||||||
|
@ -305,10 +305,10 @@ public:
|
||||||
inline int32_t get_imm_ADDI4SPN() const {
|
inline int32_t get_imm_ADDI4SPN() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr.range(12, 11) << 4;
|
aux = static_cast<int32_t>(m_instr.range(12, 11) << 4);
|
||||||
aux |= m_instr.range(10, 7) << 6;
|
aux |= static_cast<int32_t>(m_instr.range(10, 7) << 6);
|
||||||
aux |= m_instr[6] << 2;
|
aux |= static_cast<int32_t>(m_instr[6] << 2);
|
||||||
aux |= m_instr[5] << 3;
|
aux |= static_cast<int32_t>(m_instr[5] << 3);
|
||||||
|
|
||||||
return aux;
|
return aux;
|
||||||
}
|
}
|
||||||
|
@ -316,12 +316,12 @@ public:
|
||||||
inline int32_t get_imm_ADDI16SP() const {
|
inline int32_t get_imm_ADDI16SP() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 9;
|
aux = static_cast<int32_t>(m_instr[12] << 9);
|
||||||
aux |= m_instr[6] << 4;
|
aux |= static_cast<int32_t>(m_instr[6] << 4);
|
||||||
aux |= m_instr[5] << 6;
|
aux |= static_cast<int32_t>(m_instr[5] << 6);
|
||||||
aux |= m_instr[4] << 8;
|
aux |= static_cast<int32_t>(m_instr[4] << 8);
|
||||||
aux |= m_instr[3] << 7;
|
aux |= static_cast<int32_t>(m_instr[3] << 7);
|
||||||
aux |= m_instr[2] << 5;
|
aux |= static_cast<int32_t>(m_instr[2] << 5);
|
||||||
|
|
||||||
if (m_instr[12] == 1) {
|
if (m_instr[12] == 1) {
|
||||||
aux |= 0b1111111111111111111111 << 10;
|
aux |= 0b1111111111111111111111 << 10;
|
||||||
|
@ -331,8 +331,8 @@ public:
|
||||||
|
|
||||||
inline int32_t get_imm_CSS() const {
|
inline int32_t get_imm_CSS() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
aux = m_instr.range(12, 9) << 2;
|
aux = static_cast<int32_t>(m_instr.range(12, 9) << 2);
|
||||||
aux |= m_instr.range(8, 7) << 6;
|
aux |= static_cast<int32_t>(m_instr.range(8, 7) << 6);
|
||||||
|
|
||||||
return aux;
|
return aux;
|
||||||
}
|
}
|
||||||
|
@ -340,14 +340,14 @@ public:
|
||||||
inline int32_t get_imm_CB() const {
|
inline int32_t get_imm_CB() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 8;
|
aux = static_cast<int32_t>(m_instr[12] << 8);
|
||||||
aux |= m_instr[11] << 4;
|
aux |= static_cast<int32_t>(m_instr[11] << 4);
|
||||||
aux |= m_instr[10] << 3;
|
aux |= static_cast<int32_t>(m_instr[10] << 3);
|
||||||
aux |= m_instr[6] << 7;
|
aux |= static_cast<int32_t>(m_instr[6] << 7);
|
||||||
aux |= m_instr[5] << 6;
|
aux |= static_cast<int32_t>(m_instr[5] << 6);
|
||||||
aux |= m_instr[4] << 2;
|
aux |= static_cast<int32_t>(m_instr[4] << 2);
|
||||||
aux |= m_instr[3] << 1;
|
aux |= static_cast<int32_t>(m_instr[3] << 1);
|
||||||
aux |= m_instr[2] << 5;
|
aux |= static_cast<int32_t>(m_instr[2] << 5);
|
||||||
|
|
||||||
if (m_instr[12] == 1) {
|
if (m_instr[12] == 1) {
|
||||||
aux |= 0b11111111111111111111111 << 9;
|
aux |= 0b11111111111111111111111 << 9;
|
||||||
|
@ -359,8 +359,8 @@ public:
|
||||||
inline int32_t get_imm_LUI() const {
|
inline int32_t get_imm_LUI() const {
|
||||||
int32_t aux = 0;
|
int32_t aux = 0;
|
||||||
|
|
||||||
aux = m_instr[12] << 17;
|
aux = static_cast<int32_t>(m_instr[12] << 17);
|
||||||
aux |= m_instr.range(6, 2) << 12;
|
aux |= static_cast<int32_t>(m_instr.range(6, 2) << 12);
|
||||||
|
|
||||||
if (m_instr[12] == 1) {
|
if (m_instr[12] == 1) {
|
||||||
aux |= 0b111111111111111 << 17;
|
aux |= 0b111111111111111 << 17;
|
||||||
|
|
|
@ -28,7 +28,7 @@ public:
|
||||||
|
|
||||||
private:
|
private:
|
||||||
static std::string compute_checksum_string(const std::string &msg);
|
static std::string compute_checksum_string(const std::string &msg);
|
||||||
void send_packet(int conn, const std::string &msg);
|
void send_packet(int m_conn, const std::string &msg);
|
||||||
std::string receive_packet();
|
std::string receive_packet();
|
||||||
void handle_gdb_loop();
|
void handle_gdb_loop();
|
||||||
|
|
||||||
|
@ -38,7 +38,7 @@ private:
|
||||||
CPU *dbg_cpu;
|
CPU *dbg_cpu;
|
||||||
Memory *dbg_mem;
|
Memory *dbg_mem;
|
||||||
tlm::tlm_generic_payload dbg_trans;
|
tlm::tlm_generic_payload dbg_trans;
|
||||||
unsigned char pyld_array[128];
|
unsigned char pyld_array[128]{};
|
||||||
std::unordered_set<uint32_t> breakpoints;
|
std::unordered_set<uint32_t> breakpoints;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -78,7 +78,7 @@ private:
|
||||||
* @return return opcode field
|
* @return return opcode field
|
||||||
*/
|
*/
|
||||||
inline int32_t opcode() const override {
|
inline int32_t opcode() const override {
|
||||||
return m_instr.range(14, 12);
|
return static_cast<int32_t>(m_instr.range(14, 12));
|
||||||
}
|
}
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
|
@ -215,7 +215,7 @@ public:
|
||||||
* Increments PC couunter to next address
|
* Increments PC couunter to next address
|
||||||
*/
|
*/
|
||||||
inline void incPC(bool C_ext = false) {
|
inline void incPC(bool C_ext = false) {
|
||||||
if (C_ext == true) {
|
if (C_ext) {
|
||||||
register_PC += 2;
|
register_PC += 2;
|
||||||
} else {
|
} else {
|
||||||
register_PC += 4;
|
register_PC += 4;
|
||||||
|
|
|
@ -50,7 +50,7 @@ private:
|
||||||
sc_core::sc_time &delay);
|
sc_core::sc_time &delay);
|
||||||
|
|
||||||
void xtermLaunch(char *slaveName) const;
|
void xtermLaunch(char *slaveName) const;
|
||||||
void xtermKill(const char *mess);
|
void xtermKill();
|
||||||
void xtermSetup();
|
void xtermSetup();
|
||||||
|
|
||||||
int ptSlave{};
|
int ptSlave{};
|
||||||
|
|
|
@ -26,7 +26,7 @@
|
||||||
class extension_base {
|
class extension_base {
|
||||||
|
|
||||||
public:
|
public:
|
||||||
extension_base(sc_dt::sc_uint<32> instr, Registers *register_bank,
|
extension_base(const sc_dt::sc_uint<32> & instr, Registers *register_bank,
|
||||||
MemoryInterface *mem_interface);
|
MemoryInterface *mem_interface);
|
||||||
virtual ~extension_base() = 0;
|
virtual ~extension_base() = 0;
|
||||||
|
|
||||||
|
|
|
@ -72,7 +72,7 @@ bool A_extension::Exec_A_LR() {
|
||||||
mem_addr = regs->getValue(rs1);
|
mem_addr = regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
TLB_reserve(mem_addr);
|
TLB_reserve(mem_addr);
|
||||||
|
|
||||||
|
@ -124,11 +124,11 @@ bool A_extension::Exec_A_AMOSWAP() const {
|
||||||
mem_addr = regs->getValue(rs1);
|
mem_addr = regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// swap
|
// swap
|
||||||
aux = regs->getValue(rs2);
|
aux = regs->getValue(rs2);
|
||||||
regs->setValue(rs2, data);
|
regs->setValue(rs2, static_cast<int32_t>(data));
|
||||||
|
|
||||||
mem_intf->writeDataMem(mem_addr, aux, 4);
|
mem_intf->writeDataMem(mem_addr, aux, 4);
|
||||||
perf->dataMemoryWrite();
|
perf->dataMemoryWrite();
|
||||||
|
@ -152,7 +152,7 @@ bool A_extension::Exec_A_AMOADD() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// add
|
// add
|
||||||
data = data + regs->getValue(rs2);
|
data = data + regs->getValue(rs2);
|
||||||
|
@ -180,7 +180,7 @@ bool A_extension::Exec_A_AMOXOR() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// add
|
// add
|
||||||
data = data ^ regs->getValue(rs2);
|
data = data ^ regs->getValue(rs2);
|
||||||
|
@ -207,7 +207,7 @@ bool A_extension::Exec_A_AMOAND() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// add
|
// add
|
||||||
data = data & regs->getValue(rs2);
|
data = data & regs->getValue(rs2);
|
||||||
|
@ -235,7 +235,7 @@ bool A_extension::Exec_A_AMOOR() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// add
|
// add
|
||||||
data = data | regs->getValue(rs2);
|
data = data | regs->getValue(rs2);
|
||||||
|
@ -263,7 +263,7 @@ bool A_extension::Exec_A_AMOMIN() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// min
|
// min
|
||||||
aux = regs->getValue(rs2);
|
aux = regs->getValue(rs2);
|
||||||
|
@ -294,7 +294,7 @@ bool A_extension::Exec_A_AMOMAX() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// >
|
// >
|
||||||
aux = regs->getValue(rs2);
|
aux = regs->getValue(rs2);
|
||||||
|
@ -325,7 +325,7 @@ bool A_extension::Exec_A_AMOMINU() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// min
|
// min
|
||||||
aux = regs->getValue(rs2);
|
aux = regs->getValue(rs2);
|
||||||
|
@ -356,7 +356,7 @@ bool A_extension::Exec_A_AMOMAXU() const {
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
|
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
// max
|
// max
|
||||||
aux = regs->getValue(rs2);
|
aux = regs->getValue(rs2);
|
||||||
|
|
|
@ -88,7 +88,7 @@ bool BASE_ISA::Exec_LUI() const {
|
||||||
|
|
||||||
rd = get_rd();
|
rd = get_rd();
|
||||||
imm = get_imm_U() << 12;
|
imm = get_imm_U() << 12;
|
||||||
regs->setValue(rd, imm);
|
regs->setValue(rd, static_cast<int32_t>(imm));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex
|
log->SC_log(Log::INFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex
|
||||||
|
@ -105,7 +105,7 @@ bool BASE_ISA::Exec_AUIPC() const {
|
||||||
|
|
||||||
rd = get_rd();
|
rd = get_rd();
|
||||||
imm = get_imm_U() << 12;
|
imm = get_imm_U() << 12;
|
||||||
new_pc = regs->getPC() + imm;
|
new_pc = static_cast<int32_t>(regs->getPC() + imm);
|
||||||
|
|
||||||
regs->setValue(rd, new_pc);
|
regs->setValue(rd, new_pc);
|
||||||
|
|
||||||
|
@ -124,7 +124,7 @@ bool BASE_ISA::Exec_JAL() const {
|
||||||
|
|
||||||
rd = get_rd();
|
rd = get_rd();
|
||||||
mem_addr = get_imm_J();
|
mem_addr = get_imm_J();
|
||||||
old_pc = regs->getPC();
|
old_pc = static_cast<int32_t>(regs->getPC());
|
||||||
new_pc = old_pc + mem_addr;
|
new_pc = old_pc + mem_addr;
|
||||||
|
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
|
@ -150,10 +150,10 @@ bool BASE_ISA::Exec_JALR() const {
|
||||||
rs1 = get_rs1();
|
rs1 = get_rs1();
|
||||||
mem_addr = get_imm_I();
|
mem_addr = get_imm_I();
|
||||||
|
|
||||||
old_pc = regs->getPC();
|
old_pc = static_cast<int32_t>(regs->getPC());
|
||||||
regs->setValue(rd, old_pc + 4);
|
regs->setValue(rd, old_pc + 4);
|
||||||
|
|
||||||
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
|
new_pc = static_cast<int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE);
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -171,11 +171,11 @@ bool BASE_ISA::Exec_BEQ() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
if (regs->getValue(rs1) == regs->getValue(rs2)) {
|
if (regs->getValue(rs1) == regs->getValue(rs2)) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
new_pc = regs->getPC();
|
new_pc = static_cast<int32_t>(regs->getPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -200,11 +200,11 @@ bool BASE_ISA::Exec_BNE() const {
|
||||||
val2 = regs->getValue(rs2);
|
val2 = regs->getValue(rs2);
|
||||||
|
|
||||||
if (val1 != val2) {
|
if (val1 != val2) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
new_pc = regs->getPC();
|
new_pc = static_cast<int32_t>(regs->getPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -225,7 +225,7 @@ bool BASE_ISA::Exec_BLT() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
if ((int32_t) regs->getValue(rs1) < (int32_t) regs->getValue(rs2)) {
|
if ((int32_t) regs->getValue(rs1) < (int32_t) regs->getValue(rs2)) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
|
@ -250,7 +250,7 @@ bool BASE_ISA::Exec_BGE() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
if ((int32_t) regs->getValue(rs1) >= (int32_t) regs->getValue(rs2)) {
|
if ((int32_t) regs->getValue(rs1) >= (int32_t) regs->getValue(rs2)) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
|
@ -275,11 +275,11 @@ bool BASE_ISA::Exec_BLTU() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
if ((uint32_t) regs->getValue(rs1) < (uint32_t) regs->getValue(rs2)) {
|
if ((uint32_t) regs->getValue(rs1) < (uint32_t) regs->getValue(rs2)) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
new_pc = regs->getPC();
|
new_pc = static_cast<int32_t>(regs->getPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -300,7 +300,7 @@ bool BASE_ISA::Exec_BGEU() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
if ((uint32_t) regs->getValue(rs1) >= (uint32_t) regs->getValue(rs2)) {
|
if ((uint32_t) regs->getValue(rs1) >= (uint32_t) regs->getValue(rs2)) {
|
||||||
new_pc = regs->getPC() + get_imm_B();
|
new_pc = static_cast<int32_t>(regs->getPC() + get_imm_B());
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC();
|
regs->incPC();
|
||||||
|
@ -327,7 +327,7 @@ bool BASE_ISA::Exec_LB() const {
|
||||||
imm = get_imm_I();
|
imm = get_imm_I();
|
||||||
|
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 1);
|
data = static_cast<int8_t>(mem_intf->readDataMem(mem_addr, 1));
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, data);
|
||||||
|
|
||||||
|
@ -350,7 +350,7 @@ bool BASE_ISA::Exec_LH() const {
|
||||||
imm = get_imm_I();
|
imm = get_imm_I();
|
||||||
|
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 2);
|
data = static_cast<int16_t>(mem_intf->readDataMem(mem_addr, 2));
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, data);
|
||||||
|
|
||||||
|
@ -375,7 +375,7 @@ bool BASE_ISA::Exec_LW() const {
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
|
log->SC_log(Log::INFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
|
||||||
|
@ -399,7 +399,7 @@ bool BASE_ISA::Exec_LBU() const {
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 1);
|
data = mem_intf->readDataMem(mem_addr, 1);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
|
log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
|
||||||
|
@ -580,7 +580,7 @@ bool BASE_ISA::Exec_XORI() const {
|
||||||
imm = get_imm_I();
|
imm = get_imm_I();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) ^ imm;
|
calc = regs->getValue(rs1) ^ imm;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
|
log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
|
||||||
|
@ -600,7 +600,7 @@ bool BASE_ISA::Exec_ORI() const {
|
||||||
imm = get_imm_I();
|
imm = get_imm_I();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) | imm;
|
calc = regs->getValue(rs1) | imm;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
|
log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
|
||||||
|
@ -622,7 +622,7 @@ bool BASE_ISA::Exec_ANDI() const {
|
||||||
|
|
||||||
aux = regs->getValue(rs1);
|
aux = regs->getValue(rs1);
|
||||||
calc = aux & imm;
|
calc = aux & imm;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
|
log->SC_log(Log::INFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
|
||||||
|
@ -652,7 +652,7 @@ bool BASE_ISA::Exec_SLLI() {
|
||||||
shift = rs2 & 0x1F;
|
shift = rs2 & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
|
log->SC_log(Log::INFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
|
||||||
|
@ -674,7 +674,7 @@ bool BASE_ISA::Exec_SRLI() const {
|
||||||
shift = rs2 & 0x1F;
|
shift = rs2 & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
|
log->SC_log(Log::INFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
|
||||||
|
@ -715,7 +715,7 @@ bool BASE_ISA::Exec_ADD() const {
|
||||||
|
|
||||||
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
||||||
|
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
|
log->SC_log(Log::INFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
|
||||||
|
@ -733,7 +733,7 @@ bool BASE_ISA::Exec_SUB() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) - regs->getValue(rs2);
|
calc = regs->getValue(rs1) - regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
|
log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
|
||||||
|
@ -755,7 +755,7 @@ bool BASE_ISA::Exec_SLL() const {
|
||||||
shift = regs->getValue(rs2) & 0x1F;
|
shift = regs->getValue(rs2) & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
|
log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
|
||||||
|
@ -814,7 +814,7 @@ bool BASE_ISA::Exec_XOR() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
|
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
|
log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
|
||||||
|
@ -836,7 +836,7 @@ bool BASE_ISA::Exec_SRL() const {
|
||||||
shift = regs->getValue(rs2) & 0x1F;
|
shift = regs->getValue(rs2) & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
|
log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
|
||||||
|
@ -877,7 +877,7 @@ bool BASE_ISA::Exec_OR() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) | regs->getValue(rs2);
|
calc = regs->getValue(rs1) | regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
|
log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
|
||||||
|
@ -896,7 +896,7 @@ bool BASE_ISA::Exec_AND() const {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) & regs->getValue(rs2);
|
calc = regs->getValue(rs1) & regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
|
log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
|
||||||
|
@ -959,7 +959,7 @@ bool BASE_ISA::Exec_CSRRW() const {
|
||||||
/* These operations must be atomical */
|
/* These operations must be atomical */
|
||||||
if (rd != 0) {
|
if (rd != 0) {
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
}
|
}
|
||||||
|
|
||||||
aux = regs->getValue(rs1);
|
aux = regs->getValue(rs1);
|
||||||
|
@ -991,7 +991,7 @@ bool BASE_ISA::Exec_CSRRS() const {
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
bitmask = regs->getValue(rs1);
|
bitmask = regs->getValue(rs1);
|
||||||
|
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
|
|
||||||
aux2 = aux | bitmask;
|
aux2 = aux | bitmask;
|
||||||
regs->setCSR(csr, aux2);
|
regs->setCSR(csr, aux2);
|
||||||
|
@ -1022,7 +1022,7 @@ bool BASE_ISA::Exec_CSRRC() const {
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
bitmask = regs->getValue(rs1);
|
bitmask = regs->getValue(rs1);
|
||||||
|
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
|
|
||||||
aux2 = aux & ~bitmask;
|
aux2 = aux & ~bitmask;
|
||||||
regs->setCSR(csr, aux2);
|
regs->setCSR(csr, aux2);
|
||||||
|
@ -1046,7 +1046,7 @@ bool BASE_ISA::Exec_CSRRWI() const {
|
||||||
/* These operations must be atomical */
|
/* These operations must be atomical */
|
||||||
if (rd != 0) {
|
if (rd != 0) {
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
}
|
}
|
||||||
aux = rs1;
|
aux = rs1;
|
||||||
regs->setCSR(csr, aux);
|
regs->setCSR(csr, aux);
|
||||||
|
@ -1072,7 +1072,7 @@ bool BASE_ISA::Exec_CSRRSI() const {
|
||||||
|
|
||||||
/* These operations must be atomical */
|
/* These operations must be atomical */
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
|
|
||||||
bitmask = rs1;
|
bitmask = rs1;
|
||||||
aux = aux | bitmask;
|
aux = aux | bitmask;
|
||||||
|
@ -1100,7 +1100,7 @@ bool BASE_ISA::Exec_CSRRCI() const {
|
||||||
|
|
||||||
/* These operations must be atomical */
|
/* These operations must be atomical */
|
||||||
aux = regs->getCSR(csr);
|
aux = regs->getCSR(csr);
|
||||||
regs->setValue(rd, aux);
|
regs->setValue(rd, static_cast<int32_t>(aux));
|
||||||
|
|
||||||
bitmask = rs1;
|
bitmask = rs1;
|
||||||
aux = aux & ~bitmask;
|
aux = aux & ~bitmask;
|
||||||
|
|
12
src/CPU.cpp
12
src/CPU.cpp
|
@ -43,7 +43,7 @@ CPU::CPU(sc_core::sc_module_name const name, uint32_t PC, bool debug) :
|
||||||
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&INSTR));
|
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&INSTR));
|
||||||
trans.set_data_length(4);
|
trans.set_data_length(4);
|
||||||
trans.set_streaming_width(4); // = data_length to indicate no streaming
|
trans.set_streaming_width(4); // = data_length to indicate no streaming
|
||||||
trans.set_byte_enable_ptr(0); // 0 indicates unused
|
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
|
||||||
trans.set_dmi_allowed(false); // Mandatory initial value
|
trans.set_dmi_allowed(false); // Mandatory initial value
|
||||||
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
|
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
|
||||||
|
|
||||||
|
@ -67,7 +67,7 @@ bool CPU::cpu_process_IRQ() {
|
||||||
uint32_t csr_temp;
|
uint32_t csr_temp;
|
||||||
bool ret_value = false;
|
bool ret_value = false;
|
||||||
|
|
||||||
if (interrupt == true) {
|
if (interrupt) {
|
||||||
csr_temp = register_bank->getCSR(CSR_MSTATUS);
|
csr_temp = register_bank->getCSR(CSR_MSTATUS);
|
||||||
if ((csr_temp & MSTATUS_MIE) == 0) {
|
if ((csr_temp & MSTATUS_MIE) == 0) {
|
||||||
log->SC_log(Log::DEBUG) << "interrupt delayed" << std::endl;
|
log->SC_log(Log::DEBUG) << "interrupt delayed" << std::endl;
|
||||||
|
@ -102,7 +102,7 @@ bool CPU::cpu_process_IRQ() {
|
||||||
irq_already_down = false;
|
irq_already_down = false;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (irq_already_down == false) {
|
if (!irq_already_down) {
|
||||||
csr_temp = register_bank->getCSR(CSR_MIP);
|
csr_temp = register_bank->getCSR(CSR_MIP);
|
||||||
csr_temp &= ~MIP_MEIP;
|
csr_temp &= ~MIP_MEIP;
|
||||||
register_bank->setCSR(CSR_MIP, csr_temp);
|
register_bank->setCSR(CSR_MIP, csr_temp);
|
||||||
|
@ -119,7 +119,7 @@ bool CPU::CPU_step() {
|
||||||
bool PC_not_affected = false;
|
bool PC_not_affected = false;
|
||||||
|
|
||||||
/* Get new PC value */
|
/* Get new PC value */
|
||||||
if (dmi_ptr_valid == true) {
|
if (dmi_ptr_valid) {
|
||||||
/* if memory_offset at Memory module is set, this won't work */
|
/* if memory_offset at Memory module is set, this won't work */
|
||||||
memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
|
memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
|
||||||
} else {
|
} else {
|
||||||
|
@ -173,13 +173,13 @@ bool CPU::CPU_step() {
|
||||||
exec->NOP();
|
exec->NOP();
|
||||||
}
|
}
|
||||||
|
|
||||||
if (breakpoint == true) {
|
if (breakpoint) {
|
||||||
std::cout << "Breakpoint set to true\n";
|
std::cout << "Breakpoint set to true\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
perf->instructionsInc();
|
perf->instructionsInc();
|
||||||
|
|
||||||
if (PC_not_affected == true) {
|
if (PC_not_affected) {
|
||||||
register_bank->incPC(incPCby2);
|
register_bank->incPC(incPCby2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -147,14 +147,14 @@ op_C_Codes C_extension::decode() const {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool C_extension::Exec_C_JR() {
|
bool C_extension::Exec_C_JR() {
|
||||||
uint32_t mem_addr = 0;
|
uint32_t mem_addr;
|
||||||
int rs1;
|
int rs1;
|
||||||
int new_pc;
|
int new_pc;
|
||||||
|
|
||||||
rs1 = get_rs1();
|
rs1 = get_rs1();
|
||||||
mem_addr = 0;
|
mem_addr = 0;
|
||||||
|
|
||||||
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
|
new_pc = static_cast<int32_t>(static_cast<int32_t>((regs->getValue(rs1)) + static_cast<int32_t>(mem_addr)) & 0xFFFFFFFE);
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -173,7 +173,7 @@ bool C_extension::Exec_C_MV() {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
|
log->SC_log(Log::INFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
|
||||||
|
@ -194,7 +194,7 @@ bool C_extension::Exec_C_ADD() {
|
||||||
rs2 = get_rs2();
|
rs2 = get_rs2();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
|
log->SC_log(Log::INFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
|
||||||
|
@ -205,9 +205,9 @@ bool C_extension::Exec_C_ADD() {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool C_extension::Exec_C_LWSP() {
|
bool C_extension::Exec_C_LWSP() {
|
||||||
uint32_t mem_addr = 0;
|
uint32_t mem_addr;
|
||||||
int rd, rs1;
|
int rd, rs1;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
uint32_t data;
|
uint32_t data;
|
||||||
|
|
||||||
// lw rd, offset[7:2](x2)
|
// lw rd, offset[7:2](x2)
|
||||||
|
@ -219,7 +219,7 @@ bool C_extension::Exec_C_LWSP() {
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
|
log->SC_log(Log::INFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
|
||||||
|
@ -232,7 +232,7 @@ bool C_extension::Exec_C_LWSP() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_ADDI4SPN() {
|
bool C_extension::Exec_C_ADDI4SPN() {
|
||||||
int rd, rs1;
|
int rd, rs1;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
int32_t calc;
|
int32_t calc;
|
||||||
|
|
||||||
rd = get_rdp();
|
rd = get_rdp();
|
||||||
|
@ -259,7 +259,7 @@ bool C_extension::Exec_C_ADDI4SPN() {
|
||||||
bool C_extension::Exec_C_ADDI16SP() {
|
bool C_extension::Exec_C_ADDI16SP() {
|
||||||
// addi x2, x2, nzimm[9:4]
|
// addi x2, x2, nzimm[9:4]
|
||||||
int rd;
|
int rd;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
|
|
||||||
if (get_rd() == 2) {
|
if (get_rd() == 2) {
|
||||||
int rs1;
|
int rs1;
|
||||||
|
@ -289,9 +289,9 @@ bool C_extension::Exec_C_ADDI16SP() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_SWSP() {
|
bool C_extension::Exec_C_SWSP() {
|
||||||
// sw rs2, offset(x2)
|
// sw rs2, offset(x2)
|
||||||
uint32_t mem_addr = 0;
|
uint32_t mem_addr;
|
||||||
int rs1, rs2;
|
int rs1, rs2;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
uint32_t data;
|
uint32_t data;
|
||||||
|
|
||||||
rs1 = 2;
|
rs1 = 2;
|
||||||
|
@ -315,18 +315,18 @@ bool C_extension::Exec_C_SWSP() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_BEQZ() {
|
bool C_extension::Exec_C_BEQZ() {
|
||||||
int rs1;
|
int rs1;
|
||||||
int new_pc = 0;
|
int new_pc;
|
||||||
uint32_t val1;
|
uint32_t val1;
|
||||||
|
|
||||||
rs1 = get_rs1p();
|
rs1 = get_rs1p();
|
||||||
val1 = regs->getValue(rs1);
|
val1 = regs->getValue(rs1);
|
||||||
|
|
||||||
if (val1 == 0) {
|
if (val1 == 0) {
|
||||||
new_pc = regs->getPC() + get_imm_CB();
|
new_pc = static_cast<int32_t>(regs->getPC()) + get_imm_CB();
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC(true); //PC <- PC + 2
|
regs->incPC(true); //PC <- PC + 2
|
||||||
new_pc = regs->getPC();
|
new_pc = static_cast<int32_t>(regs->getPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -340,18 +340,18 @@ bool C_extension::Exec_C_BEQZ() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_BNEZ() {
|
bool C_extension::Exec_C_BNEZ() {
|
||||||
int rs1;
|
int rs1;
|
||||||
int new_pc = 0;
|
int new_pc;
|
||||||
uint32_t val1;
|
uint32_t val1;
|
||||||
|
|
||||||
rs1 = get_rs1p();
|
rs1 = get_rs1p();
|
||||||
val1 = regs->getValue(rs1);
|
val1 = regs->getValue(rs1);
|
||||||
|
|
||||||
if (val1 != 0) {
|
if (val1 != 0) {
|
||||||
new_pc = regs->getPC() + get_imm_CB();
|
new_pc = static_cast<int32_t>(regs->getPC()) + get_imm_CB();
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
} else {
|
} else {
|
||||||
regs->incPC(true); //PC <- PC +2
|
regs->incPC(true); //PC <- PC +2
|
||||||
new_pc = regs->getPC();
|
new_pc = static_cast<int32_t>(regs->getPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -365,7 +365,7 @@ bool C_extension::Exec_C_BNEZ() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_LI() {
|
bool C_extension::Exec_C_LI() {
|
||||||
int rd, rs1;
|
int rd, rs1;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
int32_t calc;
|
int32_t calc;
|
||||||
|
|
||||||
rd = get_rd();
|
rd = get_rd();
|
||||||
|
@ -396,7 +396,7 @@ bool C_extension::Exec_C_SRLI() {
|
||||||
shift = rs2 & 0x1F;
|
shift = rs2 & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
|
log->SC_log(Log::INFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
|
||||||
|
@ -440,7 +440,7 @@ bool C_extension::Exec_C_SLLI() {
|
||||||
shift = rs2 & 0x1F;
|
shift = rs2 & 0x1F;
|
||||||
|
|
||||||
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
calc = ((uint32_t) regs->getValue(rs1)) << shift;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
|
log->SC_log(Log::INFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
|
||||||
|
@ -462,7 +462,7 @@ bool C_extension::Exec_C_ANDI() {
|
||||||
|
|
||||||
aux = regs->getValue(rs1);
|
aux = regs->getValue(rs1);
|
||||||
calc = aux & imm;
|
calc = aux & imm;
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
|
log->SC_log(Log::INFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
|
||||||
|
@ -481,7 +481,7 @@ bool C_extension::Exec_C_SUB() {
|
||||||
rs2 = get_rs2p();
|
rs2 = get_rs2p();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) - regs->getValue(rs2);
|
calc = regs->getValue(rs1) - regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
|
log->SC_log(Log::INFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
|
||||||
|
@ -500,7 +500,7 @@ bool C_extension::Exec_C_XOR() {
|
||||||
rs2 = get_rs2p();
|
rs2 = get_rs2p();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
|
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
|
log->SC_log(Log::INFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
|
||||||
|
@ -519,7 +519,7 @@ bool C_extension::Exec_C_OR() {
|
||||||
rs2 = get_rs2p();
|
rs2 = get_rs2p();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) | regs->getValue(rs2);
|
calc = regs->getValue(rs1) | regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
|
log->SC_log(Log::INFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
|
||||||
|
@ -538,7 +538,7 @@ bool C_extension::Exec_C_AND() {
|
||||||
rs2 = get_rs2p();
|
rs2 = get_rs2p();
|
||||||
|
|
||||||
calc = regs->getValue(rs1) & regs->getValue(rs2);
|
calc = regs->getValue(rs1) & regs->getValue(rs2);
|
||||||
regs->setValue(rd, calc);
|
regs->setValue(rd, static_cast<int32_t>(calc));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
|
log->SC_log(Log::INFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
|
||||||
|
@ -550,7 +550,7 @@ bool C_extension::Exec_C_AND() {
|
||||||
|
|
||||||
bool C_extension::Exec_C_ADDI() const {
|
bool C_extension::Exec_C_ADDI() const {
|
||||||
int rd, rs1;
|
int rd, rs1;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
int32_t calc;
|
int32_t calc;
|
||||||
|
|
||||||
rd = get_rd();
|
rd = get_rd();
|
||||||
|
@ -577,10 +577,10 @@ bool C_extension::Exec_C_JALR() {
|
||||||
rd = 1;
|
rd = 1;
|
||||||
rs1 = get_rs1();
|
rs1 = get_rs1();
|
||||||
|
|
||||||
old_pc = regs->getPC();
|
old_pc = static_cast<int32_t>(regs->getPC());
|
||||||
regs->setValue(rd, old_pc + 2);
|
regs->setValue(rd, old_pc + 2);
|
||||||
|
|
||||||
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
|
new_pc = static_cast<int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE);
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
|
@ -593,9 +593,9 @@ bool C_extension::Exec_C_JALR() {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool C_extension::Exec_C_LW() {
|
bool C_extension::Exec_C_LW() {
|
||||||
uint32_t mem_addr = 0;
|
uint32_t mem_addr;
|
||||||
int rd, rs1;
|
int rd, rs1;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
uint32_t data;
|
uint32_t data;
|
||||||
|
|
||||||
rd = get_rdp();
|
rd = get_rdp();
|
||||||
|
@ -605,7 +605,7 @@ bool C_extension::Exec_C_LW() {
|
||||||
mem_addr = imm + regs->getValue(rs1);
|
mem_addr = imm + regs->getValue(rs1);
|
||||||
data = mem_intf->readDataMem(mem_addr, 4);
|
data = mem_intf->readDataMem(mem_addr, 4);
|
||||||
perf->dataMemoryRead();
|
perf->dataMemoryRead();
|
||||||
regs->setValue(rd, data);
|
regs->setValue(rd, static_cast<int32_t>(data));
|
||||||
|
|
||||||
if (log->getLogLevel() >= Log::INFO) {
|
if (log->getLogLevel() >= Log::INFO) {
|
||||||
log->SC_log(Log::INFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
|
log->SC_log(Log::INFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
|
||||||
|
@ -618,9 +618,9 @@ bool C_extension::Exec_C_LW() {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool C_extension::Exec_C_SW() {
|
bool C_extension::Exec_C_SW() {
|
||||||
uint32_t mem_addr = 0;
|
uint32_t mem_addr;
|
||||||
int rs1, rs2;
|
int rs1, rs2;
|
||||||
int32_t imm = 0;
|
int32_t imm;
|
||||||
uint32_t data;
|
uint32_t data;
|
||||||
|
|
||||||
rs1 = get_rs1p();
|
rs1 = get_rs1p();
|
||||||
|
@ -643,13 +643,13 @@ bool C_extension::Exec_C_SW() {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool C_extension::Exec_C_JAL(int m_rd) {
|
bool C_extension::Exec_C_JAL(int m_rd) {
|
||||||
int32_t mem_addr = 0;
|
int32_t mem_addr;
|
||||||
int rd;
|
int rd;
|
||||||
int new_pc, old_pc;
|
int new_pc, old_pc;
|
||||||
|
|
||||||
rd = m_rd;
|
rd = m_rd;
|
||||||
mem_addr = get_imm_J();
|
mem_addr = get_imm_J();
|
||||||
old_pc = regs->getPC();
|
old_pc = static_cast<int32_t>(regs->getPC());
|
||||||
|
|
||||||
new_pc = old_pc + mem_addr;
|
new_pc = old_pc + mem_addr;
|
||||||
regs->setPC(new_pc);
|
regs->setPC(new_pc);
|
||||||
|
|
|
@ -57,7 +57,7 @@ bool M_extension::Exec_M_MUL() const {
|
||||||
|
|
||||||
result = (int64_t) multiplier * multiplicand;
|
result = (int64_t) multiplier * multiplicand;
|
||||||
result = result & 0x00000000FFFFFFFF;
|
result = result & 0x00000000FFFFFFFF;
|
||||||
regs->setValue(rd, result);
|
regs->setValue(rd, static_cast<int32_t>(result));
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "MUL: x" << rs1 << " * x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "MUL: x" << rs1 << " * x" << rs2
|
||||||
<< " -> x" << rd << "(" << result << ")" << "\n";
|
<< " -> x" << rd << "(" << result << ")" << "\n";
|
||||||
|
@ -102,9 +102,9 @@ bool M_extension::Exec_M_MULHSU() const {
|
||||||
multiplier = regs->getValue(rs1);
|
multiplier = regs->getValue(rs1);
|
||||||
multiplicand = regs->getValue(rs2);
|
multiplicand = regs->getValue(rs2);
|
||||||
|
|
||||||
result = (int64_t) multiplier * (uint64_t) multiplicand;
|
result = static_cast<int64_t>(multiplier * (uint64_t) multiplicand);
|
||||||
result = (result >> 32) & 0x00000000FFFFFFFF;
|
result = (result >> 32) & 0x00000000FFFFFFFF;
|
||||||
regs->setValue(rd, result);
|
regs->setValue(rd, static_cast<int32_t>(result));
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
|
||||||
<< " -> x" << rd << "(" << result << ")" << "\n";
|
<< " -> x" << rd << "(" << result << ")" << "\n";
|
||||||
|
@ -126,7 +126,7 @@ bool M_extension::Exec_M_MULHU() const {
|
||||||
multiplicand = (uint32_t) regs->getValue(rs2);
|
multiplicand = (uint32_t) regs->getValue(rs2);
|
||||||
|
|
||||||
result = (uint64_t) multiplier * (uint64_t) multiplicand;
|
result = (uint64_t) multiplier * (uint64_t) multiplicand;
|
||||||
ret_value = (uint32_t) (result >> 32) & 0x00000000FFFFFFFF;
|
ret_value = static_cast<int32_t>((result >> 32) & 0x00000000FFFFFFFF);
|
||||||
regs->setValue(rd, ret_value);
|
regs->setValue(rd, ret_value);
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
|
||||||
|
@ -156,7 +156,7 @@ bool M_extension::Exec_M_DIV() const {
|
||||||
result = result & 0x00000000FFFFFFFF;
|
result = result & 0x00000000FFFFFFFF;
|
||||||
}
|
}
|
||||||
|
|
||||||
regs->setValue(rd, result);
|
regs->setValue(rd, static_cast<int32_t>(result));
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "DIV: x" << rs1 << " / x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "DIV: x" << rs1 << " / x" << rs2
|
||||||
<< " -> x" << rd << "(" << result << ")" << "\n";
|
<< " -> x" << rd << "(" << result << ")" << "\n";
|
||||||
|
@ -183,7 +183,7 @@ bool M_extension::Exec_M_DIVU() const {
|
||||||
result = result & 0x00000000FFFFFFFF;
|
result = result & 0x00000000FFFFFFFF;
|
||||||
}
|
}
|
||||||
|
|
||||||
regs->setValue(rd, result);
|
regs->setValue(rd, static_cast<int32_t>(result));
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
|
||||||
<< " -> x" << rd << "(" << result << ")" << "\n";
|
<< " -> x" << rd << "(" << result << ")" << "\n";
|
||||||
|
@ -237,7 +237,7 @@ bool M_extension::Exec_M_REMU() const {
|
||||||
result = dividend % divisor;
|
result = dividend % divisor;
|
||||||
}
|
}
|
||||||
|
|
||||||
regs->setValue(rd, result);
|
regs->setValue(rd, static_cast<int32_t>(result));
|
||||||
|
|
||||||
log->SC_log(Log::INFO) << std::dec << "REMU: x" << rs1 << " / x" << rs2
|
log->SC_log(Log::INFO) << std::dec << "REMU: x" << rs1 << " / x" << rs2
|
||||||
<< " -> x" << rd << "(" << result << ")" << "\n";
|
<< " -> x" << rd << "(" << result << ")" << "\n";
|
||||||
|
|
|
@ -57,7 +57,7 @@ void MemoryInterface::writeDataMem(uint32_t addr, uint32_t data, int size) {
|
||||||
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&data));
|
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&data));
|
||||||
trans.set_data_length(size);
|
trans.set_data_length(size);
|
||||||
trans.set_streaming_width(4); // = data_length to indicate no streaming
|
trans.set_streaming_width(4); // = data_length to indicate no streaming
|
||||||
trans.set_byte_enable_ptr(0); // 0 indicates unused
|
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
|
||||||
trans.set_dmi_allowed(false); // Mandatory initial value
|
trans.set_dmi_allowed(false); // Mandatory initial value
|
||||||
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
|
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
|
||||||
trans.set_address(addr);
|
trans.set_address(addr);
|
||||||
|
|
|
@ -112,7 +112,7 @@ int32_t Registers::getValue(int reg_num) {
|
||||||
perf->registerRead();
|
perf->registerRead();
|
||||||
return register_bank[reg_num];
|
return register_bank[reg_num];
|
||||||
} else {
|
} else {
|
||||||
return 0xFFFFFFFF;
|
return static_cast<int32_t>(0xFFFFFFFF);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -125,7 +125,7 @@ void Registers::setPC(uint32_t new_pc) {
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t Registers::getCSR(int csr) {
|
uint32_t Registers::getCSR(int csr) {
|
||||||
uint32_t ret_value = 0;
|
uint32_t ret_value;
|
||||||
|
|
||||||
switch (csr) {
|
switch (csr) {
|
||||||
case CSR_CYCLE:
|
case CSR_CYCLE:
|
||||||
|
|
|
@ -72,6 +72,9 @@ void Timer::b_transport(tlm::tlm_generic_payload &trans,
|
||||||
|
|
||||||
timer_event.notify(sc_core::sc_time(notify_time, sc_core::SC_NS));
|
timer_event.notify(sc_core::sc_time(notify_time, sc_core::SC_NS));
|
||||||
break;
|
break;
|
||||||
|
default:
|
||||||
|
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
} else { // TLM_READ_COMMAND
|
} else { // TLM_READ_COMMAND
|
||||||
switch (addr) {
|
switch (addr) {
|
||||||
|
@ -88,6 +91,9 @@ void Timer::b_transport(tlm::tlm_generic_payload &trans,
|
||||||
case TIMERCMP_MEMORY_ADDRESS_HI:
|
case TIMERCMP_MEMORY_ADDRESS_HI:
|
||||||
aux_value = m_mtimecmp.range(63, 32);
|
aux_value = m_mtimecmp.range(63, 32);
|
||||||
break;
|
break;
|
||||||
|
default:
|
||||||
|
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
memcpy(ptr, &aux_value, len);
|
memcpy(ptr, &aux_value, len);
|
||||||
}
|
}
|
||||||
|
|
|
@ -41,7 +41,7 @@ void Trace::xtermLaunch(char *slaveName) const {
|
||||||
execvp("xterm", argv);
|
execvp("xterm", argv);
|
||||||
}
|
}
|
||||||
|
|
||||||
void Trace::xtermKill(const char *mess) {
|
void Trace::xtermKill() {
|
||||||
|
|
||||||
if (-1 != ptSlave) { // Close down the slave
|
if (-1 != ptSlave) { // Close down the slave
|
||||||
close(ptSlave); // Close the FD
|
close(ptSlave); // Close the FD
|
||||||
|
@ -57,11 +57,6 @@ void Trace::xtermKill(const char *mess) {
|
||||||
kill(xtermPid, SIGKILL);
|
kill(xtermPid, SIGKILL);
|
||||||
waitpid(xtermPid, nullptr, 0);
|
waitpid(xtermPid, nullptr, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
if ( nullptr != mess) { // If we really want a message
|
|
||||||
perror(mess);
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void Trace::xtermSetup() {
|
void Trace::xtermSetup() {
|
||||||
|
@ -100,7 +95,7 @@ Trace::Trace(sc_core::sc_module_name const &name) :
|
||||||
}
|
}
|
||||||
|
|
||||||
Trace::~Trace() {
|
Trace::~Trace() {
|
||||||
xtermKill( nullptr);
|
xtermKill();
|
||||||
}
|
}
|
||||||
|
|
||||||
void Trace::b_transport(tlm::tlm_generic_payload &trans,
|
void Trace::b_transport(tlm::tlm_generic_payload &trans,
|
||||||
|
@ -109,7 +104,7 @@ void Trace::b_transport(tlm::tlm_generic_payload &trans,
|
||||||
unsigned char *ptr = trans.get_data_ptr();
|
unsigned char *ptr = trans.get_data_ptr();
|
||||||
delay = sc_core::SC_ZERO_TIME;
|
delay = sc_core::SC_ZERO_TIME;
|
||||||
|
|
||||||
int a = write(ptSlave, ptr, 1);
|
ssize_t a = write(ptSlave, ptr, 1);
|
||||||
(void) a;
|
(void) a;
|
||||||
|
|
||||||
trans.set_response_status(tlm::TLM_OK_RESPONSE);
|
trans.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||||
|
|
|
@ -8,7 +8,7 @@
|
||||||
|
|
||||||
#include "extension_base.h"
|
#include "extension_base.h"
|
||||||
|
|
||||||
extension_base::extension_base(sc_dt::sc_uint<32> const instr,
|
extension_base::extension_base(const sc_dt::sc_uint<32> & instr,
|
||||||
Registers *register_bank, MemoryInterface *mem_interface) :
|
Registers *register_bank, MemoryInterface *mem_interface) :
|
||||||
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
|
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue