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explicit sc_core::wait, typos and newline

This commit is contained in:
mariusmonton 2020-07-19 11:18:58 +02:00
parent d278b1e0a5
commit 1d271cbb0a
3 changed files with 3 additions and 3 deletions
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1
src/A_extension.cpp
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@ -235,6 +235,7 @@ bool A_extension::Exec_A_AMOOR() {
log->SC_log(Log::INFO) << std::dec << "AMOOR " << std::endl; log->SC_log(Log::INFO) << std::dec << "AMOOR " << std::endl;
return true; return true;
} }
bool A_extension::Exec_A_AMOMIN() { bool A_extension::Exec_A_AMOMIN() {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;

2
src/Memory.cpp
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@ -86,7 +86,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
memcpy(&mem[adr], ptr, len); memcpy(&mem[adr], ptr, len);
// Illustrates that b_transport may block // Illustrates that b_transport may block
wait(delay); sc_core::wait(delay);
// Reset timing annotation after waiting // Reset timing annotation after waiting
delay = sc_core::SC_ZERO_TIME; delay = sc_core::SC_ZERO_TIME;

3
src/Registers.cpp
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@ -165,7 +165,7 @@ uint32_t Registers::getCSR(int csr) {
void Registers::setCSR(int csr, uint32_t value) { void Registers::setCSR(int csr, uint32_t value) {
/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to writable, /* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
* but Volume II: Privileged Architectura v1.10 says MISRA is writable (?) * but Volume II: Privileged Architecture v1.10 says MISA is writable (?)
*/ */
if (csr != CSR_MISA) { if (csr != CSR_MISA) {
CSR[csr] = value; CSR[csr] = value;
@ -176,5 +176,4 @@ void Registers::initCSR() {
CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
| MISA_A_EXTENSION | MISA_I_BASE; | MISA_A_EXTENSION | MISA_I_BASE;
CSR[CSR_MSTATUS] = MISA_MXL; CSR[CSR_MSTATUS] = MISA_MXL;
} }