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mariusmonton 2019-01-13 01:36:38 +01:00
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@ -45,17 +45,18 @@ i5-5200<span>@</span>2.2Ghz
This is a preliminar and incomplete version. This is a preliminar and incomplete version.
Task to do: Task to do:
- [x] Implement all missing instructions (Execute) - [x] Implement all missing instructions (Execute)
- [x] Implement CSRs (where/how?) - [x] Implement CSRs (where/how?)
- [ ] Add full support to read file with memory contents (to memory.h) - [ ] Add full support to read file with memory contents (to memory.h)
- [ ] .elf files - [ ] .elf files
- [x] .hex files (only partial .hex support) - [x] .hex files (only partial .hex support)
- [ ] Connect some TLM peripherals - [ ] Connect some TLM peripherals
- [x] Debug module similiar to ARM's ITM - [x] Debug module similiar to ARM's ITM
- [ ] Some standard UART model - [ ] Some standard UART model
- [ ] ... - [ ] ...
- [ ] Implement interrupts - [ ] Implement interrupts
- [ ] implement timer (mtimecmp) & timer interrupt - [x] implement timer (mtimecmp) & timer interrupt
- [ ] generic IRQ comtroller
- [x] Test, test, test & test. I'm sure there are a ~~lot of~~ some bugs in the code - [x] Test, test, test & test. I'm sure there are a ~~lot of~~ some bugs in the code
- [x] riscv-test almost complete (see [Test](https://github.com/mariusmm/RISC-V-TLM/wiki/Tests)) - [x] riscv-test almost complete (see [Test](https://github.com/mariusmm/RISC-V-TLM/wiki/Tests))
- [ ] riscv-compliance WiP - [ ] riscv-compliance WiP