colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

updated

This commit is contained in:
mariusmonton 2019-01-13 01:36:38 +01:00
parent d875dc2cd3
commit 3316575820
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
README.md
View File

@ -55,7 +55,8 @@ Task to do:
- [ ] Some standard UART model
- [ ] ...
- [ ] Implement interrupts
- [ ] implement timer (mtimecmp) & timer interrupt
- [x] implement timer (mtimecmp) & timer interrupt
- [ ] generic IRQ comtroller
- [x] Test, test, test & test. I'm sure there are a ~~lot of~~ some bugs in the code
- [x] riscv-test almost complete (see [Test](https://github.com/mariusmm/RISC-V-TLM/wiki/Tests))
- [ ] riscv-compliance WiP