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risc-v-tlm
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mariusmonton 2018-09-12 13:08:48 +02:00
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.gitignore vendored
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@ -33,3 +33,5 @@
Log.txt Log.txt
helper.ods helper.ods
*.swp
RISCV_TLM

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README.md
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@ -11,6 +11,7 @@ Brief description of the modules:
* Registers: Implements the register file and PC * Registers: Implements the register file and PC
* RISC_V_execute: Executes every ISA instruction * RISC_V_execute: Executes every ISA instruction
* Instruction: Decodes instruction and acces to any instruction field * Instruction: Decodes instruction and acces to any instruction field
* Simulation: Top-level entity that builds & starts the simulation
Current performance is about 166000 instructions / sec in a Core-i5@2.2Ghz Current performance is about 166000 instructions / sec in a Core-i5@2.2Ghz