colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove #include from headers and move to cpp file.

This commit is contained in:
Màrius Montón 2022-09-19 14:43:44 +02:00
parent 0a1a0e6b6d
commit 6b21b1bfee
No known key found for this signature in database
GPG Key ID: FA199E7A752699F0
3 changed files with 16 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
inc/BASE_ISA.h
View File

@ -12,18 +12,10 @@
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <type_traits>
#include <limits>
#include "systemc"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "memory.h"
#include "MemoryInterface.h"
#include "Instruction.h"
#include "C_extension.h"
#include "M_extension.h"
#include "A_extension.h"
#include "Registers.h"
#include "BASE_ISA.h"
#include "extension_base.h"
namespace riscv_tlm {

11
inc/CPU.h
View File

@ -12,20 +12,17 @@
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "systemc"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/tlm_quantumkeeper.h"
#include "tlm_utils/simple_target_socket.h"
#include "memory.h"
#include "MemoryInterface.h"
#include "BASE_ISA.h"
#include "Registers.h"
#include "Instruction.h"
#include "C_extension.h"
#include "M_extension.h"
#include "A_extension.h"
#include "MemoryInterface.h"
#include "Performance.h"
#include "Registers.h"
namespace riscv_tlm {

17
src/BASE_ISA.cpp
View File

@ -7,6 +7,16 @@
// SPDX-License-Identifier: GPL-3.0-or-later
#include "BASE_ISA.h"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "memory.h"
#include "MemoryInterface.h"
#include "Instruction.h"
#include "C_extension.h"
#include "M_extension.h"
#include "A_extension.h"
#include "Registers.h"
namespace riscv_tlm {
@ -55,7 +65,6 @@ namespace riscv_tlm {
return static_cast<std::int32_t>(aux);
}
template<>
std::int32_t BASE_ISA<std::uint32_t>::get_imm_J() const {
std::uint32_t aux = 0;
@ -294,7 +303,6 @@ namespace riscv_tlm {
return this->m_instr.range(31, 26);
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SLLI() {
unsigned int rd, rs1, rs2;
@ -326,7 +334,6 @@ namespace riscv_tlm {
return true;
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SRLI() const {
unsigned int rd, rs1, rs2;
@ -350,7 +357,6 @@ namespace riscv_tlm {
return true;
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SRAI() const {
unsigned int rd, rs1, rs2;
@ -374,7 +380,6 @@ namespace riscv_tlm {
return true;
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SRL() const {
unsigned int rd, rs1, rs2;
@ -398,7 +403,6 @@ namespace riscv_tlm {
return true;
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SRA() const {
unsigned int rd, rs1, rs2;
@ -421,7 +425,6 @@ namespace riscv_tlm {
return true;
}
// PASS
template<>
bool BASE_ISA<std::uint64_t>::Exec_SLL() const {
unsigned int rd, rs1, rs2;