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risc-v-tlm
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stop simulation in case of transaction error

This commit is contained in:
Màrius Montón 2022-09-14 20:04:17 +02:00
parent 9bf2fc7712
commit 9176dbb2ed
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1 changed files with 12 additions and 1 deletions
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13
src/MemoryInterface.cpp
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@ -7,6 +7,8 @@
// SPDX-License-Identifier: GPL-3.0-or-later // SPDX-License-Identifier: GPL-3.0-or-later
#include "MemoryInterface.h" #include "MemoryInterface.h"
#include <iostream>
#include <sstream>
namespace riscv_tlm { namespace riscv_tlm {
@ -36,8 +38,11 @@ namespace riscv_tlm {
data_bus->b_transport(trans, delay); data_bus->b_transport(trans, delay);
if (trans.is_response_error()) { if (trans.is_response_error()) {
SC_REPORT_ERROR("Memory", "Read memory"); std::stringstream error_msg;
error_msg << "Read memory: 0x" << std::hex << addr;
SC_REPORT_ERROR("Memory", error_msg.str().c_str());
} }
return data; return data;
} }
@ -62,5 +67,11 @@ namespace riscv_tlm {
trans.set_address(addr); trans.set_address(addr);
data_bus->b_transport(trans, delay); data_bus->b_transport(trans, delay);
if (trans.is_response_error()) {
std::stringstream error_msg;
error_msg << "Write memory: 0x" << std::hex << addr;
SC_REPORT_ERROR("Memory", error_msg.str().c_str());
}
} }
} }