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risc-v-tlm
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Fixed some bugs
This commit is contained in:
mariusmonton 2019-01-01 21:11:34 +01:00
parent 5c905cb5ca
commit 9a7e7abeb0
4 changed files with 18 additions and 8 deletions
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2
README.md
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@ -19,9 +19,11 @@ Brief description of the modules:
* Execute: Executes ISA instructions * Execute: Executes ISA instructions
* Executes C instruction extensions * Executes C instruction extensions
* Executes M instruction extensions * Executes M instruction extensions
* Executes A instruction extensions
* Instruction: Decodes instruction and acces to any instruction field * Instruction: Decodes instruction and acces to any instruction field
* C_Instruction: Decodes Compressed instructions (C extension) * C_Instruction: Decodes Compressed instructions (C extension)
* M_Instruction: Decodes Multiplication and Division instructions (M extension) * M_Instruction: Decodes Multiplication and Division instructions (M extension)
* A_Instruction: Decodes Atomic instructions (A extension)
* Simulator: Top-level entity that builds & starts the simulation * Simulator: Top-level entity that builds & starts the simulation
* BusCtrl: Simple bus manager * BusCtrl: Simple bus manager
* Trace: Simple trace peripheral * Trace: Simple trace peripheral

2
inc/C_Instruction.h
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@ -272,7 +272,7 @@ public:
aux |= m_instr[2] << 5; aux |= m_instr[2] << 5;
if (m_instr[12] == 1) { if (m_instr[12] == 1) {
aux |= 0b1111 << 12; aux |= 0b11111111111111111111 << 12;
} }
return aux; return aux;

15
src/Execute.cpp
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@ -1111,8 +1111,6 @@ bool Execute::C_JR(Instruction &inst) {
rs1 = c_inst.get_rs1(); rs1 = c_inst.get_rs1();
mem_addr = 0; mem_addr = 0;
std::cout << "rs1 :" << rs1 << std::endl;
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE; new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc); regs->setPC(new_pc);
@ -1158,7 +1156,7 @@ bool Execute::C_ADD(Instruction &inst) {
log->SC_log(Log::INFO) << "C.ADD: x" log->SC_log(Log::INFO) << "C.ADD: x"
<< dec << rs1 << " + x" << dec << rs1 << " + x"
<< rs2 << " -> x" << rs2 << " -> x"
<< rd << endl; << rd << "(0x" << hex << calc << ")" << endl;
return true; return true;
} }
@ -1182,8 +1180,8 @@ bool Execute::C_LWSP(Instruction &inst) {
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "C.LWSP: x" << dec log->SC_log(Log::INFO) << "C.LWSP: x" << dec
<< rs1 << "(0x" << hex << regs->getValue(rs1) << ") + " << rs1 << " + " << imm
<< dec << imm << " (@0x" << hex << mem_addr << dec << ") -> x" << " (@0x" << hex << mem_addr << dec << ") -> x"
<< rd << "(" << hex << data << ")"<< dec << endl; << rd << "(" << hex << data << ")"<< dec << endl;
return true; return true;
@ -1408,7 +1406,7 @@ bool Execute::C_SLLI(Instruction &inst) {
log->SC_log(Log::INFO) << "C.SLLI: x" log->SC_log(Log::INFO) << "C.SLLI: x"
<< dec << rs1 << " << " << dec << rs1 << " << "
<< shift << " -> x" << shift << " -> x"
<< rd << endl; << rd << "(0x" << calc << ")"<< endl;
return true; return true;
} }
@ -2155,6 +2153,11 @@ void Execute::RaiseException(uint32_t cause, uint32_t inst) {
regs->setPC( new_pc); regs->setPC( new_pc);
log->SC_log(Log::INFO) << "Exception! new PC " << hex << new_pc << endl; log->SC_log(Log::INFO) << "Exception! new PC " << hex << new_pc << endl;
regs->dump();
cout << "Simulation time " << sc_time_stamp() << endl;
perf->dump();
SC_REPORT_ERROR("Exception" , "Exception");
} }

7
src/Registers.cpp
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@ -8,7 +8,12 @@ Registers::Registers() {
initCSR(); initCSR();
//register_bank[sp] = 1024-1; // SP points to end of memory //register_bank[sp] = 1024-1; // SP points to end of memory
register_bank[sp] = Memory::SIZE-4; //register_bank[sp] = 0x70000000;
register_bank[sp] = (0x10000000 / 4) - 1;
//cout << "Memory size: 0x" << hex << Memory::SIZE << endl;
//cout << "SP address: 0x" << hex << (0x10000000 / 4) - 1 << endl;
//register_bank[sp] = Memory::SIZE-4;
register_PC = 0x80000000; // default _start address register_PC = 0x80000000; // default _start address
} }