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risc-v-tlm
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Remove SC_MODULE macros, other trivial code clean-up

This commit is contained in:
Màrius Montón 2021-06-30 15:37:18 +02:00
parent 40c9d678ef
commit c9bab2ae27
5 changed files with 8 additions and 9 deletions
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3
inc/BusCtrl.h
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@ -72,7 +72,7 @@ public:
* @brief constructor * @brief constructor
* @param name module's name * @param name module's name
*/ */
explicit BusCtrl(sc_core::sc_module_name name); explicit BusCtrl(sc_core::sc_module_name const &name);
/** /**
* @brief TLM-2 blocking mechanism * @brief TLM-2 blocking mechanism
@ -83,7 +83,6 @@ public:
sc_core::sc_time &delay); sc_core::sc_time &delay);
private: private:
Log *log;
bool instr_direct_mem_ptr(tlm::tlm_generic_payload&, bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
tlm::tlm_dmi &dmi_data); tlm::tlm_dmi &dmi_data);

2
inc/CPU.h
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@ -54,7 +54,7 @@ public:
* @param PC Program Counter initialize value * @param PC Program Counter initialize value
* @param debug To start debugging * @param debug To start debugging
*/ */
CPU(sc_core::sc_module_name name, uint32_t PC, bool debug); CPU(sc_core::sc_module_name const &name, uint32_t PC, bool debug);
/** /**
* @brief Destructor * @brief Destructor

3
src/BusCtrl.cpp
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@ -9,13 +9,12 @@
#include "BusCtrl.h" #include "BusCtrl.h"
SC_HAS_PROCESS(BusCtrl); SC_HAS_PROCESS(BusCtrl);
BusCtrl::BusCtrl(sc_core::sc_module_name const name) : BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket( sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
"cpu_data_socket"), memory_socket("memory_socket"), trace_socket( "cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
"trace_socket") { "trace_socket") {
cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport); cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport); cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
log = Log::getInstance();
cpu_instr_socket.register_get_direct_mem_ptr(this, cpu_instr_socket.register_get_direct_mem_ptr(this,
&BusCtrl::instr_direct_mem_ptr); &BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this, memory_socket.register_invalidate_direct_mem_ptr(this,

2
src/CPU.cpp
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@ -8,7 +8,7 @@
#include "CPU.h" #include "CPU.h"
SC_HAS_PROCESS(CPU); SC_HAS_PROCESS(CPU);
CPU::CPU(sc_core::sc_module_name const name, uint32_t PC, bool debug) : CPU::CPU(sc_core::sc_module_name const &name, uint32_t PC, bool debug) :
sc_module(name), instr_bus("instr_bus"), default_time(10, sc_module(name), instr_bus("instr_bus"), default_time(10,
sc_core::SC_NS), INSTR(0) { sc_core::SC_NS), INSTR(0) {
register_bank = new Registers(); register_bank = new Registers();

7
src/Simulator.cpp
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@ -30,14 +30,15 @@ bool debug_session = false;
* *
* @brief Top simulation entity * @brief Top simulation entity
*/ */
SC_MODULE(Simulator) { class Simulator : sc_core::sc_module {
CPU *cpu; public:
CPU *cpu;
Memory *MainMemory; Memory *MainMemory;
BusCtrl *Bus; BusCtrl *Bus;
Trace *trace; Trace *trace;
Timer *timer; Timer *timer;
SC_CTOR(Simulator) { explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) {
uint32_t start_PC; uint32_t start_PC;
MainMemory = new Memory("Main_Memory", filename); MainMemory = new Memory("Main_Memory", filename);