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risc-v-tlm
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Exception doesn't stop simulation

This commit is contained in:
Màrius Montón 2021-11-08 09:24:43 +01:00
parent 08d699d34e
commit e9e4543f72
2 changed files with 3 additions and 8 deletions
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1
inc/extension_base.h
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@ -20,6 +20,7 @@
#define EXCEPTION_CAUSE_INSTRUCTION_ACCESS 1
#define EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION 2
#define EXCEPTION_CAUSE_BREAKPOINT 3
#define EXCEPTION_CAUSE_BREAK 3
#define EXCEPTION_CAUSE_LOAD_ADDR_MISALIGN 4
#define EXCEPTION_CAUSE_LOAD_ACCESS_FAULT 5

10
src/extension_base.cpp
View File

@ -49,18 +49,12 @@ void extension_base::RaiseException(uint32_t cause, uint32_t inst) {
regs->setPC(new_pc);
log->SC_log(Log::ERROR) << "Exception! new PC 0x" << std::hex << new_pc
<< std::endl;
regs->dump();
std::cout << "Simulation time " << sc_core::sc_time_stamp() << std::endl;
perf->dump();
sc_core::sc_stop();
<< std::endl << std::flush;;
}
bool extension_base::NOP() {
log->SC_log(Log::INFO) << "NOP" << "\n";
sc_core::sc_stop();
return true;
}