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risc-v-tlm
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trivial changes to increase performance

This commit is contained in:
mariusmonton 2021-01-15 09:09:52 +01:00
parent a713e13705
commit f7dbf106cc
17 changed files with 51 additions and 51 deletions
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2
inc/A_extension.h
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@ -133,7 +133,7 @@ public:
bool Exec_A_AMOMINU();
bool Exec_A_AMOMAXU();
bool process_instruction(Instruction &inst);
bool process_instruction(Instruction *inst);
void TLB_reserve(uint32_t address);
bool TLB_reserved(uint32_t address);

2
inc/BASE_ISA.h
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@ -411,7 +411,7 @@ public:
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
bool process_instruction(Instruction &inst);
bool process_instruction(Instruction *inst);
/**
* @brief Decodes opcode of instruction

2
inc/C_extension.h
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@ -416,7 +416,7 @@ public:
bool Exec_C_SW();
bool Exec_C_JAL(int m_rd);
bool process_instruction(Instruction &inst);
bool process_instruction(Instruction *inst);
};
#endif

4
inc/Instruction.h
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@ -35,7 +35,7 @@ typedef enum {
class Instruction {
public:
Instruction(sc_dt::sc_uint<32> instr);
Instruction(uint32_t instr);
/**
* @brief returns what instruction extension
@ -59,7 +59,7 @@ public:
}
private:
sc_dt::sc_uint<32> m_instr;
uint32_t m_instr;
};
#endif

2
inc/M_extension.h
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@ -69,7 +69,7 @@ public:
bool Exec_M_REM();
bool Exec_M_REMU();
bool process_instruction(Instruction &inst);
bool process_instruction(Instruction *inst);
private:

14
inc/Performance.h
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@ -87,13 +87,13 @@ private:
static Performance *instance;
Performance();
uint64_t data_memory_read;
uint64_t data_memory_write;
uint64_t code_memory_read;
uint64_t code_memory_write;
uint64_t register_read;
uint64_t register_write;
uint64_t instructions_executed;
uint_fast64_t data_memory_read;
uint_fast64_t data_memory_write;
uint_fast64_t code_memory_read;
uint_fast64_t code_memory_write;
uint_fast64_t register_read;
uint_fast64_t register_write;
uint_fast64_t instructions_executed;
};
#endif

4
inc/Registers.h
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@ -245,7 +245,7 @@ private:
/**
* bank of registers (32 regs of 32bits each)
*/
int32_t register_bank[32];
std::array<int,32> register_bank{0};
/**
* Program counter (32 bits width)
@ -256,7 +256,7 @@ private:
* CSR registers (4096 maximum)
*/
//uint32_t CSR[4096];
std::unordered_map<unsigned int, uint32_t> CSR;
std::unordered_map<unsigned int, uint32_t> CSR{0};
Performance *perf;

6
src/A_extension.cpp
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@ -367,10 +367,10 @@ bool A_extension::TLB_reserved(uint32_t address) {
}
}
bool A_extension::process_instruction(Instruction &inst) {
bool A_extension::process_instruction(Instruction *inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
setInstr(inst->getInstr());
switch (decode()) {
case OP_A_LR:
@ -408,7 +408,7 @@ bool A_extension::process_instruction(Instruction &inst) {
break;
[[unlikely]] default:
std::cout << "A instruction not implemented yet" << std::endl;
inst.dump();
inst->dump();
NOP();
break;
}

6
src/BASE_ISA.cpp
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@ -1150,10 +1150,10 @@ bool BASE_ISA::Exec_SFENCE() {
return true;
}
bool BASE_ISA::process_instruction(Instruction &inst) {
bool BASE_ISA::process_instruction(Instruction *inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
setInstr(inst->getInstr());
switch (decode()) {
case OP_LUI:
@ -1318,7 +1318,7 @@ bool BASE_ISA::process_instruction(Instruction &inst) {
break;
[[unlikely]] default:
std::cout << "Wrong instruction" << "\n";
inst.dump();
inst->dump();
NOP();
//sc_stop();
break;

2
src/BusCtrl.cpp
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@ -24,7 +24,7 @@ BusCtrl::BusCtrl(sc_core::sc_module_name name) :
void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
//tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address() / 4;
switch (adr) {

12
src/CPU.cpp
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@ -163,19 +163,19 @@ void CPU::CPU_thread(void) {
/* check what type of instruction is and execute it */
switch (inst->check_extension()) {
[[likely]] case BASE_EXTENSION:
PC_not_affected = exec->process_instruction(*inst);
PC_not_affected = exec->process_instruction(inst);
incPCby2 = false;
break;
case C_EXTENSION:
PC_not_affected = c_inst->process_instruction(*inst);
PC_not_affected = c_inst->process_instruction(inst);
incPCby2 = true;
break;
case M_EXTENSION:
PC_not_affected = m_inst->process_instruction(*inst);
PC_not_affected = m_inst->process_instruction(inst);
incPCby2 = false;
break;
case A_EXTENSION:
PC_not_affected = a_inst->process_instruction(*inst);
PC_not_affected = a_inst->process_instruction(inst);
incPCby2 = false;
break;
[[unlikely]] default:
@ -202,10 +202,8 @@ void CPU::CPU_thread(void) {
m_qk->sync();
}
#else
sc_core::wait(10, sc_core::SC_NS);
//sc_core::wait(10, sc_core::SC_NS);
#endif
} // while(1)
} // CPU_thread

8
src/CPU64.cpp
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@ -163,19 +163,19 @@ void CPU64::CPU_thread(void) {
/* check what type of instruction is and execute it */
switch (inst->check_extension()) {
[[likely]] case BASE_EXTENSION:
PC_not_affected = exec->process_instruction(*inst);
PC_not_affected = exec->process_instruction(inst);
incPCby2 = false;
break;
case C_EXTENSION:
PC_not_affected = c_inst->process_instruction(*inst);
PC_not_affected = c_inst->process_instruction(inst);
incPCby2 = true;
break;
case M_EXTENSION:
PC_not_affected = m_inst->process_instruction(*inst);
PC_not_affected = m_inst->process_instruction(inst);
incPCby2 = false;
break;
case A_EXTENSION:
PC_not_affected = a_inst->process_instruction(*inst);
PC_not_affected = a_inst->process_instruction(inst);
incPCby2 = false;
break;
[[unlikely]] default:

6
src/C_extension.cpp
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@ -661,10 +661,10 @@ bool C_extension::Exec_C_JAL(int m_rd) {
return true;
}
bool C_extension::process_instruction(Instruction &inst) {
bool C_extension::process_instruction(Instruction *inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
setInstr(inst->getInstr());
switch (decode()) {
case OP_C_ADDI4SPN:
@ -747,7 +747,7 @@ bool C_extension::process_instruction(Instruction &inst) {
break;
[[unlikely]] default:
std::cout << "C instruction not implemented yet" << "\n";
inst.dump();
inst->dump();
NOP();
break;
}

19
src/Instruction.cpp
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@ -8,26 +8,29 @@
#include "Instruction.h"
Instruction::Instruction(sc_dt::sc_uint<32> instr) {
Instruction::Instruction(uint32_t instr) {
m_instr = instr;
}
extension_t Instruction::check_extension() {
if ((m_instr.range(6, 0) == 0b0110011)
&& (m_instr.range(31, 25) == 0b0000001)) {
if (((m_instr & 0x0000007F) == 0b0110011)
&& ( ((m_instr & 0x7F000000) >> 25) == 0b0000001)) {
return M_EXTENSION;
} else if (m_instr.range(6, 0) == 0b0101111) {
} else if ((m_instr & 0x0000007F) == 0b0101111) {
return A_EXTENSION;
} else if (m_instr.range(1, 0) == 0b11) {
} else if ((m_instr & 0x00000003) == 0b11) {
return BASE_EXTENSION;
} else if (m_instr.range(1, 0) == 0b00) {
} else if ((m_instr & 0x00000003) == 0b00) {
return C_EXTENSION;
} else if (m_instr.range(1, 0) == 0b01) {
} else if ((m_instr & 0x00000003) == 0b01) {
return C_EXTENSION;
} else if (m_instr.range(1, 0) == 0b10) {
} else if ((m_instr & 0x00000003) == 0b10) {
return C_EXTENSION;
} else {
std::cout << "Unknown\n";
return UNKNOWN_EXTENSION;
}
}

6
src/M_extension.cpp
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@ -245,10 +245,10 @@ bool M_extension::Exec_M_REMU() {
return true;
}
bool M_extension::process_instruction(Instruction &inst) {
bool M_extension::process_instruction(Instruction *inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
setInstr(inst->getInstr());
switch (decode()) {
case OP_M_MUL:
@ -277,7 +277,7 @@ bool M_extension::process_instruction(Instruction &inst) {
break;
[[unlikely]] default:
std::cout << "M instruction not implemented yet" << "\n";
inst.dump();
inst->dump();
//NOP(inst);
sc_core::sc_stop();
break;

5
src/Memory.cpp
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@ -58,6 +58,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
unsigned int wid = trans.get_streaming_width();
adr = adr - memory_offset;
// Obliged to check address range and check for unsupported features,
// i.e. byte enables, streaming, and bursts
// Can ignore extensions
@ -65,7 +66,6 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
// *********************************************
// Generate the appropriate error response
// *********************************************
if (adr >= sc_dt::uint64(SIZE)) {
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
@ -79,6 +79,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
return;
}
// Obliged to implement read and write commands
if (cmd == tlm::TLM_READ_COMMAND)
memcpy(ptr, &mem[adr], len);
@ -86,7 +87,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
memcpy(&mem[adr], ptr, len);
// Illustrates that b_transport may block
sc_core::wait(delay);
//sc_core::wait(delay);
// Reset timing annotation after waiting
delay = sc_core::SC_ZERO_TIME;

2
src/Registers.cpp
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@ -10,8 +10,6 @@
Registers::Registers() {
memset(register_bank, 0, sizeof(uint32_t) * 32); // 32 registers of 32 bits each
//memset(CSR, 0, sizeof(uint32_t) * 4096);
perf = Performance::getInstance();
initCSR();