a8bdc37c12
all tests passed!
2018-11-14 19:14:57 +01:00
d449ea5502
adding M extensions to simulator
2018-11-12 17:41:17 +01:00
1fcbcf500b
typos 6 minor changes
2018-11-11 11:12:12 +01:00
9d7d84c7f8
bugs!
2018-11-07 18:43:10 +01:00
598699cd54
more bug fixes, still get j zero in func3 test example
2018-10-17 17:42:43 +02:00
374b853117
first version of C.extensions
2018-10-15 17:35:16 +02:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
f17b3b75d5
new setters to Instruction class
2018-10-10 18:58:08 +02:00
08044ac626
* Instruction: changed name to accessors
...
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
70de804983
non-static data intialization removed, moved to constructor
2018-09-27 14:32:40 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
afbf317941
updated documentation
2018-09-21 11:23:31 +02:00
21003e2fa9
remove unused SC_THREAD
2018-09-21 09:24:49 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
11fae01cba
Changed memory to be addressable to byte instead to word (32bits)
2018-09-20 12:22:13 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
mariusmonton