4c89c48fb0
removed SP init, moved to CPU module
2019-01-22 18:30:09 +01:00
9a7e7abeb0
Better logs
...
Fixed some bugs
2019-01-01 21:11:34 +01:00
5c905cb5ca
better MISA CSR register support
2018-12-12 18:15:44 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
81f61c52fc
fixed dump function!
2018-11-25 12:05:09 +01:00
6726b59c3c
bug on SLLI
2018-11-22 12:39:16 +01:00
0cd34f9f3b
fixed CSRRS and CSRRC bug
2018-11-22 12:08:16 +01:00
598699cd54
more bug fixes, still get j zero in func3 test example
2018-10-17 17:42:43 +02:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
dcd3a8c3fe
better log output
2018-09-21 09:25:27 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
8e8418e3e2
Better logging output
2018-09-20 12:21:15 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
mariusmonton