colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
90 Commits 1 Branch 0 Tags 2.1 MiB
Commit Graph

9 Commits

Author SHA1 Message Date
mariusmonton a4a1be7386 IRQ implemented 2019-01-13 01:30:49 +01:00
mariusmonton a2a9c95546 Added A Extensions 
Added SFENCE instruction
 2018-12-12 18:14:35 +01:00
mariusmonton d449ea5502 adding M extensions to simulator 2018-11-12 17:41:17 +01:00
mariusmonton aa526943b9 Added instructions to pass riscv-tests 2018-10-15 13:51:41 +02:00
mariusmonton 08044ac626 * Instruction: changed name to accessors 
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
 2018-10-10 12:08:53 +02:00
mariusmonton a5773202e1 renamed RISC_V_execute to Execute 2018-09-21 13:05:42 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00
mariusmonton 1c9bfe8c60 Added Data Memory bus. Implemented LW & SW instructions. 2018-09-17 12:21:26 +02:00
mariusmonton 35e688837a initial import 2018-09-10 18:44:54 +02:00