5d30416955
Fixed some warnings from coverity
2020-04-10 16:43:22 +02:00
e75a4bfdfd
add missing CSR register MCYcLE and similars
2019-09-13 00:00:59 +02:00
2c2cf3000b
typos, register definitions
2019-02-11 15:52:48 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
5c905cb5ca
better MISA CSR register support
2018-12-12 18:15:44 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
b9e26e4dea
first implementation supporting exceptions
2018-11-22 14:38:31 +01:00
6726b59c3c
bug on SLLI
2018-11-22 12:39:16 +01:00
0cd34f9f3b
fixed CSRRS and CSRRC bug
2018-11-22 12:08:16 +01:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
mariusmonton