mariusmonton
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5d30416955
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Fixed some warnings from coverity
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2020-04-10 16:43:22 +02:00 |
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mariusmonton
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e75a4bfdfd
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add missing CSR register MCYcLE and similars
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2019-09-13 00:00:59 +02:00 |
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Màrius Montón
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916ab46907
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print out test result at the end of simulation
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2019-09-10 12:36:45 +02:00 |
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Màrius Montón
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d63d95f634
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fixed bug related DMI access when memory offset != 0
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2019-09-10 12:24:46 +02:00 |
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Màrius Montón
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1bb3200eb6
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add destructor for clean exit
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2019-09-08 11:42:05 +02:00 |
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Màrius Montón
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1babf6cb88
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added sc_stop at the end of the simulation to call destructors
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2019-09-08 11:41:30 +02:00 |
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Màrius Montón
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0415ba3c66
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added xterm window for trace output
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2019-09-08 11:41:06 +02:00 |
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mariusmonton
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d42d67b991
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DMI access added (if available)
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2019-03-28 22:52:36 +01:00 |
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mariusmonton
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5ad8ced434
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better log for CSRRW instruction
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2019-02-18 13:57:24 +01:00 |
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mariusmonton
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a275e0fa24
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better support to IRQs
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2019-02-18 13:56:47 +01:00 |
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mariusmonton
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e31eae3f9e
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added command line arguments
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2019-02-12 14:08:40 +01:00 |
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mariusmonton
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1d4c3ec553
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removed unused code
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2019-02-12 11:40:25 +01:00 |
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mariusmonton
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d62892e3dc
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minor changes, better code
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2019-02-11 20:26:23 +01:00 |
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mariusmonton
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a87743b92d
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minor changes
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2019-02-11 15:54:13 +01:00 |
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mariusmonton
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2c93492ab1
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enhanced IRQ support
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2019-02-11 15:54:02 +01:00 |
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mariusmonton
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4c89c48fb0
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removed SP init, moved to CPU module
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2019-01-22 18:30:09 +01:00 |
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mariusmonton
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d83a15eec5
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change log level
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2019-01-22 12:47:54 +01:00 |
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mariusmonton
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098aebc15d
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changed IRQ line to TLM socket
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2019-01-22 12:43:05 +01:00 |
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mariusmonton
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0c25abdb00
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Fixed bug
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2019-01-22 12:33:32 +01:00 |
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mariusmonton
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7c263419a8
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documentation
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2019-01-13 18:39:35 +01:00 |
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mariusmonton
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a4a1be7386
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IRQ implemented
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2019-01-13 01:30:49 +01:00 |
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mariusmonton
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9a7e7abeb0
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Better logs
Fixed some bugs
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2019-01-01 21:11:34 +01:00 |
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mariusmonton
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5c905cb5ca
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better MISA CSR register support
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2018-12-12 18:15:44 +01:00 |
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mariusmonton
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93fe2237b4
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better support to hex file
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2018-12-12 18:15:21 +01:00 |
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mariusmonton
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a2a9c95546
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Added A Extensions
Added SFENCE instruction
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2018-12-12 18:14:35 +01:00 |
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mariusmonton
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1b93e7f569
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added time management and cycle counters
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2018-11-25 12:07:08 +01:00 |
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mariusmonton
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81f61c52fc
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fixed dump function!
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2018-11-25 12:05:09 +01:00 |
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mariusmonton
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0f291016c5
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add support to RaiseExecption to all instructions
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2018-11-24 23:46:47 +01:00 |
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mariusmonton
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4114f482d6
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Doxygen
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2018-11-24 23:46:01 +01:00 |
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mariusmonton
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d5489523de
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better log output
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2018-11-22 16:53:26 +01:00 |
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mariusmonton
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c832b2f80f
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all tests passed!
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2018-11-22 16:42:06 +01:00 |
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mariusmonton
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b9e26e4dea
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first implementation supporting exceptions
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2018-11-22 14:38:31 +01:00 |
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mariusmonton
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6726b59c3c
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bug on SLLI
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2018-11-22 12:39:16 +01:00 |
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mariusmonton
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0cd34f9f3b
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fixed CSRRS and CSRRC bug
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2018-11-22 12:08:16 +01:00 |
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mariusmonton
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9cd354b822
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C examples halts simulation
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2018-11-19 17:22:18 +01:00 |
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mariusmonton
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ed7be704f9
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implementation of all remaining C extension
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2018-11-19 15:56:08 +01:00 |
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mariusmonton
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3f7ecfa9df
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bug fixes
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2018-11-14 23:50:01 +01:00 |
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mariusmonton
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adc30178ab
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fixed detection of M extension
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2018-11-14 23:14:06 +01:00 |
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mariusmonton
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a8bdc37c12
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all tests passed!
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2018-11-14 19:14:57 +01:00 |
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mariusmonton
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d449ea5502
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adding M extensions to simulator
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2018-11-12 17:41:17 +01:00 |
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mariusmonton
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bdf261cbc6
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default value to variable to remove a warning
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2018-11-12 17:08:26 +01:00 |
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mariusmonton
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1fcbcf500b
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typos 6 minor changes
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2018-11-11 11:12:12 +01:00 |
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mariusmonton
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36646a182e
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buf, intermediate value whould be 32 bits long
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2018-11-08 18:55:47 +01:00 |
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mariusmonton
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9d7d84c7f8
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bugs!
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2018-11-07 18:43:10 +01:00 |
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mariusmonton
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598699cd54
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more bug fixes, still get j zero in func3 test example
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2018-10-17 17:42:43 +02:00 |
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mariusmonton
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374b853117
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first version of C.extensions
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2018-10-15 17:35:16 +02:00 |
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mariusmonton
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97b15ca7a3
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better (?) Log output
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2018-10-15 17:34:42 +02:00 |
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mariusmonton
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a409f48d40
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Fixed wrong immediate accesses
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2018-10-15 17:33:41 +02:00 |
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mariusmonton
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5ae765b304
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Proper initialization of sp register
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2018-10-15 17:32:37 +02:00 |
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mariusmonton
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aa526943b9
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Added instructions to pass riscv-tests
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2018-10-15 13:51:41 +02:00 |