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17 Commits

Author SHA1 Message Date
mariusmonton 66b27f7613 innecessary file 2018-09-20 12:24:48 +02:00
mariusmonton 9961f080c9 examples updated 2018-09-20 12:24:07 +02:00
mariusmonton 11fae01cba Changed memory to be addressable to byte instead to word (32bits) 2018-09-20 12:22:13 +02:00
mariusmonton 8e8418e3e2 Better logging output 2018-09-20 12:21:15 +02:00
mariusmonton a5cc9d60d2 updated with C examples 2018-09-20 00:06:25 +02:00
mariusmonton ea116f90e9 ASM examples updated 2018-09-19 23:52:48 +02:00
mariusmonton 17ac1ae411 C code examples 2018-09-19 23:51:56 +02:00
mariusmonton 7910a061bc updated README and minor changes 2018-09-19 23:51:01 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00
mariusmonton 79cff335e3 updated 2018-09-17 12:35:52 +02:00
mariusmonton d0806a5759 added missing Load/Store instructions 2018-09-17 12:35:36 +02:00
mariusmonton 1c9bfe8c60 Added Data Memory bus. Implemented LW & SW instructions. 2018-09-17 12:21:26 +02:00
mariusmonton c5ec56ec08 Added -O3 optimization option to g++ 2018-09-15 11:43:33 +02:00
mariusmonton 53b6234ecb minor changes 2018-09-12 13:08:48 +02:00
mariusmonton 7254794fcd benchmark 2018-09-11 23:34:30 +02:00
mariusmonton 35e688837a initial import 2018-09-10 18:44:54 +02:00
Màrius Montón 26e67681f0
Initial commit 2018-09-10 18:41:14 +02:00