Màrius Montón
|
92a450b75e
|
updated performance with new computer
|
2019-09-12 11:30:57 +02:00 |
|
Màrius Montón
|
916ab46907
|
print out test result at the end of simulation
|
2019-09-10 12:36:45 +02:00 |
|
Màrius Montón
|
d63d95f634
|
fixed bug related DMI access when memory offset != 0
|
2019-09-10 12:24:46 +02:00 |
|
Màrius Montón
|
1d7c8bbdac
|
missing docker command line update
|
2019-09-09 14:13:45 +02:00 |
|
Màrius Montón
|
37891e28a0
|
fixed wrong binary name
|
2019-09-09 14:09:16 +02:00 |
|
Màrius Montón
|
2c5615fc8d
|
updated Docker information
|
2019-09-09 14:09:06 +02:00 |
|
Màrius Montón
|
4d5efee0e9
|
added xterm package to docker image
|
2019-09-08 15:39:32 +02:00 |
|
Màrius Montón
|
1bb3200eb6
|
add destructor for clean exit
|
2019-09-08 11:42:05 +02:00 |
|
Màrius Montón
|
1babf6cb88
|
added sc_stop at the end of the simulation to call destructors
|
2019-09-08 11:41:30 +02:00 |
|
Màrius Montón
|
0415ba3c66
|
added xterm window for trace output
|
2019-09-08 11:41:06 +02:00 |
|
Màrius Montón
|
e2f3dfb30c
|
fixed wrong dump executable name
|
2019-09-07 11:41:16 +02:00 |
|
Màrius Montón
|
96c17868e4
|
added unused sys functions to avoid warning on compile
|
2019-09-07 11:40:00 +02:00 |
|
Màrius Montón
|
a703c5f4ba
|
new malloc test
|
2019-09-07 11:39:09 +02:00 |
|
Màrius Montón
|
dd847804c0
|
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
|
2019-07-12 17:50:20 +02:00 |
|
Màrius Montón
|
30e81424ee
|
added coverage
|
2019-07-12 17:50:07 +02:00 |
|
Màrius Montón
|
32c9c6c6a5
|
Update README.md
typos
|
2019-06-22 17:07:34 +02:00 |
|
Màrius Montón
|
45c1548971
|
Update README.md
add how to compile cross compiler for riscv32
|
2019-06-22 16:31:06 +02:00 |
|
mariusmonton
|
f140f5118f
|
update how to work with assembly files
|
2019-06-09 21:19:47 +02:00 |
|
mariusmonton
|
1d1c1b0931
|
added memory map
|
2019-04-10 11:16:14 +02:00 |
|
mariusmonton
|
471d2c045f
|
Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
|
2019-03-28 22:53:53 +01:00 |
|
mariusmonton
|
d42d67b991
|
DMI access added (if available)
|
2019-03-28 22:52:36 +01:00 |
|
Màrius Montón
|
0a5938a13f
|
Update issue templates
|
2019-02-21 13:27:37 +01:00 |
|
mariusmonton
|
24a27f39fe
|
another test, long loop for long tests
|
2019-02-18 23:28:46 +01:00 |
|
mariusmonton
|
5ad8ced434
|
better log for CSRRW instruction
|
2019-02-18 13:57:24 +01:00 |
|
mariusmonton
|
9d89f847a0
|
better dockerfile style
|
2019-02-18 13:57:02 +01:00 |
|
mariusmonton
|
a275e0fa24
|
better support to IRQs
|
2019-02-18 13:56:47 +01:00 |
|
mariusmonton
|
a91e590d6d
|
other usage of docker image
|
2019-02-15 14:30:12 +01:00 |
|
mariusmonton
|
e31eae3f9e
|
added command line arguments
|
2019-02-12 14:08:40 +01:00 |
|
mariusmonton
|
1d4c3ec553
|
removed unused code
|
2019-02-12 11:40:25 +01:00 |
|
mariusmonton
|
492cfd61e9
|
better extension enumeration
|
2019-02-12 11:39:15 +01:00 |
|
mariusmonton
|
111bf08297
|
added ISR register to vPortSetupTimer() function
|
2019-02-11 20:36:16 +01:00 |
|
mariusmonton
|
d62892e3dc
|
minor changes, better code
|
2019-02-11 20:26:23 +01:00 |
|
mariusmonton
|
6f8cc9ded6
|
updated with FreeRTOS port
|
2019-02-11 20:16:32 +01:00 |
|
mariusmonton
|
1c50b22c27
|
FreeRTOS portable files for this simulator
|
2019-02-11 20:12:30 +01:00 |
|
mariusmonton
|
a87743b92d
|
minor changes
|
2019-02-11 15:54:13 +01:00 |
|
mariusmonton
|
2c93492ab1
|
enhanced IRQ support
|
2019-02-11 15:54:02 +01:00 |
|
mariusmonton
|
2c2cf3000b
|
typos, register definitions
|
2019-02-11 15:52:48 +01:00 |
|
mariusmonton
|
6c0d2708a8
|
error in docker doc
|
2019-02-07 22:41:14 +01:00 |
|
mariusmonton
|
23f12f3daf
|
default all: option
|
2019-02-06 19:14:23 +01:00 |
|
mariusmonton
|
c00b1582d9
|
TOC
|
2019-02-04 13:16:50 +01:00 |
|
mariusmonton
|
6ea7f7a062
|
updated docker information
|
2019-02-03 21:46:38 +01:00 |
|
mariusmonton
|
50147b4762
|
Added Docker container
|
2019-02-03 12:05:06 +01:00 |
|
mariusmonton
|
a8943a111f
|
enable interrupts writing to mstatus
|
2019-01-22 19:31:13 +01:00 |
|
mariusmonton
|
fa3b178f79
|
update instruction/second
|
2019-01-22 18:34:48 +01:00 |
|
mariusmonton
|
4c89c48fb0
|
removed SP init, moved to CPU module
|
2019-01-22 18:30:09 +01:00 |
|
mariusmonton
|
d6f774eaea
|
Timer module test
|
2019-01-22 18:29:12 +01:00 |
|
mariusmonton
|
e9ef03890f
|
fixed ISR memory alignement
|
2019-01-22 13:26:41 +01:00 |
|
mariusmonton
|
d83a15eec5
|
change log level
|
2019-01-22 12:47:54 +01:00 |
|
mariusmonton
|
098aebc15d
|
changed IRQ line to TLM socket
|
2019-01-22 12:43:05 +01:00 |
|
mariusmonton
|
0c25abdb00
|
Fixed bug
|
2019-01-22 12:33:32 +01:00 |