97b15ca7a3
better (?) Log output
2018-10-15 17:34:42 +02:00
a409f48d40
Fixed wrong immediate accesses
2018-10-15 17:33:41 +02:00
5ae765b304
Proper initialization of sp register
2018-10-15 17:32:37 +02:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
08044ac626
* Instruction: changed name to accessors
...
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
70de804983
non-static data intialization removed, moved to constructor
2018-09-27 14:32:40 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
afbf317941
updated documentation
2018-09-21 11:23:31 +02:00
4ba8b1bbb7
Added better PC control
2018-09-21 09:25:47 +02:00
dcd3a8c3fe
better log output
2018-09-21 09:25:27 +02:00
21003e2fa9
remove unused SC_THREAD
2018-09-21 09:24:49 +02:00
406d498209
added PC control
2018-09-21 09:24:25 +02:00
981b84a5eb
Better register dump
2018-09-20 15:29:22 +02:00
11fae01cba
Changed memory to be addressable to byte instead to word (32bits)
2018-09-20 12:22:13 +02:00
8e8418e3e2
Better logging output
2018-09-20 12:21:15 +02:00
7910a061bc
updated README and minor changes
2018-09-19 23:51:01 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
d0806a5759
added missing Load/Store instructions
2018-09-17 12:35:36 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
mariusmonton