95b9685ad9
removed creation of class every CPU loop. It should get better performance
2020-05-28 17:18:50 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
a275e0fa24
better support to IRQs
2019-02-18 13:56:47 +01:00
2c2cf3000b
typos, register definitions
2019-02-11 15:52:48 +01:00
098aebc15d
changed IRQ line to TLM socket
2019-01-22 12:43:05 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
a2a9c95546
Added A Extensions
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Added SFENCE instruction
2018-12-12 18:14:35 +01:00
d449ea5502
adding M extensions to simulator
2018-11-12 17:41:17 +01:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
08044ac626
* Instruction: changed name to accessors
...
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
a5773202e1
renamed RISC_V_execute to Execute
2018-09-21 13:05:42 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón