1babf6cb88
added sc_stop at the end of the simulation to call destructors
2019-09-08 11:41:30 +02:00
d42d67b991
DMI access added (if available)
2019-03-28 22:52:36 +01:00
e31eae3f9e
added command line arguments
2019-02-12 14:08:40 +01:00
a87743b92d
minor changes
2019-02-11 15:54:13 +01:00
098aebc15d
changed IRQ line to TLM socket
2019-01-22 12:43:05 +01:00
a4a1be7386
IRQ implemented
2019-01-13 01:30:49 +01:00
1b93e7f569
added time management and cycle counters
2018-11-25 12:07:08 +01:00
afbf317941
updated documentation
2018-09-21 11:23:31 +02:00
8e8418e3e2
Better logging output
2018-09-20 12:21:15 +02:00
7910a061bc
updated README and minor changes
2018-09-19 23:51:01 +02:00
8dcbf09589
Lot of changes:
...
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
1c9bfe8c60
Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 12:21:26 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón