Màrius Montón
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dd847804c0
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Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
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2019-07-12 17:50:20 +02:00 |
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Màrius Montón
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30e81424ee
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added coverage
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2019-07-12 17:50:07 +02:00 |
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Màrius Montón
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32c9c6c6a5
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Update README.md
typos
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2019-06-22 17:07:34 +02:00 |
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Màrius Montón
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45c1548971
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Update README.md
add how to compile cross compiler for riscv32
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2019-06-22 16:31:06 +02:00 |
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mariusmonton
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f140f5118f
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update how to work with assembly files
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2019-06-09 21:19:47 +02:00 |
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mariusmonton
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1d1c1b0931
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added memory map
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2019-04-10 11:16:14 +02:00 |
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mariusmonton
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471d2c045f
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Merge branch 'master' of https://github.com/mariusmm/RISC-V-TLM
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2019-03-28 22:53:53 +01:00 |
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mariusmonton
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d42d67b991
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DMI access added (if available)
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2019-03-28 22:52:36 +01:00 |
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Màrius Montón
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0a5938a13f
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Update issue templates
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2019-02-21 13:27:37 +01:00 |
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mariusmonton
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24a27f39fe
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another test, long loop for long tests
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2019-02-18 23:28:46 +01:00 |
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mariusmonton
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5ad8ced434
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better log for CSRRW instruction
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2019-02-18 13:57:24 +01:00 |
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mariusmonton
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9d89f847a0
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better dockerfile style
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2019-02-18 13:57:02 +01:00 |
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mariusmonton
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a275e0fa24
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better support to IRQs
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2019-02-18 13:56:47 +01:00 |
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mariusmonton
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a91e590d6d
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other usage of docker image
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2019-02-15 14:30:12 +01:00 |
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mariusmonton
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e31eae3f9e
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added command line arguments
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2019-02-12 14:08:40 +01:00 |
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mariusmonton
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1d4c3ec553
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removed unused code
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2019-02-12 11:40:25 +01:00 |
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mariusmonton
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492cfd61e9
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better extension enumeration
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2019-02-12 11:39:15 +01:00 |
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mariusmonton
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111bf08297
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added ISR register to vPortSetupTimer() function
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2019-02-11 20:36:16 +01:00 |
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mariusmonton
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d62892e3dc
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minor changes, better code
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2019-02-11 20:26:23 +01:00 |
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mariusmonton
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6f8cc9ded6
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updated with FreeRTOS port
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2019-02-11 20:16:32 +01:00 |
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mariusmonton
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1c50b22c27
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FreeRTOS portable files for this simulator
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2019-02-11 20:12:30 +01:00 |
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mariusmonton
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a87743b92d
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minor changes
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2019-02-11 15:54:13 +01:00 |
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mariusmonton
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2c93492ab1
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enhanced IRQ support
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2019-02-11 15:54:02 +01:00 |
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mariusmonton
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2c2cf3000b
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typos, register definitions
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2019-02-11 15:52:48 +01:00 |
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mariusmonton
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6c0d2708a8
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error in docker doc
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2019-02-07 22:41:14 +01:00 |
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mariusmonton
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23f12f3daf
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default all: option
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2019-02-06 19:14:23 +01:00 |
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mariusmonton
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c00b1582d9
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TOC
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2019-02-04 13:16:50 +01:00 |
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mariusmonton
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6ea7f7a062
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updated docker information
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2019-02-03 21:46:38 +01:00 |
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mariusmonton
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50147b4762
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Added Docker container
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2019-02-03 12:05:06 +01:00 |
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mariusmonton
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a8943a111f
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enable interrupts writing to mstatus
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2019-01-22 19:31:13 +01:00 |
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mariusmonton
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fa3b178f79
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update instruction/second
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2019-01-22 18:34:48 +01:00 |
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mariusmonton
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4c89c48fb0
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removed SP init, moved to CPU module
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2019-01-22 18:30:09 +01:00 |
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mariusmonton
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d6f774eaea
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Timer module test
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2019-01-22 18:29:12 +01:00 |
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mariusmonton
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e9ef03890f
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fixed ISR memory alignement
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2019-01-22 13:26:41 +01:00 |
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mariusmonton
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d83a15eec5
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change log level
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2019-01-22 12:47:54 +01:00 |
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mariusmonton
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098aebc15d
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changed IRQ line to TLM socket
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2019-01-22 12:43:05 +01:00 |
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mariusmonton
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0c25abdb00
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Fixed bug
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2019-01-22 12:33:32 +01:00 |
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mariusmonton
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7c263419a8
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documentation
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2019-01-13 18:39:35 +01:00 |
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mariusmonton
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64030a7cc3
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fixed Makefile errors
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2019-01-13 18:20:02 +01:00 |
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mariusmonton
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52953bc8de
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updated with Timer module
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2019-01-13 18:12:51 +01:00 |
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mariusmonton
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3316575820
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updated
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2019-01-13 01:36:38 +01:00 |
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mariusmonton
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d875dc2cd3
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comparator value explained
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2019-01-13 01:33:28 +01:00 |
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mariusmonton
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a4a1be7386
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IRQ implemented
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2019-01-13 01:30:49 +01:00 |
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mariusmonton
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6c3b4347a8
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link fixed
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2019-01-10 15:02:41 +01:00 |
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mariusmonton
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2db8092a04
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update
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2019-01-10 14:58:27 +01:00 |
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mariusmonton
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f1f98faf13
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updates
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2019-01-09 23:06:35 +01:00 |
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mariusmonton
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532d9f7c85
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fixed compiling options
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2019-01-09 23:03:08 +01:00 |
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mariusmonton
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9a7e7abeb0
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Better logs
Fixed some bugs
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2019-01-01 21:11:34 +01:00 |
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mariusmonton
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5c905cb5ca
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better MISA CSR register support
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2018-12-12 18:15:44 +01:00 |
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mariusmonton
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93fe2237b4
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better support to hex file
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2018-12-12 18:15:21 +01:00 |