192 lines
6.3 KiB
Markdown
192 lines
6.3 KiB
Markdown
# Another RISC-V ISA simulator.
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**This code is suitable to hard refactor at any time**
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This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
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It supports RV32IMCA Instruction set by now.
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[](https://travis-ci.org/mariusmm/RISC-V-TLM)
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[](https://www.codacy.com/app/mariusmm/RISC-V-TLM?utm_source=github.com&utm_medium=referral&utm_content=mariusmm/RISC-V-TLM&utm_campaign=Badge_Grade)
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[](https://github.com/mariusmm/RISC-V-TLM/blob/master/LICENSE)
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[](https://twitter.com/mariusmonton)
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---
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Table of Contents
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=================
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<!--ts-->
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* [Another RISC-V ISA simulator.](#another-risc-v-isa-simulator)
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* [Description](#description)
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* [Structure](#structure)
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* [TODO](#todo)
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* [Compile](#compile)
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* [Docker container](#docker-container)
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* [How to use Docker](#how-to-use-docker)
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* [Test](#test)
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* [C code](#c-code)
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* [Documentation](#documentation)
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* [Contribute](#contribute)
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* [License](#license)
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<!-- Added by: marius, at: 2019-02-04T13:16+01:00 -->
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<!--te-->
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## Description
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Brief description of the modules:
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* CPU: Top entity that includes all other modules.
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* Memory: Memory highly based on TLM-2 example with read file capability
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* Registers: Implements the register file, PC register & CSR registers
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* Execute: Executes ISA instructions
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* Executes C instruction extensions
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* Executes M instruction extensions
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* Executes A instruction extensions
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* Instruction: Decodes instruction and acces to any instruction field
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* C_Instruction: Decodes Compressed instructions (C extension)
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* M_Instruction: Decodes Multiplication and Division instructions (M extension)
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* A_Instruction: Decodes Atomic instructions (A extension)
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* Simulator: Top-level entity that builds & starts the simulation
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* BusCtrl: Simple bus manager
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* Trace: Simple trace peripheral
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* Timer: Simple IRQ programable real-time counter peripheral
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Helper classes:
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* Performance: Performance indicators stores here (singleton class)
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* Log: Log class to log them all (singleton class)
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Current performance is about 1.500.000 instructions / sec in a Intel Core
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i5-5200<span>@</span>2.2Ghz
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### Structure
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## TODO
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This is a preliminar and incomplete version.
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Task to do:
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- [x] Implement all missing instructions (Execute)
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- [x] Implement CSRs (where/how?)
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- [ ] Add full support to read file with memory contents (to memory.h)
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- [ ] .elf files
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- [x] .hex files (only partial .hex support)
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- [ ] Connect some TLM peripherals
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- [x] Debug module similiar to ARM's ITM
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- [ ] Some standard UART model
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- [ ] ...
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- [ ] Implement interrupts
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- [x] implement timer (mtimecmp) & timer interrupt
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- [ ] generic IRQ comtroller
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- [x] Test, test, test & test. I'm sure there are a ~~lot of~~ some bugs in the code
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- [x] riscv-test almost complete (see [Test](https://github.com/mariusmm/RISC-V-TLM/wiki/Tests))
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- [ ] riscv-compliance WiP
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* Improve structure and modules hierarchy
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* Add 64 & 128 bits architecture (RV64I, RV128I)
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## Compile
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In order to compile the project you need SystemC-2.3.2 installed in your system.
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Just change SYSTEMC path in Makefile.
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```
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$ make
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```
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Then, you need to modifiy your LD_LIBRARY_PATH environtment variable to add
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path systemc library. In my case:
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```
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$ export LD_LIBRARY_PATH=/home/marius/Work/RiscV/code/systemc-2.3.2/lib-linux64
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```
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And then you can execute the simulator:
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```
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$ ./RISCV_TLM asm/BasicLoop.hex
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```
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## Docker container
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There is a Docker container available with the latest release at https://hub.docker.com/r/mariusmm/riscv-tlm.
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This container has RISCV-TLM already build at /usr/src/riscv64/RISCV-TLM directory.
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### How to use Docker
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```
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$ docker pull mariusmm/riscv-tlm
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$ docker run -v <localfiles>:/tmp -it mariusmm/riscv-tlm /bin/bash
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# cd /usr/src/riscv64/RISCV_TLM/
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# ./RISCV_TLM /tmp/<your_hex_file>
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```
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I'm using docker image [zmors/riscv_gcc](https://hub.docker.com/r/zmors/riscv_gcc) to have a cross-compiler, I'm using both docker images this way:
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```
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console1:
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$ docker run -v /tmp:/PRJ -it zmors/riscv_gcc:1 bash
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# cd /PRJ/func3
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# make
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console2:
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$ docker run -v /tmp:/tmp -it mariusmm/riscv-tlm /bin/bash
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# cd /usr/src/riscv64/RISC-V-TLM/
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# ./RISCV-TLM /tmp/file.hex
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...
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```
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Performance is not affected by running the simulator inside the container
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## Test
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See [Test page](Test) for more information.
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In the asm directory there are some basic assembly examples.
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I "compile" one file with the follwing command:
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```
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$ cd asm
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$ riscv32-unknown-elf-as EternalLoop.asm -o EternalLoop.o
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$ riscv32-unknown-elf-ld -T ../my_linker_script.ld EternalLoop.o -o EternalLoop.elf
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$ riscv32-unknown-elf-objcopy -O ihex EternalLoop.elf EternalLoop.hex
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$ cd ..
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$ ./RISCV_SCTLM asm/EternalLoop.hex
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```
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This example needs that you hit Ctr+C to stop execution.
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### C code
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The C directory contains simple examples in C. Each directory contains
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an example, to compile it just:
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```
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$ make
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```
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and then execute the .hex file like the example before.
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## Documentation
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The code is documented using doxygen. In the doc folder there is a Doxygen.cfg
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file ready to be used.
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## Contribute
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There are several ways to contribute to this project:
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* Test
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* Pull request are welcome (see TODO list)
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* Good documentation
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## License
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Copyright (C) 2018 Màrius Montón ([\@mariusmonton](https://twitter.com/mariusmonton/))
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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