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Add nitefury_pcie_xdma_ddr.
2025-05-10 13:29:27 +08:00
{
"design": {
"design_info": {
"boundary_crc": "0x8F1AA258A84BB33F",
"device": "xc7k480tffg1156-2L",
Update nitefury_pcie_xdma_ddr/project.
2025-05-12 02:06:47 +08:00
"gen_directory": "../../../build/my_project.gen/sources_1",
Add nitefury_pcie_xdma_ddr.
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"name": "Top",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2022.2",
"validated": "true"
},
"design_tree": {
"xdma_1": "",
"axi_interconnect_0": {
"xbar": "",
"s00_couplers": {
"auto_us": ""
},
"m00_couplers": {
"auto_cc": "",
"auto_ds": "",
"auto_pc": ""
},
"m01_couplers": {
"auto_cc": ""
},
"m02_couplers": {
"auto_cc": "",
"auto_ds": "",
"auto_pc": ""
},
"m03_couplers": {
"auto_cc": ""
},
"m04_couplers": {
"auto_ds": ""
}
},
"mig_7series_1": "",
"util_vector_logic_1": "",
"xlconstant_0": "",
"xlconstant_2": "",
"util_ds_buf_0": "",
"util_vector_logic_2": "",
"axi_bram_ctrl_0": "",
"blk_mem_gen_0": ""
},
"interface_ports": {
"pcie_clkin": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000"
}
},
"port_maps": {
"CLK_P": {
"physical_name": "pcie_clkin_clk_p",
"direction": "I",
"left": "0",
"right": "0"
},
"CLK_N": {
"physical_name": "pcie_clkin_clk_n",
"direction": "I",
"left": "0",
"right": "0"
}
}
},
"pcie_mgt_0": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:pcie_7x_mgt:1.0",
"vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
"port_maps": {
"rxn": {
"physical_name": "pcie_mgt_0_rxn",
"direction": "I",
"left": "0",
"right": "0"
},
"rxp": {
"physical_name": "pcie_mgt_0_rxp",
"direction": "I",
"left": "0",
"right": "0"
},
"txn": {
"physical_name": "pcie_mgt_0_txn",
"direction": "O",
"left": "0",
"right": "0"
},
"txp": {
"physical_name": "pcie_mgt_0_txp",
"direction": "O",
"left": "0",
"right": "0"
}
}
},
"C0_DDR3_0": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
}
},
"port_maps": {
"DQ": {
"physical_name": "C0_DDR3_0_dq",
"direction": "IO",
"left": "71",
"right": "0"
},
"DQS_P": {
"physical_name": "C0_DDR3_0_dqs_p",
"direction": "IO",
"left": "8",
"right": "0"
},
"DQS_N": {
"physical_name": "C0_DDR3_0_dqs_n",
"direction": "IO",
"left": "8",
"right": "0"
},
"ADDR": {
"physical_name": "C0_DDR3_0_addr",
"direction": "O",
"left": "14",
"right": "0"
},
"BA": {
"physical_name": "C0_DDR3_0_ba",
"direction": "O",
"left": "2",
"right": "0"
},
"RAS_N": {
"physical_name": "C0_DDR3_0_ras_n",
"direction": "O"
},
"CAS_N": {
"physical_name": "C0_DDR3_0_cas_n",
"direction": "O"
},
"WE_N": {
"physical_name": "C0_DDR3_0_we_n",
"direction": "O"
},
"RESET_N": {
"physical_name": "C0_DDR3_0_reset_n",
"direction": "O"
},
"CK_P": {
"physical_name": "C0_DDR3_0_ck_p",
"direction": "O",
"left": "0",
"right": "0"
},
"CK_N": {
"physical_name": "C0_DDR3_0_ck_n",
"direction": "O",
"left": "0",
"right": "0"
},
"CKE": {
"physical_name": "C0_DDR3_0_cke",
"direction": "O",
"left": "0",
"right": "0"
},
"CS_N": {
"physical_name": "C0_DDR3_0_cs_n",
"direction": "O",
"left": "0",
"right": "0"
},
"ODT": {
"physical_name": "C0_DDR3_0_odt",
"direction": "O",
"left": "0",
"right": "0"
}
}
},
"C1_DDR3_0": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
"parameters": {
"AXI_ARBITRATION_SCHEME": {
"value": "TDM",
"value_src": "default"
},
"BURST_LENGTH": {
"value": "8",
"value_src": "default"
},
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"CAS_LATENCY": {
"value": "11",
"value_src": "default"
},
"CAS_WRITE_LATENCY": {
"value": "11",
"value_src": "default"
},
"CS_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_MASK_ENABLED": {
"value": "true",
"value_src": "default"
},
"DATA_WIDTH": {
"value": "8",
"value_src": "default"
},
"MEMORY_TYPE": {
"value": "COMPONENTS",
"value_src": "default"
},
"MEM_ADDR_MAP": {
"value": "ROW_COLUMN_BANK",
"value_src": "default"
},
"SLOT": {
"value": "Single",
"value_src": "default"
},
"TIMEPERIOD_PS": {
"value": "1250",
"value_src": "default"
}
},
"port_maps": {
"DQ": {
"physical_name": "C1_DDR3_0_dq",
"direction": "IO",
"left": "71",
"right": "0"
},
"DQS_P": {
"physical_name": "C1_DDR3_0_dqs_p",
"direction": "IO",
"left": "8",
"right": "0"
},
"DQS_N": {
"physical_name": "C1_DDR3_0_dqs_n",
"direction": "IO",
"left": "8",
"right": "0"
},
"ADDR": {
"physical_name": "C1_DDR3_0_addr",
"direction": "O",
"left": "14",
"right": "0"
},
"BA": {
"physical_name": "C1_DDR3_0_ba",
"direction": "O",
"left": "2",
"right": "0"
},
"RAS_N": {
"physical_name": "C1_DDR3_0_ras_n",
"direction": "O"
},
"CAS_N": {
"physical_name": "C1_DDR3_0_cas_n",
"direction": "O"
},
"WE_N": {
"physical_name": "C1_DDR3_0_we_n",
"direction": "O"
},
"RESET_N": {
"physical_name": "C1_DDR3_0_reset_n",
"direction": "O"
},
"CK_P": {
"physical_name": "C1_DDR3_0_ck_p",
"direction": "O",
"left": "0",
"right": "0"
},
"CK_N": {
"physical_name": "C1_DDR3_0_ck_n",
"direction": "O",
"left": "0",
"right": "0"
},
"CKE": {
"physical_name": "C1_DDR3_0_cke",
"direction": "O",
"left": "0",
"right": "0"
},
"CS_N": {
"physical_name": "C1_DDR3_0_cs_n",
"direction": "O",
"left": "0",
"right": "0"
},
"ODT": {
"physical_name": "C1_DDR3_0_odt",
"direction": "O",
"left": "0",
"right": "0"
}
}
},
"C0_SYS_CLK_0": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
}
},
"port_maps": {
"CLK_P": {
"physical_name": "C0_SYS_CLK_0_clk_p",
"direction": "I"
},
"CLK_N": {
"physical_name": "C0_SYS_CLK_0_clk_n",
"direction": "I"
}
}
},
"C1_SYS_CLK_0": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0",
"vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
"parameters": {
"CAN_DEBUG": {
"value": "false",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "default"
}
},
"port_maps": {
"CLK_P": {
"physical_name": "C1_SYS_CLK_0_clk_p",
"direction": "I"
},
"CLK_N": {
"physical_name": "C1_SYS_CLK_0_clk_n",
"direction": "I"
}
}
}
},
"ports": {
"pci_reset": {
"type": "rst",
"direction": "I",
"parameters": {
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"POLARITY": {
"value": "ACTIVE_LOW"
}
}
},
"user_lnk_up_0": {
"direction": "O"
}
},
"components": {
"xdma_1": {
"vlnv": "xilinx.com:ip:xdma:4.1",
Update nitefury_pcie_xdma_ddr/project.
2025-05-12 02:06:47 +08:00
"xci_name": "Top_xdma_1_1",
"xci_path": "ip/Top_xdma_1_1/Top_xdma_1_1.xci",
Add nitefury_pcie_xdma_ddr.
2025-05-10 13:29:27 +08:00
"inst_hier_path": "xdma_1",
"parameters": {
"pl_link_cap_max_link_speed": {
"value": "5.0_GT/s"
}
},
"interface_ports": {
"M_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Master",
"address_space_ref": "M_AXI",
"base_address": {
"minimum": "0x00000000",
"maximum": "0xFFFFFFFFFFFFFFFF",
"width": "64"
}
}
},
"addressing": {
"address_spaces": {
"M_AXI": {
"range": "16E",
"width": "64"
}
}
}
},
"axi_interconnect_0": {
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
"xci_path": "ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci",
"inst_hier_path": "axi_interconnect_0",
"xci_name": "Top_axi_interconnect_0_0",
"parameters": {
"NUM_MI": {
"value": "5"
},
"NUM_SI": {
"value": "1"
}
},
"interface_ports": {
"S00_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M00_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M01_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M02_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M03_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M04_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_RESET": {
"value": "ARESETN"
}
}
},
"ARESETN": {
"type": "rst",
"direction": "I"
},
"S00_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S00_AXI"
},
"ASSOCIATED_RESET": {
"value": "S00_ARESETN"
}
}
},
"S00_ARESETN": {
"type": "rst",
"direction": "I"
},
"M00_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M00_AXI"
},
"ASSOCIATED_RESET": {
"value": "M00_ARESETN"
}
}
},
"M00_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"M01_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M01_AXI"
},
"ASSOCIATED_RESET": {
"value": "M01_ARESETN"
}
}
},
"M01_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"M02_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M02_AXI"
},
"ASSOCIATED_RESET": {
"value": "M02_ARESETN"
}
}
},
"M02_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"M03_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M03_AXI"
},
"ASSOCIATED_RESET": {
"value": "M03_ARESETN"
}
}
},
"M03_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"M04_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M04_AXI"
},
"ASSOCIATED_RESET": {
"value": "M04_ARESETN"
}
}
},
"M04_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"xbar": {
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
"xci_name": "Top_xbar_0",
"xci_path": "ip/Top_xbar_0/Top_xbar_0.xci",
"inst_hier_path": "axi_interconnect_0/xbar",
"parameters": {
"NUM_MI": {
"value": "5"
},
"NUM_SI": {
"value": "1"
},
"STRATEGY": {
"value": "0"
}
},
"interface_ports": {
"S00_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M00_AXI",
"M01_AXI",
"M02_AXI",
"M03_AXI",
"M04_AXI"
]
}
}
},
"s00_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_us": {
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
"xci_name": "Top_auto_us_0",
"xci_path": "ip/Top_auto_us_0/Top_auto_us_0.xci",
"inst_hier_path": "axi_interconnect_0/s00_couplers/auto_us",
"parameters": {
"MI_DATA_WIDTH": {
"value": "512"
},
"SI_DATA_WIDTH": {
"value": "64"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_us_to_s00_couplers": {
"interface_ports": [
"M_AXI",
"auto_us/M_AXI"
]
},
"s00_couplers_to_auto_us": {
"interface_ports": [
"S_AXI",
"auto_us/S_AXI"
]
}
},
"nets": {
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_us/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_us/s_axi_aresetn"
]
}
}
},
"m00_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_cc": {
"vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
"xci_name": "Top_auto_cc_0",
"xci_path": "ip/Top_auto_cc_0/Top_auto_cc_0.xci",
"inst_hier_path": "axi_interconnect_0/m00_couplers/auto_cc",
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
},
"auto_ds": {
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
"xci_name": "Top_auto_ds_0",
"xci_path": "ip/Top_auto_ds_0/Top_auto_ds_0.xci",
"inst_hier_path": "axi_interconnect_0/m00_couplers/auto_ds",
"parameters": {
"MI_DATA_WIDTH": {
"value": "32"
},
"SI_DATA_WIDTH": {
"value": "512"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
},
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"xci_name": "Top_auto_pc_0",
"xci_path": "ip/Top_auto_pc_0/Top_auto_pc_0.xci",
"inst_hier_path": "axi_interconnect_0/m00_couplers/auto_pc",
"parameters": {
"MI_PROTOCOL": {
"value": "AXI4LITE"
},
"SI_PROTOCOL": {
"value": "AXI4"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_cc_to_auto_ds": {
"interface_ports": [
"auto_cc/M_AXI",
"auto_ds/S_AXI"
]
},
"auto_ds_to_auto_pc": {
"interface_ports": [
"auto_ds/M_AXI",
"auto_pc/S_AXI"
]
},
"auto_pc_to_m00_couplers": {
"interface_ports": [
"M_AXI",
"auto_pc/M_AXI"
]
},
"m00_couplers_to_auto_cc": {
"interface_ports": [
"S_AXI",
"auto_cc/S_AXI"
]
}
},
"nets": {
"M_ACLK_1": {
"ports": [
"M_ACLK",
"auto_cc/m_axi_aclk",
"auto_ds/s_axi_aclk",
"auto_pc/aclk"
]
},
"M_ARESETN_1": {
"ports": [
"M_ARESETN",
"auto_cc/m_axi_aresetn",
"auto_ds/s_axi_aresetn",
"auto_pc/aresetn"
]
},
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_cc/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_cc/s_axi_aresetn"
]
}
}
},
"m01_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_cc": {
"vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
"xci_name": "Top_auto_cc_1",
"xci_path": "ip/Top_auto_cc_1/Top_auto_cc_1.xci",
"inst_hier_path": "axi_interconnect_0/m01_couplers/auto_cc",
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_cc_to_m01_couplers": {
"interface_ports": [
"M_AXI",
"auto_cc/M_AXI"
]
},
"m01_couplers_to_auto_cc": {
"interface_ports": [
"S_AXI",
"auto_cc/S_AXI"
]
}
},
"nets": {
"M_ACLK_1": {
"ports": [
"M_ACLK",
"auto_cc/m_axi_aclk"
]
},
"M_ARESETN_1": {
"ports": [
"M_ARESETN",
"auto_cc/m_axi_aresetn"
]
},
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_cc/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_cc/s_axi_aresetn"
]
}
}
},
"m02_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_cc": {
"vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
"xci_name": "Top_auto_cc_2",
"xci_path": "ip/Top_auto_cc_2/Top_auto_cc_2.xci",
"inst_hier_path": "axi_interconnect_0/m02_couplers/auto_cc",
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
},
"auto_ds": {
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
"xci_name": "Top_auto_ds_1",
"xci_path": "ip/Top_auto_ds_1/Top_auto_ds_1.xci",
"inst_hier_path": "axi_interconnect_0/m02_couplers/auto_ds",
"parameters": {
"MI_DATA_WIDTH": {
"value": "32"
},
"SI_DATA_WIDTH": {
"value": "512"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
},
"auto_pc": {
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
"xci_name": "Top_auto_pc_1",
"xci_path": "ip/Top_auto_pc_1/Top_auto_pc_1.xci",
"inst_hier_path": "axi_interconnect_0/m02_couplers/auto_pc",
"parameters": {
"MI_PROTOCOL": {
"value": "AXI4LITE"
},
"SI_PROTOCOL": {
"value": "AXI4"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_cc_to_auto_ds": {
"interface_ports": [
"auto_cc/M_AXI",
"auto_ds/S_AXI"
]
},
"auto_ds_to_auto_pc": {
"interface_ports": [
"auto_ds/M_AXI",
"auto_pc/S_AXI"
]
},
"auto_pc_to_m02_couplers": {
"interface_ports": [
"M_AXI",
"auto_pc/M_AXI"
]
},
"m02_couplers_to_auto_cc": {
"interface_ports": [
"S_AXI",
"auto_cc/S_AXI"
]
}
},
"nets": {
"M_ACLK_1": {
"ports": [
"M_ACLK",
"auto_cc/m_axi_aclk",
"auto_ds/s_axi_aclk",
"auto_pc/aclk"
]
},
"M_ARESETN_1": {
"ports": [
"M_ARESETN",
"auto_cc/m_axi_aresetn",
"auto_ds/s_axi_aresetn",
"auto_pc/aresetn"
]
},
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_cc/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_cc/s_axi_aresetn"
]
}
}
},
"m03_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I",
"left": "7",
"right": "0"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_cc": {
"vlnv": "xilinx.com:ip:axi_clock_converter:2.1",
"xci_name": "Top_auto_cc_3",
"xci_path": "ip/Top_auto_cc_3/Top_auto_cc_3.xci",
"inst_hier_path": "axi_interconnect_0/m03_couplers/auto_cc",
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_cc_to_m03_couplers": {
"interface_ports": [
"M_AXI",
"auto_cc/M_AXI"
]
},
"m03_couplers_to_auto_cc": {
"interface_ports": [
"S_AXI",
"auto_cc/S_AXI"
]
}
},
"nets": {
"M_ACLK_1": {
"ports": [
"M_ACLK",
"auto_cc/m_axi_aclk"
]
},
"M_ARESETN_1": {
"ports": [
"M_ARESETN",
"auto_cc/m_axi_aresetn"
]
},
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_cc/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_cc/s_axi_aresetn"
]
}
}
},
"m04_couplers": {
"interface_ports": {
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
"M_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXI"
},
"ASSOCIATED_RESET": {
"value": "M_ARESETN"
}
}
},
"M_ARESETN": {
"type": "rst",
"direction": "I"
},
"S_ACLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI"
},
"ASSOCIATED_RESET": {
"value": "S_ARESETN"
}
}
},
"S_ARESETN": {
"type": "rst",
"direction": "I"
}
},
"components": {
"auto_ds": {
"vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1",
"xci_name": "Top_auto_ds_2",
"xci_path": "ip/Top_auto_ds_2/Top_auto_ds_2.xci",
"inst_hier_path": "axi_interconnect_0/m04_couplers/auto_ds",
"parameters": {
"MI_DATA_WIDTH": {
"value": "32"
},
"SI_DATA_WIDTH": {
"value": "512"
}
},
"interface_ports": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Slave",
"bridges": [
"M_AXI"
]
}
}
}
},
"interface_nets": {
"auto_ds_to_m04_couplers": {
"interface_ports": [
"M_AXI",
"auto_ds/M_AXI"
]
},
"m04_couplers_to_auto_ds": {
"interface_ports": [
"S_AXI",
"auto_ds/S_AXI"
]
}
},
"nets": {
"S_ACLK_1": {
"ports": [
"S_ACLK",
"auto_ds/s_axi_aclk"
]
},
"S_ARESETN_1": {
"ports": [
"S_ARESETN",
"auto_ds/s_axi_aresetn"
]
}
}
}
},
"interface_nets": {
"axi_interconnect_0_to_s00_couplers": {
"interface_ports": [
"S00_AXI",
"s00_couplers/S_AXI"
]
},
"m00_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M00_AXI",
"m00_couplers/M_AXI"
]
},
"m01_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M01_AXI",
"m01_couplers/M_AXI"
]
},
"m02_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M02_AXI",
"m02_couplers/M_AXI"
]
},
"m03_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M03_AXI",
"m03_couplers/M_AXI"
]
},
"m04_couplers_to_axi_interconnect_0": {
"interface_ports": [
"M04_AXI",
"m04_couplers/M_AXI"
]
},
"s00_couplers_to_xbar": {
"interface_ports": [
"s00_couplers/M_AXI",
"xbar/S00_AXI"
]
},
"xbar_to_m00_couplers": {
"interface_ports": [
"xbar/M00_AXI",
"m00_couplers/S_AXI"
]
},
"xbar_to_m01_couplers": {
"interface_ports": [
"xbar/M01_AXI",
"m01_couplers/S_AXI"
]
},
"xbar_to_m02_couplers": {
"interface_ports": [
"xbar/M02_AXI",
"m02_couplers/S_AXI"
]
},
"xbar_to_m03_couplers": {
"interface_ports": [
"xbar/M03_AXI",
"m03_couplers/S_AXI"
]
},
"xbar_to_m04_couplers": {
"interface_ports": [
"xbar/M04_AXI",
"m04_couplers/S_AXI"
]
}
},
"nets": {
"M00_ACLK_1": {
"ports": [
"M00_ACLK",
"m00_couplers/M_ACLK"
]
},
"M00_ARESETN_1": {
"ports": [
"M00_ARESETN",
"m00_couplers/M_ARESETN"
]
},
"M01_ACLK_1": {
"ports": [
"M01_ACLK",
"m01_couplers/M_ACLK"
]
},
"M01_ARESETN_1": {
"ports": [
"M01_ARESETN",
"m01_couplers/M_ARESETN"
]
},
"M02_ACLK_1": {
"ports": [
"M02_ACLK",
"m02_couplers/M_ACLK"
]
},
"M02_ARESETN_1": {
"ports": [
"M02_ARESETN",
"m02_couplers/M_ARESETN"
]
},
"M03_ACLK_1": {
"ports": [
"M03_ACLK",
"m03_couplers/M_ACLK"
]
},
"M03_ARESETN_1": {
"ports": [
"M03_ARESETN",
"m03_couplers/M_ARESETN"
]
},
"M04_ACLK_1": {
"ports": [
"M04_ACLK",
"m04_couplers/M_ACLK"
]
},
"M04_ARESETN_1": {
"ports": [
"M04_ARESETN",
"m04_couplers/M_ARESETN"
]
},
"S00_ACLK_1": {
"ports": [
"S00_ACLK",
"s00_couplers/S_ACLK"
]
},
"S00_ARESETN_1": {
"ports": [
"S00_ARESETN",
"s00_couplers/S_ARESETN"
]
},
"axi_interconnect_0_ACLK_net": {
"ports": [
"ACLK",
"xbar/aclk",
"s00_couplers/M_ACLK",
"m00_couplers/S_ACLK",
"m01_couplers/S_ACLK",
"m02_couplers/S_ACLK",
"m03_couplers/S_ACLK",
"m04_couplers/S_ACLK"
]
},
"axi_interconnect_0_ARESETN_net": {
"ports": [
"ARESETN",
"xbar/aresetn",
"s00_couplers/M_ARESETN",
"m00_couplers/S_ARESETN",
"m01_couplers/S_ARESETN",
"m02_couplers/S_ARESETN",
"m03_couplers/S_ARESETN",
"m04_couplers/S_ARESETN"
]
}
}
},
"mig_7series_1": {
"vlnv": "xilinx.com:ip:mig_7series:4.2",
"xci_name": "Top_mig_7series_1_0",
"xci_path": "ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci",
"inst_hier_path": "mig_7series_1",
"parameters": {
"BOARD_MIG_PARAM": {
"value": "Custom"
},
"RESET_BOARD_INTERFACE": {
"value": "Custom"
},
"XML_INPUT_FILE": {
"value": "mig_b.prj"
}
}
},
"util_vector_logic_1": {
"vlnv": "xilinx.com:ip:util_vector_logic:2.0",
"xci_name": "Top_util_vector_logic_1_3",
"xci_path": "ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci",
"inst_hier_path": "util_vector_logic_1",
"parameters": {
"C_OPERATION": {
"value": "not"
}
}
},
"xlconstant_0": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
Update nitefury_pcie_xdma_ddr/project.
2025-05-12 02:06:47 +08:00
"xci_name": "Top_xlconstant_0_1",
"xci_path": "ip/Top_xlconstant_0_1/Top_xlconstant_0_1.xci",
Add nitefury_pcie_xdma_ddr.
2025-05-10 13:29:27 +08:00
"inst_hier_path": "xlconstant_0"
},
"xlconstant_2": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"xci_name": "Top_xlconstant_2_0",
"xci_path": "ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci",
"inst_hier_path": "xlconstant_2"
},
"util_ds_buf_0": {
"vlnv": "xilinx.com:ip:util_ds_buf:2.2",
"xci_name": "Top_util_ds_buf_0_0",
"xci_path": "ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci",
"inst_hier_path": "util_ds_buf_0",
"parameters": {
"C_BUF_TYPE": {
"value": "IBUFDSGTE"
}
}
},
"util_vector_logic_2": {
"vlnv": "xilinx.com:ip:util_vector_logic:2.0",
"xci_name": "Top_util_vector_logic_1_4",
"xci_path": "ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci",
"inst_hier_path": "util_vector_logic_2",
"parameters": {
"C_OPERATION": {
"value": "not"
}
}
},
"axi_bram_ctrl_0": {
"vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
"xci_name": "Top_axi_bram_ctrl_0_0",
"xci_path": "ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci",
"inst_hier_path": "axi_bram_ctrl_0",
"parameters": {
"SINGLE_PORT_BRAM": {
"value": "1"
}
}
},
"blk_mem_gen_0": {
"vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
"xci_name": "Top_blk_mem_gen_0_0",
"xci_path": "ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci",
"inst_hier_path": "blk_mem_gen_0"
}
},
"interface_nets": {
"C0_SYS_CLK_0_1": {
"interface_ports": [
"C0_SYS_CLK_0",
"mig_7series_1/C0_SYS_CLK"
]
},
"C1_SYS_CLK_0_1": {
"interface_ports": [
"C1_SYS_CLK_0",
"mig_7series_1/C1_SYS_CLK"
]
},
"S00_AXI_1": {
"interface_ports": [
"axi_interconnect_0/S00_AXI",
"xdma_1/M_AXI"
]
},
"axi_bram_ctrl_0_BRAM_PORTA": {
"interface_ports": [
"axi_bram_ctrl_0/BRAM_PORTA",
"blk_mem_gen_0/BRAM_PORTA"
]
},
"axi_interconnect_0_M00_AXI": {
"interface_ports": [
"axi_interconnect_0/M00_AXI",
"mig_7series_1/S0_AXI_CTRL"
]
},
"axi_interconnect_0_M01_AXI": {
"interface_ports": [
"axi_interconnect_0/M01_AXI",
"mig_7series_1/S0_AXI"
]
},
"axi_interconnect_0_M02_AXI": {
"interface_ports": [
"axi_interconnect_0/M02_AXI",
"mig_7series_1/S1_AXI_CTRL"
]
},
"axi_interconnect_0_M03_AXI": {
"interface_ports": [
"axi_interconnect_0/M03_AXI",
"mig_7series_1/S1_AXI"
]
},
"axi_interconnect_0_M04_AXI": {
"interface_ports": [
"axi_interconnect_0/M04_AXI",
"axi_bram_ctrl_0/S_AXI"
]
},
"mig_7series_1_C0_DDR3": {
"interface_ports": [
"C0_DDR3_0",
"mig_7series_1/C0_DDR3"
]
},
"mig_7series_1_C1_DDR3": {
"interface_ports": [
"C1_DDR3_0",
"mig_7series_1/C1_DDR3"
]
},
"pcie_clkin_1": {
"interface_ports": [
"pcie_clkin",
"util_ds_buf_0/CLK_IN_D"
]
},
"xdma_1_pcie_mgt": {
"interface_ports": [
"pcie_mgt_0",
"xdma_1/pcie_mgt"
]
}
},
"nets": {
"M00_ARESETN_2": {
"ports": [
"util_vector_logic_1/Res",
"axi_interconnect_0/M00_ARESETN",
"axi_interconnect_0/M01_ARESETN"
]
},
"mig_7series_1_c0_ui_clk_sync_rst": {
"ports": [
"mig_7series_1/c0_ui_clk_sync_rst",
"util_vector_logic_1/Op1"
]
},
"mig_7series_1_c1_ui_clk": {
"ports": [
"mig_7series_1/c1_ui_clk",
"axi_interconnect_0/M02_ACLK",
"axi_interconnect_0/M03_ACLK"
]
},
"mig_7series_1_c1_ui_clk_sync_rst": {
"ports": [
"mig_7series_1/c1_ui_clk_sync_rst",
"util_vector_logic_2/Op1"
]
},
"mig_7series_1_ui_clk": {
"ports": [
"mig_7series_1/c0_ui_clk",
"axi_interconnect_0/M00_ACLK",
"axi_interconnect_0/M01_ACLK"
]
},
"pci_reset_1": {
"ports": [
"pci_reset",
"xdma_1/sys_rst_n"
]
},
"util_ds_buf_0_IBUF_OUT": {
"ports": [
"util_ds_buf_0/IBUF_OUT",
"xdma_1/sys_clk"
]
},
"util_vector_logic_2_Res": {
"ports": [
"util_vector_logic_2/Res",
"axi_interconnect_0/M02_ARESETN",
"axi_interconnect_0/M03_ARESETN"
]
},
"xdma_1_axi_aclk": {
"ports": [
"xdma_1/axi_aclk",
"axi_interconnect_0/ACLK",
"axi_interconnect_0/S00_ACLK",
"axi_bram_ctrl_0/s_axi_aclk",
"axi_interconnect_0/M04_ACLK"
]
},
"xdma_1_axi_aresetn": {
"ports": [
"xdma_1/axi_aresetn",
"axi_interconnect_0/S00_ARESETN",
"axi_interconnect_0/ARESETN",
"axi_bram_ctrl_0/s_axi_aresetn",
"axi_interconnect_0/M04_ARESETN"
]
},
"xdma_1_user_lnk_up": {
"ports": [
"xdma_1/user_lnk_up",
"user_lnk_up_0"
]
},
"xlconstant_0_dout": {
"ports": [
"xlconstant_0/dout",
"mig_7series_1/c0_aresetn",
"mig_7series_1/c1_aresetn"
]
},
"xlconstant_2_dout": {
"ports": [
"xlconstant_2/dout",
"mig_7series_1/sys_rst"
]
}
},
"addressing": {
"/xdma_1": {
"address_spaces": {
"M_AXI": {
"segments": {
"SEG_axi_bram_ctrl_0_Mem0": {
"address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
"offset": "0x0000000200000000",
"range": "8K"
},
"SEG_mig_7series_1_c0_memaddr": {
"address_block": "/mig_7series_1/c0_memmap/c0_memaddr",
"offset": "0x0000000080000000",
"range": "2G"
},
"SEG_mig_7series_1_c0_s_axi_ctrl_memaddr": {
"address_block": "/mig_7series_1/c0_s_axi_ctrl_memmap/c0_s_axi_ctrl_memaddr",
"offset": "0x0000000100000000",
"range": "1M"
},
"SEG_mig_7series_1_c1_memaddr": {
"address_block": "/mig_7series_1/c1_memmap/c1_memaddr",
"offset": "0x0000000000000000",
"range": "2G"
},
"SEG_mig_7series_1_c1_s_axi_ctrl_memaddr": {
"address_block": "/mig_7series_1/c1_s_axi_ctrl_memmap/c1_s_axi_ctrl_memaddr",
"offset": "0x0000000100100000",
"range": "1M"
}
}
}
}
}
}
}
}