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Update addr base.

This commit is contained in:
Colin 2025-05-12 23:58:09 +08:00
parent 92d449f72d
commit d4fa8d57d7
4 changed files with 14 additions and 5 deletions
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2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
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@ -244,7 +244,7 @@
"description": "Memory Map for S_AXI", "description": "Memory Map for S_AXI",
"address_blocks": { "address_blocks": {
"Mem0": { "Mem0": {
"base_address": "0", "base_address": "4294967296",
"range": "4096", "range": "4096",
"display_name": "Mem0", "display_name": "Mem0",
"description": "Register Block", "description": "Register Block",

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
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@ -247,7 +247,7 @@
"S_1": { "S_1": {
"address_blocks": { "address_blocks": {
"Mem0": { "Mem0": {
"base_address": "0", "base_address": "4294967296",
"range": "4096", "range": "4096",
"usage": "memory", "usage": "memory",
"access": "read-write", "access": "read-write",

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
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@ -2147,7 +2147,7 @@
"c0_s_axi_ctrl_memmap": { "c0_s_axi_ctrl_memmap": {
"address_blocks": { "address_blocks": {
"c0_s_axi_ctrl_memaddr": { "c0_s_axi_ctrl_memaddr": {
"base_address": "0", "base_address": "4295229440",
"range": "1048576", "range": "1048576",
"usage": "register", "usage": "register",
"access": "read-write" "access": "read-write"
@ -2167,7 +2167,7 @@
"c1_s_axi_ctrl_memmap": { "c1_s_axi_ctrl_memmap": {
"address_blocks": { "address_blocks": {
"c1_s_axi_ctrl_memaddr": { "c1_s_axi_ctrl_memaddr": {
"base_address": "0", "base_address": "4295491584",
"range": "1048576", "range": "1048576",
"usage": "register", "usage": "register",
"access": "read-write" "access": "read-write"
@ -2177,7 +2177,7 @@
"c1_memmap": { "c1_memmap": {
"address_blocks": { "address_blocks": {
"c1_memaddr": { "c1_memaddr": {
"base_address": "0", "base_address": "2147483648",
"range": "2147483648", "range": "2147483648",
"usage": "memory", "usage": "memory",
"access": "read-write" "access": "read-write"

9
nitefury_pcie_xdma_ddr/project/xdma_ddr_prog.tcl Normal file
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@ -0,0 +1,9 @@
if { [ catch { open_hw_manager } ] } { open_hw }
connect_hw_server
open_hw_target
puts [get_hw_devices]
set obj [lindex [get_hw_devices [current_hw_device]] 0]
set_property PROGRAM.FILE ./xdma_ddr.bit $obj
program_hw_devices $obj