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Update nitefury_pcie_xdma_ddr/project

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Colin 2025-05-11 16:27:43 +08:00
parent d1ce19df57
commit e8cf5bf65e
15 changed files with 150 additions and 170 deletions
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112
nitefury_pcie_xdma_ddr/project/o.tcl
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@ -1,9 +1,13 @@
# 创建Vivado工程（非图形界面模式）
create_project my_project ./my_project -part xc7k480tffg1156-2L -force
create_project -force my_project
set_property SOURCE_MGMT_MODE None [current_project]
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
set_property PART xc7k480tffg1156-2L [current_project]
# # 生成IP核（以AXI UART Lite为例）
# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst
# # 配置IP参数
# set_property -dict [list \
# CONFIG.C_BAUDRATE {115200} \
@ -13,31 +17,95 @@ create_project my_project ./my_project -part xc7k480tffg1156-2L -force
# ] [get_ips uart_inst]
create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0
generate_target -force all [get_ips axi_interconnect_0]
synth_ip [get_ips axi_interconnect_0]
# add_file ../uart_inst.xci
add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
# import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
# import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
generate_target all [get_ips Top_axi_bram_ctrl_0_0]
generate_target all [get_ips Top_xlconstant_2_0]
# upgrade_ip [get_ips Top_axi_interconnect_0_0]
# # set_property GENERATE_SYNTH_CHECKPOINT true Top_axi_interconnect_0_0
# generate_target -force all [get_ips Top_axi_interconnect_0_0]
# synth_ip [get_ips Top_axi_interconnect_0_0]
# import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
# import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
# import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
# import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
# import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
# import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
# import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
# add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# add_file ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
# add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
# add_file ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
# add_file ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
# add_file ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
# add_file ../sources/ip/Top_xbar_0/Top_xbar_0.xci
# add_file ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
# add_file ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
# add_file ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
# add_file ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
# generate_target all [get_ips Top_axi_bram_ctrl_0_0]
# generate_target all [get_ips Top_util_vector_logic_1_3]
# generate_target all [get_ips Top_xlconstant_2_0]
# generate_target all [get_ips Top_axi_interconnect_0_0]
# generate_target all [get_ips Top_util_vector_logic_1_4]
# generate_target all [get_ips Top_blk_mem_gen_0_0]
# generate_target all [get_ips Top_xbar_0]
# generate_target all [get_ips Top_mig_7series_1_0]
# generate_target all [get_ips Top_xdma_1_0]
# generate_target all [get_ips Top_util_ds_buf_0_0]
# generate_target all [get_ips Top_xlconstant_0_0]
# synth_ip [get_ips Top_axi_bram_ctrl_0_0]
# synth_ip [get_ips Top_util_vector_logic_1_3]
# synth_ip [get_ips Top_xlconstant_2_0]
# synth_ip [get_ips Top_axi_interconnect_0_0]
# synth_ip [get_ips Top_util_vector_logic_1_4]
# synth_ip [get_ips Top_blk_mem_gen_0_0]
# synth_ip [get_ips Top_xbar_0]
# synth_ip [get_ips Top_mig_7series_1_0]
# synth_ip [get_ips Top_xdma_1_0]
# synth_ip [get_ips Top_util_ds_buf_0_0]
# synth_ip [get_ips Top_xlconstant_0_0]
# add_file ../sources/Top_wrapper.v
# add_file ../sources/Top.bd
# add_file -fileset constrs_1 ../normal.xdc
# set_property TOP Top_wrapper [current_fileset]
# set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]
# close_project
# open_project my_project
# # Synthesis
# # PRESYNTH
# # set_property DESIGN_MODE GateLvl [current_fileset]
# reset_run synth_1
# launch_runs synth_1
# wait_on_run synth_1
# #report_property [get_runs synth_1]
# if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
# # Place and Route
# reset_run impl_1
# launch_runs impl_1
# wait_on_run impl_1
# #report_property [get_runs impl_1]
# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
# # Bitstream generation
# open_run impl_1
# # write_bitstream -force xdma480t
# # write_debug_probes -force -quiet xdma480t.ltx
# close_project
synth_ip [get_ips Top_axi_bram_ctrl_0_0]
synth_ip [get_ips Top_xlconstant_2_0]
# write_ip_tcl -help
# write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl

104
nitefury_pcie_xdma_ddr/project/sources/Top.bda
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@ -23,63 +23,6 @@
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="BA">0x0000000000000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x000000007FFFFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c1_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S1_AXI</data>
<data key="MM">c1_memmap</data>
<data key="SS">c1_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">memory</data>
<data key="VT">AC</data>
</node>
<node id="n1">
<data key="BA">0x0000000100100000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000001001FFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c1_s_axi_ctrl_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S1_AXI_CTRL</data>
<data key="MM">c1_s_axi_ctrl_memmap</data>
<data key="SS">c1_s_axi_ctrl_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<node id="n2">
<data key="BA">0x0000000100000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000001000FFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c0_s_axi_ctrl_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S0_AXI_CTRL</data>
<data key="MM">c0_s_axi_ctrl_memmap</data>
<data key="SS">c0_s_axi_ctrl_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<node id="n3">
<data key="BA">0x0000000200000000</data>
<data key="BP">C_S_AXI_BASEADDR</data>
<data key="HA">0x0000000200001FFF</data>
@ -97,54 +40,23 @@
<data key="TU">memory</data>
<data key="VT">AC</data>
</node>
<node id="n4">
<data key="BA">0x0000000080000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000000FFFFFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c0_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S0_AXI</data>
<data key="MM">c0_memmap</data>
<data key="SS">c0_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">memory</data>
<data key="VT">AC</data>
<node id="n1">
<data key="VM">Top</data>
<data key="VT">BC</data>
</node>
<node id="n5">
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n6">
<node id="n3">
<data key="VH">2</data>
<data key="VM">Top</data>
<data key="VT">VR</data>
</node>
<node id="n7">
<data key="VM">Top</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n7" target="n6"/>
<edge id="e1" source="n6" target="n5"/>
<edge id="e2" source="n3" target="n5">
<data key="EH">2</data>
</edge>
<edge id="e3" source="n4" target="n5">
<data key="EH">2</data>
</edge>
<edge id="e4" source="n2" target="n5">
<data key="EH">2</data>
</edge>
<edge id="e5" source="n0" target="n5">
<data key="EH">2</data>
</edge>
<edge id="e6" source="n1" target="n5">
<edge id="e0" source="n1" target="n3"/>
<edge id="e1" source="n3" target="n2"/>
<edge id="e2" source="n0" target="n2">
<data key="EH">2</data>
</edge>
</graph>

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
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@ -54,7 +54,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
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@ -335,7 +335,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

4
nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
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@ -156,7 +156,7 @@
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.10587 mW", "resolve_type": "generated", "usage": "all" } ]
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.3746 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintex7" } ],
@ -169,7 +169,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
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@ -1174,7 +1174,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj
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@ -19,7 +19,7 @@
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k480ti-ffg1156/-2L</TargetFPGA>
<TargetFPGA>xc7k480t-ffg1156/-2L</TargetFPGA>
<Version>4.2</Version>

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj
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@ -19,7 +19,7 @@
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k480ti-ffg1156/-2L</TargetFPGA>
<TargetFPGA>xc7k480t-ffg1156/-2L</TargetFPGA>
<Version>4.2</Version>

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
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@ -40,7 +40,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
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@ -28,7 +28,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
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@ -28,7 +28,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci
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@ -1251,7 +1251,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

78
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
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@ -1286,7 +1286,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -1366,13 +1366,13 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
@ -1387,10 +1387,10 @@
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
@ -1416,7 +1416,7 @@
"parameters": {
"BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
@ -1443,32 +1443,32 @@
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
"HAS_BURST.VALUE_SRC": [ { "value": "CONSTANT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "62500000", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MAX_BURST_LENGTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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},
"port_maps": {

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
View File

@ -27,7 +27,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
View File

@ -27,7 +27,7 @@
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
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"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},