82 lines
2.5 KiB
Tcl
82 lines
2.5 KiB
Tcl
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create_project -force my_project
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set_property SOURCE_MGMT_MODE None [current_project]
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set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
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set_property PART xc7k480tffg1156-2L [current_project]
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set_param general.maxThreads 16
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# create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0
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# set_property -dict [list \
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# CONFIG.NUM_SLAVE_PORTS {5} \
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# ] [get_ips axi_interconnect_0]
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# generate_target -force all [get_ips axi_interconnect_0]
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# synth_ip [get_ips axi_interconnect_0]
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import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
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import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
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import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
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import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
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import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
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import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
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import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
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import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
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import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
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import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
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generate_target all [get_ips Top_axi_bram_ctrl_0_0]
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generate_target all [get_ips Top_util_vector_logic_1_3]
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generate_target all [get_ips Top_xlconstant_2_0]
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generate_target all [get_ips Top_util_vector_logic_1_4]
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generate_target all [get_ips Top_blk_mem_gen_0_0]
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generate_target all [get_ips Top_xbar_0]
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generate_target all [get_ips Top_xdma_1_0]
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generate_target all [get_ips Top_util_ds_buf_0_0]
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generate_target all [get_ips Top_xlconstant_0_0]
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generate_target all [get_ips Top_mig_7series_1_0]
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add_file ../sources/Top.v
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add_file -fileset constrs_1 ../normal.xdc
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set_property TOP Top [current_fileset]
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set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]
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close_project
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open_project my_project
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##### Synthesis
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##### PRESYNTH
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# set_property DESIGN_MODE GateLvl [current_fileset]
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reset_run synth_1
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launch_runs synth_1 -jobs 16
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wait_on_run synth_1
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#report_property [get_runs synth_1]
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if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
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##### Place and Route
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reset_run impl_1
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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#report_property [get_runs impl_1]
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# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
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##### Bitstream generation
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open_run impl_1
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write_bitstream -force my_project
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write_debug_probes -force -quiet my_project.ltx
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close_project
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