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xc7k480t/nitefury_pcie_xdma_ddr/project/sources/Top.v

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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
//Date : Mon May 12 00:32:06 2025
//Host : deve running 64-bit Ubuntu 22.04.5 LTS
//Command : generate_target Top.bd
//Design : Top
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* HW_HANDOFF = "Top.hwdef" *) (* core_generation_info = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=27,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *)
module Top
(C0_DDR3_0_addr,
C0_DDR3_0_ba,
C0_DDR3_0_cas_n,
C0_DDR3_0_ck_n,
C0_DDR3_0_ck_p,
C0_DDR3_0_cke,
C0_DDR3_0_cs_n,
C0_DDR3_0_dq,
C0_DDR3_0_dqs_n,
C0_DDR3_0_dqs_p,
C0_DDR3_0_odt,
C0_DDR3_0_ras_n,
C0_DDR3_0_reset_n,
C0_DDR3_0_we_n,
C0_SYS_CLK_0_clk_n,
C0_SYS_CLK_0_clk_p,
C1_DDR3_0_addr,
C1_DDR3_0_ba,
C1_DDR3_0_cas_n,
C1_DDR3_0_ck_n,
C1_DDR3_0_ck_p,
C1_DDR3_0_cke,
C1_DDR3_0_cs_n,
C1_DDR3_0_dq,
C1_DDR3_0_dqs_n,
C1_DDR3_0_dqs_p,
C1_DDR3_0_odt,
C1_DDR3_0_ras_n,
C1_DDR3_0_reset_n,
C1_DDR3_0_we_n,
C1_SYS_CLK_0_clk_n,
C1_SYS_CLK_0_clk_p,
pci_reset,
pcie_clkin_clk_n,
pcie_clkin_clk_p,
pcie_mgt_0_rxn,
pcie_mgt_0_rxp,
pcie_mgt_0_txn,
pcie_mgt_0_txp,
user_lnk_up_0);
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n;
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p;
(* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn;
(* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp;
(* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn;
(* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp;
output user_lnk_up_0;
wire C0_SYS_CLK_0_1_CLK_N;
wire C0_SYS_CLK_0_1_CLK_P;
wire C1_SYS_CLK_0_1_CLK_N;
wire C1_SYS_CLK_0_1_CLK_P;
wire [7:0]M00_ARESETN_2;
wire [63:0]S00_AXI_1_ARADDR;
wire [1:0]S00_AXI_1_ARBURST;
wire [3:0]S00_AXI_1_ARCACHE;
wire [3:0]S00_AXI_1_ARID;
wire [7:0]S00_AXI_1_ARLEN;
wire S00_AXI_1_ARLOCK;
wire [2:0]S00_AXI_1_ARPROT;
wire S00_AXI_1_ARREADY;
wire [2:0]S00_AXI_1_ARSIZE;
wire S00_AXI_1_ARVALID;
wire [63:0]S00_AXI_1_AWADDR;
wire [1:0]S00_AXI_1_AWBURST;
wire [3:0]S00_AXI_1_AWCACHE;
wire [3:0]S00_AXI_1_AWID;
wire [7:0]S00_AXI_1_AWLEN;
wire S00_AXI_1_AWLOCK;
wire [2:0]S00_AXI_1_AWPROT;
wire S00_AXI_1_AWREADY;
wire [2:0]S00_AXI_1_AWSIZE;
wire S00_AXI_1_AWVALID;
wire [3:0]S00_AXI_1_BID;
wire S00_AXI_1_BREADY;
wire [1:0]S00_AXI_1_BRESP;
wire S00_AXI_1_BVALID;
wire [63:0]S00_AXI_1_RDATA;
wire [3:0]S00_AXI_1_RID;
wire S00_AXI_1_RLAST;
wire S00_AXI_1_RREADY;
wire [1:0]S00_AXI_1_RRESP;
wire S00_AXI_1_RVALID;
wire [63:0]S00_AXI_1_WDATA;
wire S00_AXI_1_WLAST;
wire S00_AXI_1_WREADY;
wire [7:0]S00_AXI_1_WSTRB;
wire S00_AXI_1_WVALID;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [31:0]axi_interconnect_0_M00_AXI_ARADDR;
wire axi_interconnect_0_M00_AXI_ARREADY;
wire axi_interconnect_0_M00_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M00_AXI_AWADDR;
wire axi_interconnect_0_M00_AXI_AWREADY;
wire axi_interconnect_0_M00_AXI_AWVALID;
wire axi_interconnect_0_M00_AXI_BREADY;
wire [1:0]axi_interconnect_0_M00_AXI_BRESP;
wire axi_interconnect_0_M00_AXI_BVALID;
wire [31:0]axi_interconnect_0_M00_AXI_RDATA;
wire axi_interconnect_0_M00_AXI_RREADY;
wire [1:0]axi_interconnect_0_M00_AXI_RRESP;
wire axi_interconnect_0_M00_AXI_RVALID;
wire [31:0]axi_interconnect_0_M00_AXI_WDATA;
wire axi_interconnect_0_M00_AXI_WREADY;
wire axi_interconnect_0_M00_AXI_WVALID;
wire [30:0]axi_interconnect_0_M01_AXI_ARADDR;
wire [1:0]axi_interconnect_0_M01_AXI_ARBURST;
wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE;
wire [7:0]axi_interconnect_0_M01_AXI_ARLEN;
wire axi_interconnect_0_M01_AXI_ARLOCK;
wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;
wire [3:0]axi_interconnect_0_M01_AXI_ARQOS;
wire axi_interconnect_0_M01_AXI_ARREADY;
wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE;
wire axi_interconnect_0_M01_AXI_ARVALID;
wire [30:0]axi_interconnect_0_M01_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M01_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE;
wire [7:0]axi_interconnect_0_M01_AXI_AWLEN;
wire axi_interconnect_0_M01_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;
wire [3:0]axi_interconnect_0_M01_AXI_AWQOS;
wire axi_interconnect_0_M01_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE;
wire axi_interconnect_0_M01_AXI_AWVALID;
wire axi_interconnect_0_M01_AXI_BREADY;
wire [1:0]axi_interconnect_0_M01_AXI_BRESP;
wire axi_interconnect_0_M01_AXI_BVALID;
wire [511:0]axi_interconnect_0_M01_AXI_RDATA;
wire axi_interconnect_0_M01_AXI_RLAST;
wire axi_interconnect_0_M01_AXI_RREADY;
wire [1:0]axi_interconnect_0_M01_AXI_RRESP;
wire axi_interconnect_0_M01_AXI_RVALID;
wire [511:0]axi_interconnect_0_M01_AXI_WDATA;
wire axi_interconnect_0_M01_AXI_WLAST;
wire axi_interconnect_0_M01_AXI_WREADY;
wire [63:0]axi_interconnect_0_M01_AXI_WSTRB;
wire axi_interconnect_0_M01_AXI_WVALID;
wire [31:0]axi_interconnect_0_M02_AXI_ARADDR;
wire axi_interconnect_0_M02_AXI_ARREADY;
wire axi_interconnect_0_M02_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M02_AXI_AWADDR;
wire axi_interconnect_0_M02_AXI_AWREADY;
wire axi_interconnect_0_M02_AXI_AWVALID;
wire axi_interconnect_0_M02_AXI_BREADY;
wire [1:0]axi_interconnect_0_M02_AXI_BRESP;
wire axi_interconnect_0_M02_AXI_BVALID;
wire [31:0]axi_interconnect_0_M02_AXI_RDATA;
wire axi_interconnect_0_M02_AXI_RREADY;
wire [1:0]axi_interconnect_0_M02_AXI_RRESP;
wire axi_interconnect_0_M02_AXI_RVALID;
wire [31:0]axi_interconnect_0_M02_AXI_WDATA;
wire axi_interconnect_0_M02_AXI_WREADY;
wire axi_interconnect_0_M02_AXI_WVALID;
wire [30:0]axi_interconnect_0_M03_AXI_ARADDR;
wire [1:0]axi_interconnect_0_M03_AXI_ARBURST;
wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE;
wire [7:0]axi_interconnect_0_M03_AXI_ARLEN;
wire axi_interconnect_0_M03_AXI_ARLOCK;
wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;
wire [3:0]axi_interconnect_0_M03_AXI_ARQOS;
wire axi_interconnect_0_M03_AXI_ARREADY;
wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE;
wire axi_interconnect_0_M03_AXI_ARVALID;
wire [30:0]axi_interconnect_0_M03_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M03_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE;
wire [7:0]axi_interconnect_0_M03_AXI_AWLEN;
wire axi_interconnect_0_M03_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;
wire [3:0]axi_interconnect_0_M03_AXI_AWQOS;
wire axi_interconnect_0_M03_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE;
wire axi_interconnect_0_M03_AXI_AWVALID;
wire axi_interconnect_0_M03_AXI_BREADY;
wire [1:0]axi_interconnect_0_M03_AXI_BRESP;
wire axi_interconnect_0_M03_AXI_BVALID;
wire [511:0]axi_interconnect_0_M03_AXI_RDATA;
wire axi_interconnect_0_M03_AXI_RLAST;
wire axi_interconnect_0_M03_AXI_RREADY;
wire [1:0]axi_interconnect_0_M03_AXI_RRESP;
wire axi_interconnect_0_M03_AXI_RVALID;
wire [511:0]axi_interconnect_0_M03_AXI_WDATA;
wire axi_interconnect_0_M03_AXI_WLAST;
wire axi_interconnect_0_M03_AXI_WREADY;
wire [63:0]axi_interconnect_0_M03_AXI_WSTRB;
wire axi_interconnect_0_M03_AXI_WVALID;
wire [12:0]axi_interconnect_0_M04_AXI_ARADDR;
wire [1:0]axi_interconnect_0_M04_AXI_ARBURST;
wire [3:0]axi_interconnect_0_M04_AXI_ARCACHE;
wire [7:0]axi_interconnect_0_M04_AXI_ARLEN;
wire axi_interconnect_0_M04_AXI_ARLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_ARPROT;
wire axi_interconnect_0_M04_AXI_ARREADY;
wire [2:0]axi_interconnect_0_M04_AXI_ARSIZE;
wire axi_interconnect_0_M04_AXI_ARVALID;
wire [12:0]axi_interconnect_0_M04_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M04_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M04_AXI_AWCACHE;
wire [7:0]axi_interconnect_0_M04_AXI_AWLEN;
wire axi_interconnect_0_M04_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_AWPROT;
wire axi_interconnect_0_M04_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M04_AXI_AWSIZE;
wire axi_interconnect_0_M04_AXI_AWVALID;
wire axi_interconnect_0_M04_AXI_BREADY;
wire [1:0]axi_interconnect_0_M04_AXI_BRESP;
wire axi_interconnect_0_M04_AXI_BVALID;
wire [31:0]axi_interconnect_0_M04_AXI_RDATA;
wire axi_interconnect_0_M04_AXI_RLAST;
wire axi_interconnect_0_M04_AXI_RREADY;
wire [1:0]axi_interconnect_0_M04_AXI_RRESP;
wire axi_interconnect_0_M04_AXI_RVALID;
wire [31:0]axi_interconnect_0_M04_AXI_WDATA;
wire axi_interconnect_0_M04_AXI_WLAST;
wire axi_interconnect_0_M04_AXI_WREADY;
wire [3:0]axi_interconnect_0_M04_AXI_WSTRB;
wire axi_interconnect_0_M04_AXI_WVALID;
wire [14:0]mig_7series_1_C0_DDR3_ADDR;
wire [2:0]mig_7series_1_C0_DDR3_BA;
wire mig_7series_1_C0_DDR3_CAS_N;
wire [0:0]mig_7series_1_C0_DDR3_CKE;
wire [0:0]mig_7series_1_C0_DDR3_CK_N;
wire [0:0]mig_7series_1_C0_DDR3_CK_P;
wire [0:0]mig_7series_1_C0_DDR3_CS_N;
wire [71:0]mig_7series_1_C0_DDR3_DQ;
wire [8:0]mig_7series_1_C0_DDR3_DQS_N;
wire [8:0]mig_7series_1_C0_DDR3_DQS_P;
wire [0:0]mig_7series_1_C0_DDR3_ODT;
wire mig_7series_1_C0_DDR3_RAS_N;
wire mig_7series_1_C0_DDR3_RESET_N;
wire mig_7series_1_C0_DDR3_WE_N;
wire [14:0]mig_7series_1_C1_DDR3_ADDR;
wire [2:0]mig_7series_1_C1_DDR3_BA;
wire mig_7series_1_C1_DDR3_CAS_N;
wire [0:0]mig_7series_1_C1_DDR3_CKE;
wire [0:0]mig_7series_1_C1_DDR3_CK_N;
wire [0:0]mig_7series_1_C1_DDR3_CK_P;
wire [0:0]mig_7series_1_C1_DDR3_CS_N;
wire [71:0]mig_7series_1_C1_DDR3_DQ;
wire [8:0]mig_7series_1_C1_DDR3_DQS_N;
wire [8:0]mig_7series_1_C1_DDR3_DQS_P;
wire [0:0]mig_7series_1_C1_DDR3_ODT;
wire mig_7series_1_C1_DDR3_RAS_N;
wire mig_7series_1_C1_DDR3_RESET_N;
wire mig_7series_1_C1_DDR3_WE_N;
wire mig_7series_1_c0_ui_clk_sync_rst;
wire mig_7series_1_c1_ui_clk;
wire mig_7series_1_c1_ui_clk_sync_rst;
wire mig_7series_1_ui_clk;
wire pci_reset_1;
wire [0:0]pcie_clkin_1_CLK_N;
wire [0:0]pcie_clkin_1_CLK_P;
wire [0:0]util_ds_buf_0_IBUF_OUT;
wire [7:0]util_vector_logic_2_Res;
wire xdma_1_axi_aclk;
wire xdma_1_axi_aresetn;
wire [0:0]xdma_1_pcie_mgt_rxn;
wire [0:0]xdma_1_pcie_mgt_rxp;
wire [0:0]xdma_1_pcie_mgt_txn;
wire [0:0]xdma_1_pcie_mgt_txp;
wire xdma_1_user_lnk_up;
wire [0:0]xlconstant_0_dout;
wire [0:0]xlconstant_2_dout;
assign C0_DDR3_0_addr[14:0] = mig_7series_1_C0_DDR3_ADDR;
assign C0_DDR3_0_ba[2:0] = mig_7series_1_C0_DDR3_BA;
assign C0_DDR3_0_cas_n = mig_7series_1_C0_DDR3_CAS_N;
assign C0_DDR3_0_ck_n[0] = mig_7series_1_C0_DDR3_CK_N;
assign C0_DDR3_0_ck_p[0] = mig_7series_1_C0_DDR3_CK_P;
assign C0_DDR3_0_cke[0] = mig_7series_1_C0_DDR3_CKE;
assign C0_DDR3_0_cs_n[0] = mig_7series_1_C0_DDR3_CS_N;
assign C0_DDR3_0_odt[0] = mig_7series_1_C0_DDR3_ODT;
assign C0_DDR3_0_ras_n = mig_7series_1_C0_DDR3_RAS_N;
assign C0_DDR3_0_reset_n = mig_7series_1_C0_DDR3_RESET_N;
assign C0_DDR3_0_we_n = mig_7series_1_C0_DDR3_WE_N;
assign C0_SYS_CLK_0_1_CLK_N = C0_SYS_CLK_0_clk_n;
assign C0_SYS_CLK_0_1_CLK_P = C0_SYS_CLK_0_clk_p;
assign C1_DDR3_0_addr[14:0] = mig_7series_1_C1_DDR3_ADDR;
assign C1_DDR3_0_ba[2:0] = mig_7series_1_C1_DDR3_BA;
assign C1_DDR3_0_cas_n = mig_7series_1_C1_DDR3_CAS_N;
assign C1_DDR3_0_ck_n[0] = mig_7series_1_C1_DDR3_CK_N;
assign C1_DDR3_0_ck_p[0] = mig_7series_1_C1_DDR3_CK_P;
assign C1_DDR3_0_cke[0] = mig_7series_1_C1_DDR3_CKE;
assign C1_DDR3_0_cs_n[0] = mig_7series_1_C1_DDR3_CS_N;
assign C1_DDR3_0_odt[0] = mig_7series_1_C1_DDR3_ODT;
assign C1_DDR3_0_ras_n = mig_7series_1_C1_DDR3_RAS_N;
assign C1_DDR3_0_reset_n = mig_7series_1_C1_DDR3_RESET_N;
assign C1_DDR3_0_we_n = mig_7series_1_C1_DDR3_WE_N;
assign C1_SYS_CLK_0_1_CLK_N = C1_SYS_CLK_0_clk_n;
assign C1_SYS_CLK_0_1_CLK_P = C1_SYS_CLK_0_clk_p;
assign pci_reset_1 = pci_reset;
assign pcie_clkin_1_CLK_N = pcie_clkin_clk_n[0];
assign pcie_clkin_1_CLK_P = pcie_clkin_clk_p[0];
assign pcie_mgt_0_txn[0] = xdma_1_pcie_mgt_txn;
assign pcie_mgt_0_txp[0] = xdma_1_pcie_mgt_txp;
assign user_lnk_up_0 = xdma_1_user_lnk_up;
assign xdma_1_pcie_mgt_rxn = pcie_mgt_0_rxn[0];
assign xdma_1_pcie_mgt_rxp = pcie_mgt_0_rxp[0];
Top_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(xdma_1_axi_aclk),
.s_axi_araddr(axi_interconnect_0_M04_AXI_ARADDR),
.s_axi_arburst(axi_interconnect_0_M04_AXI_ARBURST),
.s_axi_arcache(axi_interconnect_0_M04_AXI_ARCACHE),
.s_axi_aresetn(xdma_1_axi_aresetn),
.s_axi_arlen(axi_interconnect_0_M04_AXI_ARLEN),
.s_axi_arlock(axi_interconnect_0_M04_AXI_ARLOCK),
.s_axi_arprot(axi_interconnect_0_M04_AXI_ARPROT),
.s_axi_arready(axi_interconnect_0_M04_AXI_ARREADY),
.s_axi_arsize(axi_interconnect_0_M04_AXI_ARSIZE),
.s_axi_arvalid(axi_interconnect_0_M04_AXI_ARVALID),
.s_axi_awaddr(axi_interconnect_0_M04_AXI_AWADDR),
.s_axi_awburst(axi_interconnect_0_M04_AXI_AWBURST),
.s_axi_awcache(axi_interconnect_0_M04_AXI_AWCACHE),
.s_axi_awlen(axi_interconnect_0_M04_AXI_AWLEN),
.s_axi_awlock(axi_interconnect_0_M04_AXI_AWLOCK),
.s_axi_awprot(axi_interconnect_0_M04_AXI_AWPROT),
.s_axi_awready(axi_interconnect_0_M04_AXI_AWREADY),
.s_axi_awsize(axi_interconnect_0_M04_AXI_AWSIZE),
.s_axi_awvalid(axi_interconnect_0_M04_AXI_AWVALID),
.s_axi_bready(axi_interconnect_0_M04_AXI_BREADY),
.s_axi_bresp(axi_interconnect_0_M04_AXI_BRESP),
.s_axi_bvalid(axi_interconnect_0_M04_AXI_BVALID),
.s_axi_rdata(axi_interconnect_0_M04_AXI_RDATA),
.s_axi_rlast(axi_interconnect_0_M04_AXI_RLAST),
.s_axi_rready(axi_interconnect_0_M04_AXI_RREADY),
.s_axi_rresp(axi_interconnect_0_M04_AXI_RRESP),
.s_axi_rvalid(axi_interconnect_0_M04_AXI_RVALID),
.s_axi_wdata(axi_interconnect_0_M04_AXI_WDATA),
.s_axi_wlast(axi_interconnect_0_M04_AXI_WLAST),
.s_axi_wready(axi_interconnect_0_M04_AXI_WREADY),
.s_axi_wstrb(axi_interconnect_0_M04_AXI_WSTRB),
.s_axi_wvalid(axi_interconnect_0_M04_AXI_WVALID));
Top_axi_interconnect_0_0 axi_interconnect_0
(.ACLK(xdma_1_axi_aclk),
.ARESETN(xdma_1_axi_aresetn),
.M00_ACLK(mig_7series_1_ui_clk),
.M00_ARESETN(M00_ARESETN_2),
.M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR),
.M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY),
.M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR),
.M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY),
.M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID),
.M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY),
.M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID),
.M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA),
.M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY),
.M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID),
.M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA),
.M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY),
.M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID),
.M01_ACLK(mig_7series_1_ui_clk),
.M01_ARESETN(M00_ARESETN_2),
.M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),
.M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST),
.M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE),
.M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN),
.M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK),
.M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS),
.M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),
.M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE),
.M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),
.M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST),
.M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE),
.M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN),
.M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK),
.M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS),
.M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),
.M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE),
.M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),
.M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),
.M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST),
.M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),
.M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),
.M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST),
.M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),
.M02_ACLK(mig_7series_1_c1_ui_clk),
.M02_ARESETN(util_vector_logic_2_Res),
.M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),
.M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),
.M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),
.M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),
.M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),
.M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),
.M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),
.M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),
.M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),
.M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),
.M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),
.M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.M03_ACLK(mig_7series_1_c1_ui_clk),
.M03_ARESETN(util_vector_logic_2_Res),
.M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),
.M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST),
.M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE),
.M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN),
.M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK),
.M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS),
.M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),
.M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE),
.M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),
.M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST),
.M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE),
.M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN),
.M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK),
.M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS),
.M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),
.M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE),
.M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),
.M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),
.M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),
.M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST),
.M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),
.M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),
.M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),
.M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST),
.M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),
.M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.M04_ACLK(xdma_1_axi_aclk),
.M04_ARESETN(xdma_1_axi_aresetn),
.M04_AXI_araddr(axi_interconnect_0_M04_AXI_ARADDR),
.M04_AXI_arburst(axi_interconnect_0_M04_AXI_ARBURST),
.M04_AXI_arcache(axi_interconnect_0_M04_AXI_ARCACHE),
.M04_AXI_arlen(axi_interconnect_0_M04_AXI_ARLEN),
.M04_AXI_arlock(axi_interconnect_0_M04_AXI_ARLOCK),
.M04_AXI_arprot(axi_interconnect_0_M04_AXI_ARPROT),
.M04_AXI_arready(axi_interconnect_0_M04_AXI_ARREADY),
.M04_AXI_arsize(axi_interconnect_0_M04_AXI_ARSIZE),
.M04_AXI_arvalid(axi_interconnect_0_M04_AXI_ARVALID),
.M04_AXI_awaddr(axi_interconnect_0_M04_AXI_AWADDR),
.M04_AXI_awburst(axi_interconnect_0_M04_AXI_AWBURST),
.M04_AXI_awcache(axi_interconnect_0_M04_AXI_AWCACHE),
.M04_AXI_awlen(axi_interconnect_0_M04_AXI_AWLEN),
.M04_AXI_awlock(axi_interconnect_0_M04_AXI_AWLOCK),
.M04_AXI_awprot(axi_interconnect_0_M04_AXI_AWPROT),
.M04_AXI_awready(axi_interconnect_0_M04_AXI_AWREADY),
.M04_AXI_awsize(axi_interconnect_0_M04_AXI_AWSIZE),
.M04_AXI_awvalid(axi_interconnect_0_M04_AXI_AWVALID),
.M04_AXI_bready(axi_interconnect_0_M04_AXI_BREADY),
.M04_AXI_bresp(axi_interconnect_0_M04_AXI_BRESP),
.M04_AXI_bvalid(axi_interconnect_0_M04_AXI_BVALID),
.M04_AXI_rdata(axi_interconnect_0_M04_AXI_RDATA),
.M04_AXI_rlast(axi_interconnect_0_M04_AXI_RLAST),
.M04_AXI_rready(axi_interconnect_0_M04_AXI_RREADY),
.M04_AXI_rresp(axi_interconnect_0_M04_AXI_RRESP),
.M04_AXI_rvalid(axi_interconnect_0_M04_AXI_RVALID),
.M04_AXI_wdata(axi_interconnect_0_M04_AXI_WDATA),
.M04_AXI_wlast(axi_interconnect_0_M04_AXI_WLAST),
.M04_AXI_wready(axi_interconnect_0_M04_AXI_WREADY),
.M04_AXI_wstrb(axi_interconnect_0_M04_AXI_WSTRB),
.M04_AXI_wvalid(axi_interconnect_0_M04_AXI_WVALID),
.S00_ACLK(xdma_1_axi_aclk),
.S00_ARESETN(xdma_1_axi_aresetn),
.S00_AXI_araddr(S00_AXI_1_ARADDR),
.S00_AXI_arburst(S00_AXI_1_ARBURST),
.S00_AXI_arcache(S00_AXI_1_ARCACHE),
.S00_AXI_arid(S00_AXI_1_ARID),
.S00_AXI_arlen(S00_AXI_1_ARLEN),
.S00_AXI_arlock(S00_AXI_1_ARLOCK),
.S00_AXI_arprot(S00_AXI_1_ARPROT),
.S00_AXI_arready(S00_AXI_1_ARREADY),
.S00_AXI_arsize(S00_AXI_1_ARSIZE),
.S00_AXI_arvalid(S00_AXI_1_ARVALID),
.S00_AXI_awaddr(S00_AXI_1_AWADDR),
.S00_AXI_awburst(S00_AXI_1_AWBURST),
.S00_AXI_awcache(S00_AXI_1_AWCACHE),
.S00_AXI_awid(S00_AXI_1_AWID),
.S00_AXI_awlen(S00_AXI_1_AWLEN),
.S00_AXI_awlock(S00_AXI_1_AWLOCK),
.S00_AXI_awprot(S00_AXI_1_AWPROT),
.S00_AXI_awready(S00_AXI_1_AWREADY),
.S00_AXI_awsize(S00_AXI_1_AWSIZE),
.S00_AXI_awvalid(S00_AXI_1_AWVALID),
.S00_AXI_bid(S00_AXI_1_BID),
.S00_AXI_bready(S00_AXI_1_BREADY),
.S00_AXI_bresp(S00_AXI_1_BRESP),
.S00_AXI_bvalid(S00_AXI_1_BVALID),
.S00_AXI_rdata(S00_AXI_1_RDATA),
.S00_AXI_rid(S00_AXI_1_RID),
.S00_AXI_rlast(S00_AXI_1_RLAST),
.S00_AXI_rready(S00_AXI_1_RREADY),
.S00_AXI_rresp(S00_AXI_1_RRESP),
.S00_AXI_rvalid(S00_AXI_1_RVALID),
.S00_AXI_wdata(S00_AXI_1_WDATA),
.S00_AXI_wlast(S00_AXI_1_WLAST),
.S00_AXI_wready(S00_AXI_1_WREADY),
.S00_AXI_wstrb(S00_AXI_1_WSTRB),
.S00_AXI_wvalid(S00_AXI_1_WVALID));
Top_blk_mem_gen_0_0 blk_mem_gen_0
(.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,axi_bram_ctrl_0_BRAM_PORTA_ADDR}),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE));
Top_mig_7series_1_0 mig_7series_1
(.c0_aresetn(xlconstant_0_dout),
.c0_ddr3_addr(mig_7series_1_C0_DDR3_ADDR),
.c0_ddr3_ba(mig_7series_1_C0_DDR3_BA),
.c0_ddr3_cas_n(mig_7series_1_C0_DDR3_CAS_N),
.c0_ddr3_ck_n(mig_7series_1_C0_DDR3_CK_N),
.c0_ddr3_ck_p(mig_7series_1_C0_DDR3_CK_P),
.c0_ddr3_cke(mig_7series_1_C0_DDR3_CKE),
.c0_ddr3_cs_n(mig_7series_1_C0_DDR3_CS_N),
.c0_ddr3_dq(C0_DDR3_0_dq[71:0]),
.c0_ddr3_dqs_n(C0_DDR3_0_dqs_n[8:0]),
.c0_ddr3_dqs_p(C0_DDR3_0_dqs_p[8:0]),
.c0_ddr3_odt(mig_7series_1_C0_DDR3_ODT),
.c0_ddr3_ras_n(mig_7series_1_C0_DDR3_RAS_N),
.c0_ddr3_reset_n(mig_7series_1_C0_DDR3_RESET_N),
.c0_ddr3_we_n(mig_7series_1_C0_DDR3_WE_N),
.c0_s_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR),
.c0_s_axi_arburst(axi_interconnect_0_M01_AXI_ARBURST),
.c0_s_axi_arcache(axi_interconnect_0_M01_AXI_ARCACHE),
.c0_s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.c0_s_axi_arlen(axi_interconnect_0_M01_AXI_ARLEN),
.c0_s_axi_arlock(axi_interconnect_0_M01_AXI_ARLOCK),
.c0_s_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.c0_s_axi_arqos(axi_interconnect_0_M01_AXI_ARQOS),
.c0_s_axi_arready(axi_interconnect_0_M01_AXI_ARREADY),
.c0_s_axi_arsize(axi_interconnect_0_M01_AXI_ARSIZE),
.c0_s_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.c0_s_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR),
.c0_s_axi_awburst(axi_interconnect_0_M01_AXI_AWBURST),
.c0_s_axi_awcache(axi_interconnect_0_M01_AXI_AWCACHE),
.c0_s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.c0_s_axi_awlen(axi_interconnect_0_M01_AXI_AWLEN),
.c0_s_axi_awlock(axi_interconnect_0_M01_AXI_AWLOCK),
.c0_s_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.c0_s_axi_awqos(axi_interconnect_0_M01_AXI_AWQOS),
.c0_s_axi_awready(axi_interconnect_0_M01_AXI_AWREADY),
.c0_s_axi_awsize(axi_interconnect_0_M01_AXI_AWSIZE),
.c0_s_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.c0_s_axi_bready(axi_interconnect_0_M01_AXI_BREADY),
.c0_s_axi_bresp(axi_interconnect_0_M01_AXI_BRESP),
.c0_s_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.c0_s_axi_ctrl_araddr(axi_interconnect_0_M00_AXI_ARADDR),
.c0_s_axi_ctrl_arready(axi_interconnect_0_M00_AXI_ARREADY),
.c0_s_axi_ctrl_arvalid(axi_interconnect_0_M00_AXI_ARVALID),
.c0_s_axi_ctrl_awaddr(axi_interconnect_0_M00_AXI_AWADDR),
.c0_s_axi_ctrl_awready(axi_interconnect_0_M00_AXI_AWREADY),
.c0_s_axi_ctrl_awvalid(axi_interconnect_0_M00_AXI_AWVALID),
.c0_s_axi_ctrl_bready(axi_interconnect_0_M00_AXI_BREADY),
.c0_s_axi_ctrl_bresp(axi_interconnect_0_M00_AXI_BRESP),
.c0_s_axi_ctrl_bvalid(axi_interconnect_0_M00_AXI_BVALID),
.c0_s_axi_ctrl_rdata(axi_interconnect_0_M00_AXI_RDATA),
.c0_s_axi_ctrl_rready(axi_interconnect_0_M00_AXI_RREADY),
.c0_s_axi_ctrl_rresp(axi_interconnect_0_M00_AXI_RRESP),
.c0_s_axi_ctrl_rvalid(axi_interconnect_0_M00_AXI_RVALID),
.c0_s_axi_ctrl_wdata(axi_interconnect_0_M00_AXI_WDATA),
.c0_s_axi_ctrl_wready(axi_interconnect_0_M00_AXI_WREADY),
.c0_s_axi_ctrl_wvalid(axi_interconnect_0_M00_AXI_WVALID),
.c0_s_axi_rdata(axi_interconnect_0_M01_AXI_RDATA),
.c0_s_axi_rlast(axi_interconnect_0_M01_AXI_RLAST),
.c0_s_axi_rready(axi_interconnect_0_M01_AXI_RREADY),
.c0_s_axi_rresp(axi_interconnect_0_M01_AXI_RRESP),
.c0_s_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.c0_s_axi_wdata(axi_interconnect_0_M01_AXI_WDATA),
.c0_s_axi_wlast(axi_interconnect_0_M01_AXI_WLAST),
.c0_s_axi_wready(axi_interconnect_0_M01_AXI_WREADY),
.c0_s_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.c0_s_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID),
.c0_sys_clk_n(C0_SYS_CLK_0_1_CLK_N),
.c0_sys_clk_p(C0_SYS_CLK_0_1_CLK_P),
.c0_ui_clk(mig_7series_1_ui_clk),
.c0_ui_clk_sync_rst(mig_7series_1_c0_ui_clk_sync_rst),
.c1_aresetn(xlconstant_0_dout),
.c1_ddr3_addr(mig_7series_1_C1_DDR3_ADDR),
.c1_ddr3_ba(mig_7series_1_C1_DDR3_BA),
.c1_ddr3_cas_n(mig_7series_1_C1_DDR3_CAS_N),
.c1_ddr3_ck_n(mig_7series_1_C1_DDR3_CK_N),
.c1_ddr3_ck_p(mig_7series_1_C1_DDR3_CK_P),
.c1_ddr3_cke(mig_7series_1_C1_DDR3_CKE),
.c1_ddr3_cs_n(mig_7series_1_C1_DDR3_CS_N),
.c1_ddr3_dq(C1_DDR3_0_dq[71:0]),
.c1_ddr3_dqs_n(C1_DDR3_0_dqs_n[8:0]),
.c1_ddr3_dqs_p(C1_DDR3_0_dqs_p[8:0]),
.c1_ddr3_odt(mig_7series_1_C1_DDR3_ODT),
.c1_ddr3_ras_n(mig_7series_1_C1_DDR3_RAS_N),
.c1_ddr3_reset_n(mig_7series_1_C1_DDR3_RESET_N),
.c1_ddr3_we_n(mig_7series_1_C1_DDR3_WE_N),
.c1_s_axi_araddr(axi_interconnect_0_M03_AXI_ARADDR),
.c1_s_axi_arburst(axi_interconnect_0_M03_AXI_ARBURST),
.c1_s_axi_arcache(axi_interconnect_0_M03_AXI_ARCACHE),
.c1_s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.c1_s_axi_arlen(axi_interconnect_0_M03_AXI_ARLEN),
.c1_s_axi_arlock(axi_interconnect_0_M03_AXI_ARLOCK),
.c1_s_axi_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.c1_s_axi_arqos(axi_interconnect_0_M03_AXI_ARQOS),
.c1_s_axi_arready(axi_interconnect_0_M03_AXI_ARREADY),
.c1_s_axi_arsize(axi_interconnect_0_M03_AXI_ARSIZE),
.c1_s_axi_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.c1_s_axi_awaddr(axi_interconnect_0_M03_AXI_AWADDR),
.c1_s_axi_awburst(axi_interconnect_0_M03_AXI_AWBURST),
.c1_s_axi_awcache(axi_interconnect_0_M03_AXI_AWCACHE),
.c1_s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.c1_s_axi_awlen(axi_interconnect_0_M03_AXI_AWLEN),
.c1_s_axi_awlock(axi_interconnect_0_M03_AXI_AWLOCK),
.c1_s_axi_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.c1_s_axi_awqos(axi_interconnect_0_M03_AXI_AWQOS),
.c1_s_axi_awready(axi_interconnect_0_M03_AXI_AWREADY),
.c1_s_axi_awsize(axi_interconnect_0_M03_AXI_AWSIZE),
.c1_s_axi_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.c1_s_axi_bready(axi_interconnect_0_M03_AXI_BREADY),
.c1_s_axi_bresp(axi_interconnect_0_M03_AXI_BRESP),
.c1_s_axi_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.c1_s_axi_ctrl_araddr(axi_interconnect_0_M02_AXI_ARADDR),
.c1_s_axi_ctrl_arready(axi_interconnect_0_M02_AXI_ARREADY),
.c1_s_axi_ctrl_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.c1_s_axi_ctrl_awaddr(axi_interconnect_0_M02_AXI_AWADDR),
.c1_s_axi_ctrl_awready(axi_interconnect_0_M02_AXI_AWREADY),
.c1_s_axi_ctrl_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.c1_s_axi_ctrl_bready(axi_interconnect_0_M02_AXI_BREADY),
.c1_s_axi_ctrl_bresp(axi_interconnect_0_M02_AXI_BRESP),
.c1_s_axi_ctrl_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.c1_s_axi_ctrl_rdata(axi_interconnect_0_M02_AXI_RDATA),
.c1_s_axi_ctrl_rready(axi_interconnect_0_M02_AXI_RREADY),
.c1_s_axi_ctrl_rresp(axi_interconnect_0_M02_AXI_RRESP),
.c1_s_axi_ctrl_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.c1_s_axi_ctrl_wdata(axi_interconnect_0_M02_AXI_WDATA),
.c1_s_axi_ctrl_wready(axi_interconnect_0_M02_AXI_WREADY),
.c1_s_axi_ctrl_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.c1_s_axi_rdata(axi_interconnect_0_M03_AXI_RDATA),
.c1_s_axi_rlast(axi_interconnect_0_M03_AXI_RLAST),
.c1_s_axi_rready(axi_interconnect_0_M03_AXI_RREADY),
.c1_s_axi_rresp(axi_interconnect_0_M03_AXI_RRESP),
.c1_s_axi_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.c1_s_axi_wdata(axi_interconnect_0_M03_AXI_WDATA),
.c1_s_axi_wlast(axi_interconnect_0_M03_AXI_WLAST),
.c1_s_axi_wready(axi_interconnect_0_M03_AXI_WREADY),
.c1_s_axi_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.c1_s_axi_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.c1_sys_clk_n(C1_SYS_CLK_0_1_CLK_N),
.c1_sys_clk_p(C1_SYS_CLK_0_1_CLK_P),
.c1_ui_clk(mig_7series_1_c1_ui_clk),
.c1_ui_clk_sync_rst(mig_7series_1_c1_ui_clk_sync_rst),
.sys_rst(xlconstant_2_dout));
Top_util_ds_buf_0_0 util_ds_buf_0
(.IBUF_DS_N(pcie_clkin_1_CLK_N),
.IBUF_DS_P(pcie_clkin_1_CLK_P),
.IBUF_OUT(util_ds_buf_0_IBUF_OUT));
Top_util_vector_logic_1_3 util_vector_logic_1
(.Op1({mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst}),
.Res(M00_ARESETN_2));
Top_util_vector_logic_1_4 util_vector_logic_2
(.Op1({mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst}),
.Res(util_vector_logic_2_Res));
Top_xdma_1_0 xdma_1
(.axi_aclk(xdma_1_axi_aclk),
.axi_aresetn(xdma_1_axi_aresetn),
.cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.cfg_mgmt_byte_enable({1'b0,1'b0,1'b0,1'b0}),
.cfg_mgmt_read(1'b0),
.cfg_mgmt_type1_cfg_reg_access(1'b0),
.cfg_mgmt_write(1'b0),
.cfg_mgmt_write_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_araddr(S00_AXI_1_ARADDR),
.m_axi_arburst(S00_AXI_1_ARBURST),
.m_axi_arcache(S00_AXI_1_ARCACHE),
.m_axi_arid(S00_AXI_1_ARID),
.m_axi_arlen(S00_AXI_1_ARLEN),
.m_axi_arlock(S00_AXI_1_ARLOCK),
.m_axi_arprot(S00_AXI_1_ARPROT),
.m_axi_arready(S00_AXI_1_ARREADY),
.m_axi_arsize(S00_AXI_1_ARSIZE),
.m_axi_arvalid(S00_AXI_1_ARVALID),
.m_axi_awaddr(S00_AXI_1_AWADDR),
.m_axi_awburst(S00_AXI_1_AWBURST),
.m_axi_awcache(S00_AXI_1_AWCACHE),
.m_axi_awid(S00_AXI_1_AWID),
.m_axi_awlen(S00_AXI_1_AWLEN),
.m_axi_awlock(S00_AXI_1_AWLOCK),
.m_axi_awprot(S00_AXI_1_AWPROT),
.m_axi_awready(S00_AXI_1_AWREADY),
.m_axi_awsize(S00_AXI_1_AWSIZE),
.m_axi_awvalid(S00_AXI_1_AWVALID),
.m_axi_bid(S00_AXI_1_BID),
.m_axi_bready(S00_AXI_1_BREADY),
.m_axi_bresp(S00_AXI_1_BRESP),
.m_axi_bvalid(S00_AXI_1_BVALID),
.m_axi_rdata(S00_AXI_1_RDATA),
.m_axi_rid(S00_AXI_1_RID),
.m_axi_rlast(S00_AXI_1_RLAST),
.m_axi_rready(S00_AXI_1_RREADY),
.m_axi_rresp(S00_AXI_1_RRESP),
.m_axi_rvalid(S00_AXI_1_RVALID),
.m_axi_wdata(S00_AXI_1_WDATA),
.m_axi_wlast(S00_AXI_1_WLAST),
.m_axi_wready(S00_AXI_1_WREADY),
.m_axi_wstrb(S00_AXI_1_WSTRB),
.m_axi_wvalid(S00_AXI_1_WVALID),
.pci_exp_rxn(xdma_1_pcie_mgt_rxn),
.pci_exp_rxp(xdma_1_pcie_mgt_rxp),
.pci_exp_txn(xdma_1_pcie_mgt_txn),
.pci_exp_txp(xdma_1_pcie_mgt_txp),
.sys_clk(util_ds_buf_0_IBUF_OUT),
.sys_rst_n(pci_reset_1),
.user_lnk_up(xdma_1_user_lnk_up),
.usr_irq_req(1'b0));
Top_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
Top_xlconstant_2_0 xlconstant_2
(.dout(xlconstant_2_dout));
endmodule
module Top_axi_interconnect_0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arburst,
M01_AXI_arcache,
M01_AXI_arlen,
M01_AXI_arlock,
M01_AXI_arprot,
M01_AXI_arqos,
M01_AXI_arready,
M01_AXI_arsize,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awburst,
M01_AXI_awcache,
M01_AXI_awlen,
M01_AXI_awlock,
M01_AXI_awprot,
M01_AXI_awqos,
M01_AXI_awready,
M01_AXI_awsize,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rlast,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wlast,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wvalid,
M03_ACLK,
M03_ARESETN,
M03_AXI_araddr,
M03_AXI_arburst,
M03_AXI_arcache,
M03_AXI_arlen,
M03_AXI_arlock,
M03_AXI_arprot,
M03_AXI_arqos,
M03_AXI_arready,
M03_AXI_arsize,
M03_AXI_arvalid,
M03_AXI_awaddr,
M03_AXI_awburst,
M03_AXI_awcache,
M03_AXI_awlen,
M03_AXI_awlock,
M03_AXI_awprot,
M03_AXI_awqos,
M03_AXI_awready,
M03_AXI_awsize,
M03_AXI_awvalid,
M03_AXI_bready,
M03_AXI_bresp,
M03_AXI_bvalid,
M03_AXI_rdata,
M03_AXI_rlast,
M03_AXI_rready,
M03_AXI_rresp,
M03_AXI_rvalid,
M03_AXI_wdata,
M03_AXI_wlast,
M03_AXI_wready,
M03_AXI_wstrb,
M03_AXI_wvalid,
M04_ACLK,
M04_ARESETN,
M04_AXI_araddr,
M04_AXI_arburst,
M04_AXI_arcache,
M04_AXI_arlen,
M04_AXI_arlock,
M04_AXI_arprot,
M04_AXI_arready,
M04_AXI_arsize,
M04_AXI_arvalid,
M04_AXI_awaddr,
M04_AXI_awburst,
M04_AXI_awcache,
M04_AXI_awlen,
M04_AXI_awlock,
M04_AXI_awprot,
M04_AXI_awready,
M04_AXI_awsize,
M04_AXI_awvalid,
M04_AXI_bready,
M04_AXI_bresp,
M04_AXI_bvalid,
M04_AXI_rdata,
M04_AXI_rlast,
M04_AXI_rready,
M04_AXI_rresp,
M04_AXI_rvalid,
M04_AXI_wdata,
M04_AXI_wlast,
M04_AXI_wready,
M04_AXI_wstrb,
M04_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input [7:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output M00_AXI_wvalid;
input M01_ACLK;
input [7:0]M01_ARESETN;
output [30:0]M01_AXI_araddr;
output [1:0]M01_AXI_arburst;
output [3:0]M01_AXI_arcache;
output [7:0]M01_AXI_arlen;
output M01_AXI_arlock;
output [2:0]M01_AXI_arprot;
output [3:0]M01_AXI_arqos;
input M01_AXI_arready;
output [2:0]M01_AXI_arsize;
output M01_AXI_arvalid;
output [30:0]M01_AXI_awaddr;
output [1:0]M01_AXI_awburst;
output [3:0]M01_AXI_awcache;
output [7:0]M01_AXI_awlen;
output M01_AXI_awlock;
output [2:0]M01_AXI_awprot;
output [3:0]M01_AXI_awqos;
input M01_AXI_awready;
output [2:0]M01_AXI_awsize;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [511:0]M01_AXI_rdata;
input M01_AXI_rlast;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [511:0]M01_AXI_wdata;
output M01_AXI_wlast;
input M01_AXI_wready;
output [63:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [7:0]M02_ARESETN;
output [31:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [31:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output M02_AXI_wvalid;
input M03_ACLK;
input [7:0]M03_ARESETN;
output [30:0]M03_AXI_araddr;
output [1:0]M03_AXI_arburst;
output [3:0]M03_AXI_arcache;
output [7:0]M03_AXI_arlen;
output M03_AXI_arlock;
output [2:0]M03_AXI_arprot;
output [3:0]M03_AXI_arqos;
input M03_AXI_arready;
output [2:0]M03_AXI_arsize;
output M03_AXI_arvalid;
output [30:0]M03_AXI_awaddr;
output [1:0]M03_AXI_awburst;
output [3:0]M03_AXI_awcache;
output [7:0]M03_AXI_awlen;
output M03_AXI_awlock;
output [2:0]M03_AXI_awprot;
output [3:0]M03_AXI_awqos;
input M03_AXI_awready;
output [2:0]M03_AXI_awsize;
output M03_AXI_awvalid;
output M03_AXI_bready;
input [1:0]M03_AXI_bresp;
input M03_AXI_bvalid;
input [511:0]M03_AXI_rdata;
input M03_AXI_rlast;
output M03_AXI_rready;
input [1:0]M03_AXI_rresp;
input M03_AXI_rvalid;
output [511:0]M03_AXI_wdata;
output M03_AXI_wlast;
input M03_AXI_wready;
output [63:0]M03_AXI_wstrb;
output M03_AXI_wvalid;
input M04_ACLK;
input M04_ARESETN;
output [12:0]M04_AXI_araddr;
output [1:0]M04_AXI_arburst;
output [3:0]M04_AXI_arcache;
output [7:0]M04_AXI_arlen;
output M04_AXI_arlock;
output [2:0]M04_AXI_arprot;
input M04_AXI_arready;
output [2:0]M04_AXI_arsize;
output M04_AXI_arvalid;
output [12:0]M04_AXI_awaddr;
output [1:0]M04_AXI_awburst;
output [3:0]M04_AXI_awcache;
output [7:0]M04_AXI_awlen;
output M04_AXI_awlock;
output [2:0]M04_AXI_awprot;
input M04_AXI_awready;
output [2:0]M04_AXI_awsize;
output M04_AXI_awvalid;
output M04_AXI_bready;
input [1:0]M04_AXI_bresp;
input M04_AXI_bvalid;
input [31:0]M04_AXI_rdata;
input M04_AXI_rlast;
output M04_AXI_rready;
input [1:0]M04_AXI_rresp;
input M04_AXI_rvalid;
output [31:0]M04_AXI_wdata;
output M04_AXI_wlast;
input M04_AXI_wready;
output [3:0]M04_AXI_wstrb;
output M04_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [63:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [3:0]S00_AXI_arid;
input [7:0]S00_AXI_arlen;
input [0:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [63:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [3:0]S00_AXI_awid;
input [7:0]S00_AXI_awlen;
input [0:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [3:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [63:0]S00_AXI_rdata;
output [3:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [63:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [7:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [7:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [7:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [7:0]M02_ARESETN_1;
wire M03_ACLK_1;
wire [7:0]M03_ARESETN_1;
wire M04_ACLK_1;
wire M04_ARESETN_1;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire axi_interconnect_0_ACLK_net;
wire axi_interconnect_0_ARESETN_net;
wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARID;
wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN;
wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;
wire axi_interconnect_0_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;
wire axi_interconnect_0_to_s00_couplers_ARVALID;
wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWID;
wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN;
wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;
wire axi_interconnect_0_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;
wire axi_interconnect_0_to_s00_couplers_AWVALID;
wire [3:0]axi_interconnect_0_to_s00_couplers_BID;
wire axi_interconnect_0_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;
wire axi_interconnect_0_to_s00_couplers_BVALID;
wire [63:0]axi_interconnect_0_to_s00_couplers_RDATA;
wire [3:0]axi_interconnect_0_to_s00_couplers_RID;
wire axi_interconnect_0_to_s00_couplers_RLAST;
wire axi_interconnect_0_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;
wire axi_interconnect_0_to_s00_couplers_RVALID;
wire [63:0]axi_interconnect_0_to_s00_couplers_WDATA;
wire axi_interconnect_0_to_s00_couplers_WLAST;
wire axi_interconnect_0_to_s00_couplers_WREADY;
wire [7:0]axi_interconnect_0_to_s00_couplers_WSTRB;
wire axi_interconnect_0_to_s00_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_interconnect_0_ARADDR;
wire m00_couplers_to_axi_interconnect_0_ARREADY;
wire m00_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m00_couplers_to_axi_interconnect_0_AWADDR;
wire m00_couplers_to_axi_interconnect_0_AWREADY;
wire m00_couplers_to_axi_interconnect_0_AWVALID;
wire m00_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP;
wire m00_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m00_couplers_to_axi_interconnect_0_RDATA;
wire m00_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP;
wire m00_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m00_couplers_to_axi_interconnect_0_WDATA;
wire m00_couplers_to_axi_interconnect_0_WREADY;
wire m00_couplers_to_axi_interconnect_0_WVALID;
wire [30:0]m01_couplers_to_axi_interconnect_0_ARADDR;
wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST;
wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE;
wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN;
wire m01_couplers_to_axi_interconnect_0_ARLOCK;
wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;
wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS;
wire m01_couplers_to_axi_interconnect_0_ARREADY;
wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE;
wire m01_couplers_to_axi_interconnect_0_ARVALID;
wire [30:0]m01_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE;
wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN;
wire m01_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;
wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS;
wire m01_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE;
wire m01_couplers_to_axi_interconnect_0_AWVALID;
wire m01_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;
wire m01_couplers_to_axi_interconnect_0_BVALID;
wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA;
wire m01_couplers_to_axi_interconnect_0_RLAST;
wire m01_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;
wire m01_couplers_to_axi_interconnect_0_RVALID;
wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA;
wire m01_couplers_to_axi_interconnect_0_WLAST;
wire m01_couplers_to_axi_interconnect_0_WREADY;
wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB;
wire m01_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_ARADDR;
wire m02_couplers_to_axi_interconnect_0_ARREADY;
wire m02_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_AWADDR;
wire m02_couplers_to_axi_interconnect_0_AWREADY;
wire m02_couplers_to_axi_interconnect_0_AWVALID;
wire m02_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;
wire m02_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_RDATA;
wire m02_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;
wire m02_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_WDATA;
wire m02_couplers_to_axi_interconnect_0_WREADY;
wire m02_couplers_to_axi_interconnect_0_WVALID;
wire [30:0]m03_couplers_to_axi_interconnect_0_ARADDR;
wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST;
wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE;
wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN;
wire m03_couplers_to_axi_interconnect_0_ARLOCK;
wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;
wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS;
wire m03_couplers_to_axi_interconnect_0_ARREADY;
wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE;
wire m03_couplers_to_axi_interconnect_0_ARVALID;
wire [30:0]m03_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE;
wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN;
wire m03_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;
wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS;
wire m03_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE;
wire m03_couplers_to_axi_interconnect_0_AWVALID;
wire m03_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;
wire m03_couplers_to_axi_interconnect_0_BVALID;
wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA;
wire m03_couplers_to_axi_interconnect_0_RLAST;
wire m03_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;
wire m03_couplers_to_axi_interconnect_0_RVALID;
wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA;
wire m03_couplers_to_axi_interconnect_0_WLAST;
wire m03_couplers_to_axi_interconnect_0_WREADY;
wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB;
wire m03_couplers_to_axi_interconnect_0_WVALID;
wire [12:0]m04_couplers_to_axi_interconnect_0_ARADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_ARBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARCACHE;
wire [7:0]m04_couplers_to_axi_interconnect_0_ARLEN;
wire m04_couplers_to_axi_interconnect_0_ARLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARPROT;
wire m04_couplers_to_axi_interconnect_0_ARREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARSIZE;
wire m04_couplers_to_axi_interconnect_0_ARVALID;
wire [12:0]m04_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWCACHE;
wire [7:0]m04_couplers_to_axi_interconnect_0_AWLEN;
wire m04_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWPROT;
wire m04_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWSIZE;
wire m04_couplers_to_axi_interconnect_0_AWVALID;
wire m04_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_BRESP;
wire m04_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_RDATA;
wire m04_couplers_to_axi_interconnect_0_RLAST;
wire m04_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_RRESP;
wire m04_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_WDATA;
wire m04_couplers_to_axi_interconnect_0_WLAST;
wire m04_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m04_couplers_to_axi_interconnect_0_WSTRB;
wire m04_couplers_to_axi_interconnect_0_WVALID;
wire [63:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [63:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [511:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [511:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [63:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [63:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [63:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [511:0]xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [511:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [63:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [127:64]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [127:64]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [511:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [1023:512]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [127:64]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [191:128]xbar_to_m02_couplers_ARADDR;
wire [5:4]xbar_to_m02_couplers_ARBURST;
wire [11:8]xbar_to_m02_couplers_ARCACHE;
wire [23:16]xbar_to_m02_couplers_ARLEN;
wire [2:2]xbar_to_m02_couplers_ARLOCK;
wire [8:6]xbar_to_m02_couplers_ARPROT;
wire [11:8]xbar_to_m02_couplers_ARQOS;
wire xbar_to_m02_couplers_ARREADY;
wire [11:8]xbar_to_m02_couplers_ARREGION;
wire [8:6]xbar_to_m02_couplers_ARSIZE;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [191:128]xbar_to_m02_couplers_AWADDR;
wire [5:4]xbar_to_m02_couplers_AWBURST;
wire [11:8]xbar_to_m02_couplers_AWCACHE;
wire [23:16]xbar_to_m02_couplers_AWLEN;
wire [2:2]xbar_to_m02_couplers_AWLOCK;
wire [8:6]xbar_to_m02_couplers_AWPROT;
wire [11:8]xbar_to_m02_couplers_AWQOS;
wire xbar_to_m02_couplers_AWREADY;
wire [11:8]xbar_to_m02_couplers_AWREGION;
wire [8:6]xbar_to_m02_couplers_AWSIZE;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [511:0]xbar_to_m02_couplers_RDATA;
wire xbar_to_m02_couplers_RLAST;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [1535:1024]xbar_to_m02_couplers_WDATA;
wire [2:2]xbar_to_m02_couplers_WLAST;
wire xbar_to_m02_couplers_WREADY;
wire [191:128]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [255:192]xbar_to_m03_couplers_ARADDR;
wire [7:6]xbar_to_m03_couplers_ARBURST;
wire [15:12]xbar_to_m03_couplers_ARCACHE;
wire [31:24]xbar_to_m03_couplers_ARLEN;
wire [3:3]xbar_to_m03_couplers_ARLOCK;
wire [11:9]xbar_to_m03_couplers_ARPROT;
wire [15:12]xbar_to_m03_couplers_ARQOS;
wire xbar_to_m03_couplers_ARREADY;
wire [15:12]xbar_to_m03_couplers_ARREGION;
wire [11:9]xbar_to_m03_couplers_ARSIZE;
wire [3:3]xbar_to_m03_couplers_ARVALID;
wire [255:192]xbar_to_m03_couplers_AWADDR;
wire [7:6]xbar_to_m03_couplers_AWBURST;
wire [15:12]xbar_to_m03_couplers_AWCACHE;
wire [31:24]xbar_to_m03_couplers_AWLEN;
wire [3:3]xbar_to_m03_couplers_AWLOCK;
wire [11:9]xbar_to_m03_couplers_AWPROT;
wire [15:12]xbar_to_m03_couplers_AWQOS;
wire xbar_to_m03_couplers_AWREADY;
wire [15:12]xbar_to_m03_couplers_AWREGION;
wire [11:9]xbar_to_m03_couplers_AWSIZE;
wire [3:3]xbar_to_m03_couplers_AWVALID;
wire [3:3]xbar_to_m03_couplers_BREADY;
wire [1:0]xbar_to_m03_couplers_BRESP;
wire xbar_to_m03_couplers_BVALID;
wire [511:0]xbar_to_m03_couplers_RDATA;
wire xbar_to_m03_couplers_RLAST;
wire [3:3]xbar_to_m03_couplers_RREADY;
wire [1:0]xbar_to_m03_couplers_RRESP;
wire xbar_to_m03_couplers_RVALID;
wire [2047:1536]xbar_to_m03_couplers_WDATA;
wire [3:3]xbar_to_m03_couplers_WLAST;
wire xbar_to_m03_couplers_WREADY;
wire [255:192]xbar_to_m03_couplers_WSTRB;
wire [3:3]xbar_to_m03_couplers_WVALID;
wire [319:256]xbar_to_m04_couplers_ARADDR;
wire [9:8]xbar_to_m04_couplers_ARBURST;
wire [19:16]xbar_to_m04_couplers_ARCACHE;
wire [39:32]xbar_to_m04_couplers_ARLEN;
wire [4:4]xbar_to_m04_couplers_ARLOCK;
wire [14:12]xbar_to_m04_couplers_ARPROT;
wire [19:16]xbar_to_m04_couplers_ARQOS;
wire xbar_to_m04_couplers_ARREADY;
wire [19:16]xbar_to_m04_couplers_ARREGION;
wire [14:12]xbar_to_m04_couplers_ARSIZE;
wire [4:4]xbar_to_m04_couplers_ARVALID;
wire [319:256]xbar_to_m04_couplers_AWADDR;
wire [9:8]xbar_to_m04_couplers_AWBURST;
wire [19:16]xbar_to_m04_couplers_AWCACHE;
wire [39:32]xbar_to_m04_couplers_AWLEN;
wire [4:4]xbar_to_m04_couplers_AWLOCK;
wire [14:12]xbar_to_m04_couplers_AWPROT;
wire [19:16]xbar_to_m04_couplers_AWQOS;
wire xbar_to_m04_couplers_AWREADY;
wire [19:16]xbar_to_m04_couplers_AWREGION;
wire [14:12]xbar_to_m04_couplers_AWSIZE;
wire [4:4]xbar_to_m04_couplers_AWVALID;
wire [4:4]xbar_to_m04_couplers_BREADY;
wire [1:0]xbar_to_m04_couplers_BRESP;
wire xbar_to_m04_couplers_BVALID;
wire [511:0]xbar_to_m04_couplers_RDATA;
wire xbar_to_m04_couplers_RLAST;
wire [4:4]xbar_to_m04_couplers_RREADY;
wire [1:0]xbar_to_m04_couplers_RRESP;
wire xbar_to_m04_couplers_RVALID;
wire [2559:2048]xbar_to_m04_couplers_WDATA;
wire [4:4]xbar_to_m04_couplers_WLAST;
wire xbar_to_m04_couplers_WREADY;
wire [319:256]xbar_to_m04_couplers_WSTRB;
wire [4:4]xbar_to_m04_couplers_WVALID;
Top_xbar_0 xbar
(.aclk(axi_interconnect_0_ACLK_net),
.aresetn(axi_interconnect_0_ARESETN_net),
.m_axi_araddr({M04_AXI_araddr,M03_AXI_araddr,M02_AXI_araddr,M01_AXI_araddr,M00_AXI_araddr}),
.m_axi_arburst({M04_AXI_arburst,M03_AXI_arburst,M02_AXI_arburst,M01_AXI_arburst,M00_AXI_arburst}),
.m_axi_arcache({M04_AXI_arcache,M03_AXI_arcache,M02_AXI_arcache,M01_AXI_arcache,M00_AXI_arcache}),
.m_axi_arlen({M04_AXI_arlen,M03_AXI_arlen,M02_AXI_arlen,M01_AXI_arlen,M00_AXI_arlen}),
.m_axi_arlock({M04_AXI_arlock,M03_AXI_arlock,M02_AXI_arlock,M01_AXI_arlock,M00_AXI_arlock}),
.m_axi_arprot({M04_AXI_arprot,M03_AXI_arprot,M02_AXI_arprot,M01_AXI_arprot,M00_AXI_arprot}),
.m_axi_arqos({M04_AXI_arqos,M03_AXI_arqos,M02_AXI_arqos,M01_AXI_arqos,M00_AXI_arqos}),
.m_axi_arready({M04_AXI_arready,M03_AXI_arready,M02_AXI_arready,M01_AXI_arready,M00_AXI_arready}),
.m_axi_arregion({M04_AXI_arregion,M03_AXI_arregion,M02_AXI_arregion,M01_AXI_arregion,M00_AXI_arregion}),
.m_axi_arsize({M04_AXI_arsize,M03_AXI_arsize,M02_AXI_arsize,M01_AXI_arsize,M00_AXI_arsize}),
.m_axi_arvalid({M04_AXI_arvalid,M03_AXI_arvalid,M02_AXI_arvalid,M01_AXI_arvalid,M00_AXI_arvalid}),
.m_axi_awaddr({M04_AXI_awaddr,M03_AXI_awaddr,M02_AXI_awaddr,M01_AXI_awaddr,M00_AXI_awaddr}),
.m_axi_awburst({M04_AXI_awburst,M03_AXI_awburst,M02_AXI_awburst,M01_AXI_awburst,M00_AXI_awburst}),
.m_axi_awcache({M04_AXI_awcache,M03_AXI_awcache,M02_AXI_awcache,M01_AXI_awcache,M00_AXI_awcache}),
.m_axi_awlen({M04_AXI_awlen,M03_AXI_awlen,M02_AXI_awlen,M01_AXI_awlen,M00_AXI_awlen}),
.m_axi_awlock({M04_AXI_awlock,M03_AXI_awlock,M02_AXI_awlock,M01_AXI_awlock,M00_AXI_awlock}),
.m_axi_awprot({M04_AXI_awprot,M03_AXI_awprot,M02_AXI_awprot,M01_AXI_awprot,M00_AXI_awprot}),
.m_axi_awqos({M04_AXI_awqos,M03_AXI_awqos,M02_AXI_awqos,M01_AXI_awqos,M00_AXI_awqos}),
.m_axi_awready({M04_AXI_awready,M03_AXI_awready,M02_AXI_awready,M01_AXI_awready,M00_AXI_awready}),
.m_axi_awregion({M04_AXI_awregion,M03_AXI_awregion,M02_AXI_awregion,M01_AXI_awregion,M00_AXI_awregion}),
.m_axi_awsize({M04_AXI_awsize,M03_AXI_awsize,M02_AXI_awsize,M01_AXI_awsize,M00_AXI_awsize}),
.m_axi_awvalid({M04_AXI_awvalid,M03_AXI_awvalid,M02_AXI_awvalid,M01_AXI_awvalid,M00_AXI_awvalid}),
.m_axi_bready({M04_AXI_bready,M03_AXI_bready,M02_AXI_bready,M01_AXI_bready,M00_AXI_bready}),
.m_axi_bresp({M04_AXI_bresp,M03_AXI_bresp,M02_AXI_bresp,M01_AXI_bresp,M00_AXI_bresp}),
.m_axi_bvalid({M04_AXI_bvalid,M03_AXI_bvalid,M02_AXI_bvalid,M01_AXI_bvalid,M00_AXI_bvalid}),
.m_axi_rdata({M04_AXI_rdata,M03_AXI_rdata,M02_AXI_rdata,M01_AXI_rdata,M00_AXI_rdata}),
.m_axi_rlast({M04_AXI_rlast,M03_AXI_rlast,M02_AXI_rlast,M01_AXI_rlast,M00_AXI_rlast}),
.m_axi_rready({M04_AXI_rready,M03_AXI_rready,M02_AXI_rready,M01_AXI_rready,M00_AXI_rready}),
.m_axi_rresp({M04_AXI_rresp,M03_AXI_rresp,M02_AXI_rresp,M01_AXI_rresp,M00_AXI_rresp}),
.m_axi_rvalid({M04_AXI_rvalid,M03_AXI_rvalid,M02_AXI_rvalid,M01_AXI_rvalid,M00_AXI_rvalid}),
.m_axi_wdata({M04_AXI_wdata,M03_AXI_wdata,M02_AXI_wdata,M01_AXI_wdata,M00_AXI_wdata}),
.m_axi_wlast({M04_AXI_wlast,M03_AXI_wlast,M02_AXI_wlast,M01_AXI_wlast,M00_AXI_wlast}),
.m_axi_wready({M04_AXI_wready,M03_AXI_wready,M02_AXI_wready,M01_AXI_wready,M00_AXI_wready}),
.m_axi_wstrb({M04_AXI_wstrb,M03_AXI_wstrb,M02_AXI_wstrb,M01_AXI_wstrb,M00_AXI_wstrb}),
.m_axi_wvalid({M04_AXI_wvalid,M03_AXI_wvalid,M02_AXI_wvalid,M01_AXI_wvalid,M00_AXI_wvalid}),
.s_axi_araddr(S00_AXI_araddr),
.s_axi_arburst(S00_AXI_arburst),
.s_axi_arcache(S00_AXI_arcache),
.s_axi_arlen(S00_AXI_arlen),
.s_axi_arlock(S00_AXI_arlock),
.s_axi_arprot(S00_AXI_arprot),
.s_axi_arqos(S00_AXI_arqos),
.s_axi_arready(S00_AXI_arready),
.s_axi_arsize(S00_AXI_arsize),
.s_axi_arvalid(S00_AXI_arvalid),
.s_axi_awaddr(S00_AXI_awaddr),
.s_axi_awburst(S00_AXI_awburst),
.s_axi_awcache(S00_AXI_awcache),
.s_axi_awlen(S00_AXI_awlen),
.s_axi_awlock(S00_AXI_awlock),
.s_axi_awprot(S00_AXI_awprot),
.s_axi_awqos(S00_AXI_awqos),
.s_axi_awready(S00_AXI_awready),
.s_axi_awsize(S00_AXI_awsize),
.s_axi_awvalid(S00_AXI_awvalid),
.s_axi_bready(S00_AXI_bready),
.s_axi_bresp(S00_AXI_bresp),
.s_axi_bvalid(S00_AXI_bvalid),
.s_axi_rdata(S00_AXI_rdata),
.s_axi_rlast(S00_AXI_rlast),
.s_axi_rready(S00_AXI_rready),
.s_axi_rresp(S00_AXI_rresp),
.s_axi_rvalid(S00_AXI_rvalid),
.s_axi_wdata(S00_AXI_wdata),
.s_axi_wlast(S00_AXI_wlast),
.s_axi_wready(S00_AXI_wready),
.s_axi_wstrb(S00_AXI_wstrb),
.s_axi_wvalid(S00_AXI_wvalid));
endmodule
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