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xc7k480t/nitefury_pcie_xdma_ddr/project/sources/Top.bda

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<?xml version="1.0" encoding="utf-8"?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
<key id="LT" for="node" attr.name="lock_type" attr.type="string"/>
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
<key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/>
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="BA">0x0000000100100000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000001001FFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c1_s_axi_ctrl_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S1_AXI_CTRL</data>
<data key="MM">c1_s_axi_ctrl_memmap</data>
<data key="SS">c1_s_axi_ctrl_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<node id="n1">
<data key="BA">0x0000000000000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x000000007FFFFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c1_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S1_AXI</data>
<data key="MM">c1_memmap</data>
<data key="SS">c1_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">memory</data>
<data key="VT">AC</data>
</node>
<node id="n2">
<data key="BA">0x0000000200000000</data>
<data key="BP">C_S_AXI_BASEADDR</data>
<data key="HA">0x0000000200001FFF</data>
<data key="HP">C_S_AXI_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_axi_bram_ctrl_0_Mem0</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/axi_bram_ctrl_0</data>
<data key="SI">S_AXI</data>
<data key="SS">Mem0</data>
<data key="SV">xilinx.com:ip:axi_bram_ctrl:4.1</data>
<data key="TU">memory</data>
<data key="VT">AC</data>
</node>
<node id="n3">
<data key="VM">Top</data>
<data key="VT">BC</data>
</node>
<node id="n4">
<data key="VH">2</data>
<data key="VM">Top</data>
<data key="VT">VR</data>
</node>
<node id="n5">
<data key="BA">0x0000000080000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000000FFFFFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c0_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S0_AXI</data>
<data key="MM">c0_memmap</data>
<data key="SS">c0_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">memory</data>
<data key="VT">AC</data>
</node>
<node id="n6">
<data key="BA">0x0000000100000000</data>
<data key="BP">C_BASEADDR</data>
<data key="HA">0x00000001000FFFFF</data>
<data key="HP">C_HIGHADDR</data>
<data key="MA">M_AXI</data>
<data key="MX">/xdma_1</data>
<data key="MI">M_AXI</data>
<data key="MS">SEG_mig_7series_1_c0_s_axi_ctrl_memaddr</data>
<data key="MV">xilinx.com:ip:xdma:4.1</data>
<data key="TM">both</data>
<data key="SX">/mig_7series_1</data>
<data key="SI">S0_AXI_CTRL</data>
<data key="MM">c0_s_axi_ctrl_memmap</data>
<data key="SS">c0_s_axi_ctrl_memaddr</data>
<data key="SV">xilinx.com:ip:mig_7series:4.2</data>
<data key="TU">register</data>
<data key="VT">AC</data>
</node>
<node id="n7">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n3" target="n4"/>
<edge id="e1" source="n4" target="n7"/>
<edge id="e2" source="n2" target="n7">
<data key="EH">2</data>
</edge>
<edge id="e3" source="n5" target="n7">
<data key="EH">2</data>
</edge>
<edge id="e4" source="n6" target="n7">
<data key="EH">2</data>
</edge>
<edge id="e5" source="n1" target="n7">
<data key="EH">2</data>
</edge>
<edge id="e6" source="n0" target="n7">
<data key="EH">2</data>
</edge>
</graph>
</graphml>
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