197 lines
4.9 KiB
Verilog
197 lines
4.9 KiB
Verilog
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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//Date : Wed Apr 24 10:52:27 2019
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//Host : dr-lt2 running 64-bit major release (build 9200)
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//Command : generate_target Top_wrapper.bd
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//Design : Top_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module Top_wrapper
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(DDR3_addr,
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DDR3_ba,
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DDR3_cas_n,
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DDR3_ck_n,
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DDR3_ck_p,
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DDR3_cke,
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DDR3_dm,
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DDR3_dq,
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DDR3_dqs_n,
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DDR3_dqs_p,
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DDR3_odt,
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DDR3_ras_n,
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DDR3_reset_n,
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DDR3_we_n,
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LED_A1,
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LED_A2,
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LED_A3,
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LED_A4,
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SPI_0_io0_io,
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SPI_0_io1_io,
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SPI_0_io2_io,
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SPI_0_io3_io,
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SPI_0_ss_i,
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SPI_0_ss_t,
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pci_reset,
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pcie_clkin_clk_n,
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pcie_clkin_clk_p,
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pcie_clkreq_l,
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pcie_mgt_rxn,
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pcie_mgt_rxp,
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pcie_mgt_txn,
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pcie_mgt_txp,
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real_spi_ss,
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sys_clk_clk_n,
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sys_clk_clk_p);
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output [14:0]DDR3_addr;
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output [2:0]DDR3_ba;
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output DDR3_cas_n;
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output [0:0]DDR3_ck_n;
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output [0:0]DDR3_ck_p;
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output [0:0]DDR3_cke;
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output [1:0]DDR3_dm;
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inout [15:0]DDR3_dq;
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inout [1:0]DDR3_dqs_n;
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inout [1:0]DDR3_dqs_p;
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output [0:0]DDR3_odt;
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output DDR3_ras_n;
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output DDR3_reset_n;
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output DDR3_we_n;
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output [0:0]LED_A1;
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output [0:0]LED_A2;
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output [0:0]LED_A3;
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output [0:0]LED_A4;
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inout SPI_0_io0_io;
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inout SPI_0_io1_io;
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inout SPI_0_io2_io;
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inout SPI_0_io3_io;
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input [0:0]SPI_0_ss_i;
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output SPI_0_ss_t;
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input pci_reset;
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input [0:0]pcie_clkin_clk_n;
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input [0:0]pcie_clkin_clk_p;
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output [0:0]pcie_clkreq_l;
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input [3:0]pcie_mgt_rxn;
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input [3:0]pcie_mgt_rxp;
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output [3:0]pcie_mgt_txn;
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output [3:0]pcie_mgt_txp;
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output [0:0]real_spi_ss;
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input sys_clk_clk_n;
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input sys_clk_clk_p;
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wire [14:0]DDR3_addr;
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wire [2:0]DDR3_ba;
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wire DDR3_cas_n;
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wire [0:0]DDR3_ck_n;
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wire [0:0]DDR3_ck_p;
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wire [0:0]DDR3_cke;
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wire [1:0]DDR3_dm;
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wire [15:0]DDR3_dq;
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wire [1:0]DDR3_dqs_n;
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wire [1:0]DDR3_dqs_p;
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wire [0:0]DDR3_odt;
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wire DDR3_ras_n;
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wire DDR3_reset_n;
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wire DDR3_we_n;
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wire [0:0]LED_A1;
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wire [0:0]LED_A2;
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wire [0:0]LED_A3;
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wire [0:0]LED_A4;
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wire SPI_0_io0_i;
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wire SPI_0_io0_io;
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wire SPI_0_io0_o;
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wire SPI_0_io0_t;
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wire SPI_0_io1_i;
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wire SPI_0_io1_io;
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wire SPI_0_io1_o;
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wire SPI_0_io1_t;
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wire SPI_0_io2_i;
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wire SPI_0_io2_io;
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wire SPI_0_io2_o;
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wire SPI_0_io2_t;
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wire SPI_0_io3_i;
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wire SPI_0_io3_io;
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wire SPI_0_io3_o;
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wire SPI_0_io3_t;
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wire [0:0]SPI_0_ss_i;
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wire SPI_0_ss_t;
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wire pci_reset;
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wire [0:0]pcie_clkin_clk_n;
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wire [0:0]pcie_clkin_clk_p;
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wire [0:0]pcie_clkreq_l;
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wire [3:0]pcie_mgt_rxn;
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wire [3:0]pcie_mgt_rxp;
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wire [3:0]pcie_mgt_txn;
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wire [3:0]pcie_mgt_txp;
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wire [0:0]real_spi_ss;
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wire sys_clk_clk_n;
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wire sys_clk_clk_p;
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IOBUF SPI_0_io0_iobuf
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(.I(SPI_0_io0_o),
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.IO(SPI_0_io0_io),
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.O(SPI_0_io0_i),
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.T(SPI_0_io0_t));
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IOBUF SPI_0_io1_iobuf
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(.I(SPI_0_io1_o),
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.IO(SPI_0_io1_io),
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.O(SPI_0_io1_i),
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.T(SPI_0_io1_t));
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IOBUF SPI_0_io2_iobuf
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(.I(SPI_0_io2_o),
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.IO(SPI_0_io2_io),
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.O(SPI_0_io2_i),
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.T(SPI_0_io2_t));
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IOBUF SPI_0_io3_iobuf
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(.I(SPI_0_io3_o),
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.IO(SPI_0_io3_io),
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.O(SPI_0_io3_i),
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.T(SPI_0_io3_t));
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Top Top_i
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(.DDR3_addr(DDR3_addr),
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.DDR3_ba(DDR3_ba),
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.DDR3_cas_n(DDR3_cas_n),
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.DDR3_ck_n(DDR3_ck_n),
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.DDR3_ck_p(DDR3_ck_p),
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.DDR3_cke(DDR3_cke),
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.DDR3_dm(DDR3_dm),
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.DDR3_dq(DDR3_dq),
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.DDR3_dqs_n(DDR3_dqs_n),
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.DDR3_dqs_p(DDR3_dqs_p),
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.DDR3_odt(DDR3_odt),
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.DDR3_ras_n(DDR3_ras_n),
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.DDR3_reset_n(DDR3_reset_n),
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.DDR3_we_n(DDR3_we_n),
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.LED_A1(LED_A1),
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.LED_A2(LED_A2),
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.LED_A3(LED_A3),
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.LED_A4(LED_A4),
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.SPI_0_io0_i(SPI_0_io0_i),
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.SPI_0_io0_o(SPI_0_io0_o),
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.SPI_0_io0_t(SPI_0_io0_t),
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.SPI_0_io1_i(SPI_0_io1_i),
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.SPI_0_io1_o(SPI_0_io1_o),
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.SPI_0_io1_t(SPI_0_io1_t),
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.SPI_0_io2_i(SPI_0_io2_i),
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.SPI_0_io2_o(SPI_0_io2_o),
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.SPI_0_io2_t(SPI_0_io2_t),
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.SPI_0_io3_i(SPI_0_io3_i),
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.SPI_0_io3_o(SPI_0_io3_o),
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.SPI_0_io3_t(SPI_0_io3_t),
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.SPI_0_ss_i(SPI_0_ss_i),
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.SPI_0_ss_t(SPI_0_ss_t),
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.pci_reset(pci_reset),
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.pcie_clkin_clk_n(pcie_clkin_clk_n),
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.pcie_clkin_clk_p(pcie_clkin_clk_p),
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.pcie_clkreq_l(pcie_clkreq_l),
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.pcie_mgt_rxn(pcie_mgt_rxn),
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.pcie_mgt_rxp(pcie_mgt_rxp),
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.pcie_mgt_txn(pcie_mgt_txn),
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.pcie_mgt_txp(pcie_mgt_txp),
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.real_spi_ss(real_spi_ss),
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.sys_clk_clk_n(sys_clk_clk_n),
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.sys_clk_clk_p(sys_clk_clk_p));
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endmodule
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