239 lines
9.2 KiB
VHDL
239 lines
9.2 KiB
VHDL
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- DO NOT MODIFY THIS FILE.
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-- IP VLNV: xilinx.com:ip:xdma:4.1
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-- IP Revision: 20
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-- The following code must appear in the VHDL architecture header.
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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COMPONENT xdma_0
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PORT (
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sys_clk : IN STD_LOGIC;
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sys_rst_n : IN STD_LOGIC;
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user_lnk_up : OUT STD_LOGIC;
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pci_exp_txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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pci_exp_txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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pci_exp_rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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pci_exp_rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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axi_aclk : OUT STD_LOGIC;
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axi_aresetn : OUT STD_LOGIC;
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usr_irq_req : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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usr_irq_ack : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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msix_enable : OUT STD_LOGIC;
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m_axi_awready : IN STD_LOGIC;
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m_axi_wready : IN STD_LOGIC;
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m_axi_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axi_bvalid : IN STD_LOGIC;
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m_axi_arready : IN STD_LOGIC;
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m_axi_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axi_rlast : IN STD_LOGIC;
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m_axi_rvalid : IN STD_LOGIC;
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m_axi_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_awaddr : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axi_awvalid : OUT STD_LOGIC;
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m_axi_awlock : OUT STD_LOGIC;
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m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axi_wlast : OUT STD_LOGIC;
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m_axi_wvalid : OUT STD_LOGIC;
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m_axi_bready : OUT STD_LOGIC;
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m_axi_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_araddr : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axi_arvalid : OUT STD_LOGIC;
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m_axi_arlock : OUT STD_LOGIC;
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m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axi_rready : OUT STD_LOGIC;
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m_axib_awid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_awaddr : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axib_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axib_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axib_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axib_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axib_awvalid : OUT STD_LOGIC;
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m_axib_awready : IN STD_LOGIC;
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m_axib_awlock : OUT STD_LOGIC;
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m_axib_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axib_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axib_wlast : OUT STD_LOGIC;
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m_axib_wvalid : OUT STD_LOGIC;
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m_axib_wready : IN STD_LOGIC;
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m_axib_bid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axib_bvalid : IN STD_LOGIC;
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m_axib_bready : OUT STD_LOGIC;
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m_axib_arid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_araddr : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axib_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axib_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axib_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axib_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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m_axib_arvalid : OUT STD_LOGIC;
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m_axib_arready : IN STD_LOGIC;
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m_axib_arlock : OUT STD_LOGIC;
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m_axib_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_rid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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m_axib_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
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m_axib_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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m_axib_rlast : IN STD_LOGIC;
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m_axib_rvalid : IN STD_LOGIC;
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m_axib_rready : OUT STD_LOGIC
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);
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : xdma_0
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PORT MAP (
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sys_clk => sys_clk,
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sys_rst_n => sys_rst_n,
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user_lnk_up => user_lnk_up,
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pci_exp_txp => pci_exp_txp,
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pci_exp_txn => pci_exp_txn,
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pci_exp_rxp => pci_exp_rxp,
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pci_exp_rxn => pci_exp_rxn,
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axi_aclk => axi_aclk,
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axi_aresetn => axi_aresetn,
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usr_irq_req => usr_irq_req,
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usr_irq_ack => usr_irq_ack,
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msix_enable => msix_enable,
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m_axi_awready => m_axi_awready,
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m_axi_wready => m_axi_wready,
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m_axi_bid => m_axi_bid,
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m_axi_bresp => m_axi_bresp,
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m_axi_bvalid => m_axi_bvalid,
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m_axi_arready => m_axi_arready,
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m_axi_rid => m_axi_rid,
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m_axi_rdata => m_axi_rdata,
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m_axi_rresp => m_axi_rresp,
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m_axi_rlast => m_axi_rlast,
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m_axi_rvalid => m_axi_rvalid,
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m_axi_awid => m_axi_awid,
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m_axi_awaddr => m_axi_awaddr,
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m_axi_awlen => m_axi_awlen,
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m_axi_awsize => m_axi_awsize,
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m_axi_awburst => m_axi_awburst,
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m_axi_awprot => m_axi_awprot,
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m_axi_awvalid => m_axi_awvalid,
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m_axi_awlock => m_axi_awlock,
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m_axi_awcache => m_axi_awcache,
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m_axi_wdata => m_axi_wdata,
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m_axi_wstrb => m_axi_wstrb,
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m_axi_wlast => m_axi_wlast,
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m_axi_wvalid => m_axi_wvalid,
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m_axi_bready => m_axi_bready,
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m_axi_arid => m_axi_arid,
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m_axi_araddr => m_axi_araddr,
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m_axi_arlen => m_axi_arlen,
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m_axi_arsize => m_axi_arsize,
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m_axi_arburst => m_axi_arburst,
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m_axi_arprot => m_axi_arprot,
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m_axi_arvalid => m_axi_arvalid,
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m_axi_arlock => m_axi_arlock,
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m_axi_arcache => m_axi_arcache,
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m_axi_rready => m_axi_rready,
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m_axib_awid => m_axib_awid,
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m_axib_awaddr => m_axib_awaddr,
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m_axib_awlen => m_axib_awlen,
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m_axib_awsize => m_axib_awsize,
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m_axib_awburst => m_axib_awburst,
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m_axib_awprot => m_axib_awprot,
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m_axib_awvalid => m_axib_awvalid,
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m_axib_awready => m_axib_awready,
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m_axib_awlock => m_axib_awlock,
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m_axib_awcache => m_axib_awcache,
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m_axib_wdata => m_axib_wdata,
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m_axib_wstrb => m_axib_wstrb,
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m_axib_wlast => m_axib_wlast,
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m_axib_wvalid => m_axib_wvalid,
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m_axib_wready => m_axib_wready,
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m_axib_bid => m_axib_bid,
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m_axib_bresp => m_axib_bresp,
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m_axib_bvalid => m_axib_bvalid,
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m_axib_bready => m_axib_bready,
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m_axib_arid => m_axib_arid,
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m_axib_araddr => m_axib_araddr,
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m_axib_arlen => m_axib_arlen,
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m_axib_arsize => m_axib_arsize,
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m_axib_arburst => m_axib_arburst,
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m_axib_arprot => m_axib_arprot,
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m_axib_arvalid => m_axib_arvalid,
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m_axib_arready => m_axib_arready,
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m_axib_arlock => m_axib_arlock,
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m_axib_arcache => m_axib_arcache,
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m_axib_rid => m_axib_rid,
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m_axib_rdata => m_axib_rdata,
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m_axib_rresp => m_axib_rresp,
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m_axib_rlast => m_axib_rlast,
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m_axib_rvalid => m_axib_rvalid,
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m_axib_rready => m_axib_rready
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);
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-- INST_TAG_END ------ End INSTANTIATION Template ---------
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-- You must compile the wrapper file xdma_0.vhd when simulating
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-- the core, xdma_0. When compiling the wrapper file, be sure to
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-- reference the VHDL simulation library.
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