hdl
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
ip_0
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
ip_1
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
ip_2
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
ip_3
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
ip_4
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
source
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
synth
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_v4_1/hdl/verilog
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0.dcp
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0.veo
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0.vho
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0.xci
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0.xml
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0_board.xdc
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0_sim_netlist.v
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0_sim_netlist.vhdl
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0_stub.v
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |
xdma_0_stub.vhdl
|
Add xdma.
|
2025-05-01 20:15:12 +08:00 |