61441 lines
3.1 MiB
61441 lines
3.1 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>customized_ip</spirit:library>
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<spirit:name>xdma_0</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>CLK.SYS_CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sys_clk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>FREQ_HZ</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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<spirit:vendorExtensions>
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|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PHASE</spirit:name>
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE">0.0</spirit:value>
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<spirit:vendorExtensions>
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|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN"/>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF"/>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_PORT</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_PORT"/>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET"/>
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|
<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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|
</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>INSERT_VIP</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:busInterfaceInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.SYS_CLK" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">true</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:busInterfaceInfo>
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</spirit:vendorExtensions>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>CLK.sys_clk_gt</spirit:name>
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<spirit:displayName>CLK.sys_clk_gt</spirit:displayName>
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<spirit:description>sys_clk_gt interface</spirit:description>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>sys_clk_gt</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>FREQ_HZ</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_HZ">100000000</spirit:value>
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<spirit:vendorExtensions>
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|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.FREQ_TOLERANCE_HZ">0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PHASE</spirit:name>
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.PHASE">0.0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.CLK_DOMAIN"/>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_BUSIF"/>
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|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
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</xilinx:parameterInfo>
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|
</spirit:vendorExtensions>
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|
</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_PORT</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_PORT"/>
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<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
|
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.ASSOCIATED_RESET"/>
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<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>INSERT_VIP</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.SYS_CLK_GT.INSERT_VIP">0</spirit:value>
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|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
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</xilinx:parameterInfo>
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|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
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</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.sys_clk_gt" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:busInterfaceInfo>
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</spirit:vendorExtensions>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>CLK.axi_aclk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>axi_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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|
<spirit:parameters>
|
|
<spirit:parameter>
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|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.ASSOCIATED_BUSIF">M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx</spirit:value>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.ASSOCIATED_RESET">axi_aresetn</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.FREQ_HZ">125000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_ACLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.axi_ctl_aclk</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>axi_ctl_aclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.ASSOCIATED_BUSIF">S_AXI_LITE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.FREQ_HZ">125000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.ASSOCIATED_RESET">axi_ctl_aresetn</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.AXI_CTL_ACLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.axi_ctl_aclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ACLK_LOOPBACK')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RST.axi_aresetn</spirit:name>
|
|
<spirit:displayName>RST.axi_aresetn</spirit:displayName>
|
|
<spirit:description>axi_aresetn interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>axi_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.AXI_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.AXI_ARESETN.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RST.sys_rst_n</spirit:name>
|
|
<spirit:displayName>RST.sys_rst_n</spirit:displayName>
|
|
<spirit:description>sys_rst interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sys_rst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.BOARD.ASSOCIATED_PARAM">SYS_RST_N_BOARD_INTERFACE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>required</xilinx:presence>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TYPE</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.TYPE">PCIE_PERST</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.POLARITY">ACTIVE_LOW</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST_N.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RST.axi_ctl_aresetn</spirit:name>
|
|
<spirit:displayName>RST.axi_ctl_aresetn</spirit:displayName>
|
|
<spirit:description>axi_ctl_aresetn interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>axi_ctl_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.AXI_CTL_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.AXI_CTL_ARESETN.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.axi_ctl_aresetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msi_vec0to31</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msi_vec0to31</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msi_vec0to31</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC0TO31.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC0TO31.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msi_vec0to31" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH'))>1)) and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msi_vec32to63</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msi_vec32to63</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msi_vec32to63</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC32TO63.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSI_VEC32TO63.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msi_vec32to63" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH'))>1)) and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msix_0</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msix_0</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msix_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_0.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_0.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_0" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msix_1</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msix_1</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msix_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_1.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_1.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_1" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msix_2</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msix_2</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msix_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_2.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_2.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_2" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.interrupt_out_msix_3</spirit:name>
|
|
<spirit:displayName>INTERRUPT.interrupt_out_msix_3</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>interrupt_out_msix_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_3.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.INTERRUPT_OUT_MSIX_3.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.interrupt_out_msix_3" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.rd_interrupt</spirit:name>
|
|
<spirit:displayName>INTERRUPT.rd_interrupt</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rd_interrupt</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.RD_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.RD_INTERRUPT.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.rd_interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.wr_interrupt</spirit:name>
|
|
<spirit:displayName>INTERRUPT.wr_interrupt</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>wr_interrupt</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.WR_INTERRUPT.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.WR_INTERRUPT.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.wr_interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>INTERRUPT.ats_pri_en</spirit:name>
|
|
<spirit:displayName>INTERRUPT.ats_pri_en</spirit:displayName>
|
|
<spirit:description>Interrupt interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTERRUPT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ats_pri_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>SENSITIVITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.ATS_PRI_EN.SENSITIVITY">LEVEL_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PortWidth</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.ATS_PRI_EN.PortWidth">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.INTERRUPT.ats_pri_en" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.user_clk</spirit:name>
|
|
<spirit:displayName>CLK.user_clk</spirit:displayName>
|
|
<spirit:description>user_clk interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>user_clk_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_BUSIF">m_axis_cq:s_axis_cc:s_axis_rq:m_axis_rc:pcie4_cxs_rx:pcie4_cxs_tx</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_RESET">user_reset_sd</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.USER_CLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.user_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.core_clk</spirit:name>
|
|
<spirit:displayName>CLK.core_clk</spirit:displayName>
|
|
<spirit:description>core_clk interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>core_clk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_HZ">500000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_BUSIF"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.ASSOCIATED_RESET"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.CORE_CLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.core_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE" && (spirit:decode(id('MODELPARAM_VALUE.ENABLE_MORE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.gt_drp_clk</spirit:name>
|
|
<spirit:displayName>CLK.gt_drp_clk</spirit:displayName>
|
|
<spirit:description>gt_drp_clk interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_drp_clk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_HZ">125000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_BUSIF"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.ASSOCIATED_RESET"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.GT_DRP_CLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.gt_drp_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE" && spirit:decode(id('MODELPARAM_VALUE.ENABLE_MORE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RST.user_reset</spirit:name>
|
|
<spirit:displayName>RST.user_reset</spirit:displayName>
|
|
<spirit:description>user_reset interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>user_reset_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.USER_RESET.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXI</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:master>
|
|
<spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI"/>
|
|
</spirit:master>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_ruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">16</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">16</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST.VALUE_SRC</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BURST.VALUE_SRC" spirit:choiceRef="choice_list_9e15bd51">CONSTANT</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0 )">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXI_B</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave>
|
|
<spirit:memoryMapRef spirit:memoryMapRef="S_AXI_B"/>
|
|
</spirit:slave>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREGION</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arregion</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREGION</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awregion</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_ruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axib_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_READ_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_WRITE_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.SUPPORTS_NARROW_BURST" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_SUPPORTS_NARROW_BURST'))" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.DATA_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.PROTOCOL">AXI4LITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ADDR_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_BURST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_LOCK">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_PROT">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_CACHE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_WSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_BRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.HAS_RRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.MAX_BURST_LENGTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_READ_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.NUM_WRITE_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_B.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_B" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXI_BYPASS</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:master>
|
|
<spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_BYPASS"/>
|
|
</spirit:master>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_aruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_ruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_READ_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_WRITE_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_READ_THREADS">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.NUM_WRITE_THREADS">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.DATA_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.PROTOCOL">AXI4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ID_WIDTH">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ADDR_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_LOCK">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_PROT">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_CACHE">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_WSTRB">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_BRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_RRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.MAX_BURST_LENGTH">256</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_BYPASS.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_BYPASS" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXI_B</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:master>
|
|
<spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_B"/>
|
|
</spirit:master>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_aruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axib_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_READ_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_WRITE_OUTSTANDING">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_READ_THREADS">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.NUM_WRITE_THREADS">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.DATA_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.PROTOCOL">AXI4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ID_WIDTH">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ADDR_WIDTH">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_LOCK">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_PROT">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_CACHE">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_WSTRB">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_BRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.HAS_RRESP">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.MAX_BURST_LENGTH">256</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_B.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_B" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXI_LITE</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:master>
|
|
<spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_LITE"/>
|
|
</spirit:master>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_aruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_awuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axil_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.DATA_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ADDR_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BURST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_LOCK">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_PROT">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_CACHE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_WSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_RRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXI_LITE.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXI_LITE" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXI_LITE</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave>
|
|
<spirit:memoryMapRef spirit:memoryMapRef="S_AXI_LITE"/>
|
|
</spirit:slave>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axil_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_LITE" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXIS_C2H_0</spirit:name>
|
|
<spirit:displayName>S_AXIS_C2H_0</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tkeep_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tlast_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tuser_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tvalid_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_0.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXIS_H2C_0</spirit:name>
|
|
<spirit:displayName>M_AXIS_H2C_0</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tkeep_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tlast_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tuser_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tvalid_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_0.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXIS_C2H_1</spirit:name>
|
|
<spirit:displayName>S_AXIS_C2H_1</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tkeep_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tlast_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tuser_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tvalid_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_1.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXIS_H2C_1</spirit:name>
|
|
<spirit:displayName>M_AXIS_H2C_1</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tkeep_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tlast_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tuser_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tvalid_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_1.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXIS_C2H_2</spirit:name>
|
|
<spirit:displayName>S_AXIS_C2H_2</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tkeep_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tlast_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tuser_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tvalid_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_2.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXIS_H2C_2</spirit:name>
|
|
<spirit:displayName>M_AXIS_H2C_2</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tkeep_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tlast_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tuser_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tvalid_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_2.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXIS_C2H_3</spirit:name>
|
|
<spirit:displayName>S_AXIS_C2H_3</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tkeep_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tlast_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tuser_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_c2h_tvalid_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_C2H_3.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXIS_C2H_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>M_AXIS_H2C_3</spirit:name>
|
|
<spirit:displayName>M_AXIS_H2C_3</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tkeep_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tlast_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tuser_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_h2c_tvalid_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_H2C_3.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.M_AXIS_H2C_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>m_axis_cq</spirit:name>
|
|
<spirit:displayName>m_axis_cq</spirit:displayName>
|
|
<spirit:description>The Completer Request interface is used to transmit Completion TLP's to the Client Application</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tdata_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tkeep_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tlast_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tready_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tuser_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cq_tvalid_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_CQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_cq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>s_axis_cc</spirit:name>
|
|
<spirit:displayName>s_axis_cc</spirit:displayName>
|
|
<spirit:description>The Completer Completion Interface is used to transmit Completion TLP's</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tdata_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tkeep_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tlast_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tready_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tuser_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cc_tvalid_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_CC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axis_cc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>s_axis_rq</spirit:name>
|
|
<spirit:displayName>s_axis_rq</spirit:displayName>
|
|
<spirit:description>The Requestor Request interface received requests TLP's from the Client Application</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tdata_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tkeep_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tlast_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tready_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tuser_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rq_tvalid_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_RQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axis_rq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>m_axis_rc</spirit:name>
|
|
<spirit:displayName>m_axis_rc</spirit:displayName>
|
|
<spirit:description>The Requestor Completer interface transmits completions to the client application</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tdata_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tkeep_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tlast_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tready_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tuser_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rc_tvalid_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS_RC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axis_rc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_mesg_tx</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_mesg_tx</spirit:displayName>
|
|
<spirit:description>Configuration Transmit Message Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_mesg_tx_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TRANSMIT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_transmit_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TRANSMIT_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_transmit_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TRANSMIT_DONE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_transmit_done_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TRANSMIT_TYPE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_transmit_type_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_mesg_rcvd</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_mesg_rcvd</spirit:displayName>
|
|
<spirit:description>Configuration Received Message Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msg_received_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>recd</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_received_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>recd_data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_received_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>recd_type</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_msg_received_type_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_mesg_rcvd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_status</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_status</spirit:displayName>
|
|
<spirit:description>Configuration Status Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_np_req</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_cq_np_req_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_np_req_count</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_cq_np_req_count_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>current_speed</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_current_speed_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_cor_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_cor_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_fatal_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_fatal_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_nonfatal_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_nonfatal_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_function_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>local_error_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_local_error_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ltssm_state</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ltssm_state_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>max_payload</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_max_payload_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>max_read_req</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_max_read_req_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>negotiated_width</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_negotiated_width_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phy_link_down</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_phy_link_down_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phy_link_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_phy_link_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pl_status_change</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_pl_status_change_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num_vld0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num_vld0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num_vld1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num_vld1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tfc_npd_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_npd_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tfc_nph_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_nph_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_status_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_status</spirit:displayName>
|
|
<spirit:description>Configuration Status Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_status_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_np_req</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_cq_np_req_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_np_req_count</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_cq_np_req_count_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>current_speed</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_current_speed_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_cor_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_cor_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_fatal_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_fatal_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_nonfatal_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_nonfatal_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_function_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>local_error_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_local_error_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ltssm_state</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ltssm_state_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>max_payload</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_max_payload_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>max_read_req</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_max_read_req_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>negotiated_width</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_negotiated_width_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phy_link_down</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_phy_link_down_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phy_link_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_phy_link_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pl_status_change</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_pl_status_change_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num_vld0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num_vld0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_seq_num_vld1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_rq_seq_num_vld1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_status_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_transmit_fc_if</spirit:name>
|
|
<spirit:displayName>pcie4_transmit_fc</spirit:displayName>
|
|
<spirit:description>Transmit Flow Control Interfce</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>npd_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_npd_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>nph_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_nph_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_transmit_fc_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_transmit_fc</spirit:name>
|
|
<spirit:displayName>pcie4_transmit_fc</spirit:displayName>
|
|
<spirit:description>Transmit Flow Control Interfce</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_transmit_fc_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>npd_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_npd_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>nph_av</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie_tfc_nph_av_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_transmit_fc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_rbar</spirit:name>
|
|
<spirit:displayName>pcie4_rbar</spirit:displayName>
|
|
<spirit:description>Resizable bar Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_rbar_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bar_size</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_bar_size_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar2_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar3_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar4_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_bar5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar5_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_rbar" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_control</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_control</spirit:displayName>
|
|
<spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_bus_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_bus_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_device_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_device_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_port_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_port_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsn</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dsn_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_cor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_cor_in_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_uncor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_uncor_in_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>flr_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_flr_done_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>flr_in_process</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_flr_in_process_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>hot_reset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_hot_reset_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>link_training_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_link_training_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_flr_in_process</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_vf_flr_in_process_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_control_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_control</spirit:displayName>
|
|
<spirit:description>It allows a broad range of information exchange between user application and the core</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_control_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>config_space_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_config_space_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_bus_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_bus_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_device_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_device_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ds_port_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ds_port_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsn</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dsn_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_cor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_cor_in_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>err_uncor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_uncor_in_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>flr_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_flr_done_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>flr_in_process</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_flr_in_process_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>hot_reset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_hot_reset_out_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>link_training_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_link_training_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rbar_function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rbar_size</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_bar_size_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_flr_in_process</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_vf_flr_in_process_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar0_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar1_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar2_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar3_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar4_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_enable_rbar5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rbar_write_enable_bar5_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_control_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_fc</spirit:name>
|
|
<spirit:displayName>pcie_cfg_fc</spirit:displayName>
|
|
<spirit:description>Configuration Flow Control INTERFACE</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>NPH</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_fc_nph_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>SEL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_fc_sel_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_fc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_fc</spirit:name>
|
|
<spirit:displayName>pcie_cfg_fc</spirit:displayName>
|
|
<spirit:description>Configuration Flow Control interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc" spirit:version="1.1"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_fc_rtl" spirit:version="1.1"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>NPH</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_fc_nph_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>SEL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_fc_sel_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_fc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_msi</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msi</spirit:displayName>
|
|
<spirit:description>PCIE MSI interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_msi_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>attr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask_update</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_mask_update_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pending_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pending_status_data_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_data_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pending_status_function_num</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_function_num_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_present</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_st_tag</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_type</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msi" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_msix_external</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msix_external</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_external_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_external" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_external_msix_with_msi_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_external_msix_with_msi</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_with_msi_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_external_msix</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_external_msix</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_external_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_msix_internal</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
|
|
<spirit:description>PCIE MSIx Int Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_msix_internal_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>attr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mint_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_present</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_st_tag</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_type</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vec_pending</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vec_pending_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_msix_internal_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msix_internal</spirit:displayName>
|
|
<spirit:description>PCIE MSIx Int Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>attr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mint_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_present</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_st_tag</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tph_type</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vec_pending</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vec_pending_status</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_status_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_msix_internal_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_external_msix_without_msi_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_external_msix_without_msi</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vf_mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_external_msix_without_msi_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cfg_interrupt</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_interrupt</spirit:displayName>
|
|
<spirit:description>PCIE Legacy Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_interrupt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>INTx_VECTOR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_int_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>PENDING</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_pending_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>SENT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_sent_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cfg_interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_mgmt_sd</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
|
|
<spirit:description>PCIE Configuration Management Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_addr_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BYTE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_byte_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEBUG_ACCESS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_type1_cfg_reg_access_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>FUNCTION_NUMBER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_WRITE_DONE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_write_done_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "FALSE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_mgmt_if</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_mgmt</spirit:displayName>
|
|
<spirit:description>PCIE Configuration Management Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie4_cfg_mgmt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_addr_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BYTE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_byte_enable_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEBUG_ACCESS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_type1_cfg_reg_access_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>FUNCTION_NUMBER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_function_number_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_WRITE_DONE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_write_done_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write_data_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.USE_STANDARD_INTERFACES')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_mgmt</spirit:name>
|
|
<spirit:displayName>pcie_cfg_mgmt</spirit:displayName>
|
|
<spirit:description>PCIE Configuration Management Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_mgmt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_cfg_mgmt_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_addr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BYTE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_byte_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>READ_WRITE_DONE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_read_write_done</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TYPE1_CFG_REG_ACCESS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_type1_cfg_reg_access</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WRITE_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_mgmt_write</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_mgmt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_mgt</spirit:name>
|
|
<spirit:displayName>pcie_7x_mgt</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_7x_mgt_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxn</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pci_exp_rxn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxp</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pci_exp_rxp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txn</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pci_exp_txn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txp</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pci_exp_txp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.PCIE_MGT.BOARD.ASSOCIATED_PARAM">PCIE_BOARD_INTERFACE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>required</xilinx:presence>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_mgt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>drp</spirit:name>
|
|
<spirit:displayName>drp</spirit:displayName>
|
|
<spirit:description>DRP interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_addr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DI</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_di</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DO</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_do</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DRDY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_rdy</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DWE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drp_we</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_debug_ports</spirit:name>
|
|
<spirit:displayName>pcie_debug_ports</spirit:displayName>
|
|
<spirit:description>PCIe Debug Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_debug" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_debug_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_current_speed</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_current_speed_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_err_cor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_cor_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_err_fatal</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_fatal_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_err_nonfatal</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_err_nonfatal_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_local_error</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_local_error_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_local_error_valid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_local_error_valid_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_ltssm_state</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ltssm_state_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_negotiated_width</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_negotiated_width_o</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_debug_ports" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_pcie_id</spirit:name>
|
|
<spirit:displayName>pcie4_pcie_id</spirit:displayName>
|
|
<spirit:description>PCIE 4 PCIE ID interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>subsys_vend_id</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_subsys_vend_id</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>vend_id</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_vend_id</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_pcie_id_pf0</spirit:name>
|
|
<spirit:displayName>pcie4_pcie_id_pf0</spirit:displayName>
|
|
<spirit:description>PCIE 4 PCIE ID interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dev_id_pf0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dev_id_pf0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rev_id_pf0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_rev_id_pf0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>subsys_id_pf0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_subsys_id_pf0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 0 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_pcie_id_pf1</spirit:name>
|
|
<spirit:displayName>pcie4_pcie_id_pf1</spirit:displayName>
|
|
<spirit:description>PCIE 4 PCIE ID interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dev_id_pf1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dev_id_pf1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rev_id_pf1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_rev_id_pf1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>subsys_id_pf1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_subsys_id_pf1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_pcie_id_pf2</spirit:name>
|
|
<spirit:displayName>pcie4_pcie_id_pf2</spirit:displayName>
|
|
<spirit:description>PCIE 4 PCIE ID interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dev_id_pf2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dev_id_pf2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rev_id_pf2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_rev_id_pf2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>subsys_id_pf2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_subsys_id_pf2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_pcie_id_pf3</spirit:name>
|
|
<spirit:displayName>pcie4_pcie_id_pf3</spirit:displayName>
|
|
<spirit:description>PCIE 4 PCIE ID interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_pcie_id_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dev_id_pf3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_dev_id_pf3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rev_id_pf3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_rev_id_pf3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>subsys_id_pf3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_subsys_id_pf3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_pcie_id_pf3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_7x_transceiver_debug</spirit:name>
|
|
<spirit:displayName>pcie3_7x_transceiver_debug</spirit:displayName>
|
|
<spirit:description>Transceiver Debug Interface of pcie3_7x</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_7x_transceiver_debug" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_7x_transceiver_debug_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpll_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_cpll_lock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>debug_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_debug_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_dmonitorout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drp_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_drp_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescandataerror</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_eyescandataerror</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gt_ch_drp_rdy</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_ch_drp_rdy</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>loopback</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_loopback</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_qpll_lock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qrst_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_qrst_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qrst_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_qrst_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rate_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rate_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rst_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rst_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxbufstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadet</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxcommadet</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdisperr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxdisperr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxnotintable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxnotintable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmaresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxpmaresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxprbscntreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxprbserr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxsyncdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxsyncdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sync_fsm_rx</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_sync_fsm_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sync_fsm_tx</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_sync_fsm_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txinhibit</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txinhibit</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinitdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txphinitdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txprbsforceerr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_7x_transceiver_debug" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_us_transceiver_debug</spirit:name>
|
|
<spirit:displayName>pcie3_us_transceiver_debug</spirit:displayName>
|
|
<spirit:description>Transceiver Debug Interface of pcie3_us</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_us_transceiver_debug" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie3_us_transceiver_debug_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_bufgtdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpll_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_cplllock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonfiforeset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonfiforeset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonitorclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonitorout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescandataerror</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_eyescandataerror</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtpowergood</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_gtpowergood</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>loopback</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_loopback</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratedone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcieuserratedone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratestart</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcieuserratestart</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phystatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_phystatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_prst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_qpll1lock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcierateidle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rrst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rrst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rst_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rst_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxbufstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrlock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxcdrlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadet</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxcommadet</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxeq_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rxeq_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxoutclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmaresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxpmaresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbscntreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbserr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxrecclkout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxrecclkout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxsyncdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxsyncdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxvalid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txelecidle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txelecidle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_ctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_ctrl</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_preset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_preset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txinhibit</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txinhibit</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinitdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txphinitdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txprbsforceerr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_transceiver_debug" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_us_plus_transceiver_debug</spirit:name>
|
|
<spirit:displayName>pcie4_us_plus_transceiver_debug</spirit:displayName>
|
|
<spirit:description>Transceiver Debug Interface of pcie4_us_plus</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie4_us_plus_transceiver_debug" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie4_us_plus_transceiver_debug_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_bufgtdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpll_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_cplllock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonfiforeset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonfiforeset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonitorclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_dmonitorout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescandataerror</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_eyescandataerror</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gen34_eios_det</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_gen34_eios_det</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtpowergood</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_gtpowergood</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>loopback</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_loopback</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratedone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcieuserratedone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratestart</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcieuserratestart</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phystatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_phystatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>prst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_prst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_qpll0lock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1_lock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_qpll1lock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_pcierateidle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rrst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rrst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rst_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rst_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxbufreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxbufstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrlock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxcdrlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxcdrreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadet</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxcommadet</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfelpmreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxdfelpmreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxeq_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_rxeq_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxoutclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclkfabric</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxoutclkfabric</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclkpcs</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxoutclkpcs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpcsreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxpcsreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmareset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxpmareset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmaresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxpmaresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbscntreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbscntreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbserr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbserr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbslocked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbslocked</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxrecclkout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxrecclkout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxstatus</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxstatus</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxsyncdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxsyncdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxvalid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_rxvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txdlysresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txelecidle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txelecidle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_ctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_ctrl</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txeq_preset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phy_txeq_preset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txinhibit</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txinhibit</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txoutclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclkfabric</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txoutclkfabric</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclkpcs</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txoutclkpcs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpcsreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txpcsreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphaligndone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txphaligndone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinitdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txphinitdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpmareset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txpmareset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpmaresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txpmaresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbsforceerr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txprbsforceerr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbssel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txprbssel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprogdivresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txprogdivresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txresetdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txresetdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncdone</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gt_txsyncdone</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_us_plus_transceiver_debug" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_us_gt_if</spirit:name>
|
|
<spirit:displayName>pcie3_us_gt_if</spirit:displayName>
|
|
<spirit:description>GT Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="pcie3_us_gt_if" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_ultrascale" spirit:name="pcie3_us_gt_if_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtce_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtce_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtcemask_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtcemask_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtdiv_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtdiv_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtreset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtreset_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtrstmask_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtrstmask_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cplllock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cplllock_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpllpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpllpd_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpllreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpllreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonfiforeset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonfiforeset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonitorclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonitorout_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpaddr_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpaddr_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpdi_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpdi_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpdo_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpdo_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drprdy_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drprdy_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpwe_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpwe_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescandataerror_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>eyescandataerror_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescanreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>eyescanreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gthrxn_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gthrxn_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gthrxp_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gthrxp_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gthtxn_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gthtxn_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gthtxp_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gthtxp_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtpowergood_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtpowergood_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrefclk0_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrefclk0_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrefclk01_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrefclk01_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrxreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrxreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gttxreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gttxreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_reset_rx_done_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_reset_rx_done_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_reset_tx_done_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_reset_tx_done_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_userclk_rx_active_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_active_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_reset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_reset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>loopback_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>loopback_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieeqrxeqadaptdone_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierategen3_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierategen3_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateidle_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateidle_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpllpd_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpllpd_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpllreset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpllreset_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierstidle_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierstidle_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pciersttxsyncstart_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pciersttxsyncstart_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pciesynctxsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pciesynctxsyncdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieusergen3rdy_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieusergen3rdy_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserphystatusrst_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserphystatusrst_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratedone_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserratedone_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratestart_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserratestart_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcsrsvdin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcsrsvdin_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcsrsvdout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcsrsvdout_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phystatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phystatus_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0clk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0clk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0refclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0refclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1clk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1clk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1lock_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1outclk_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1outrefclk_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1pd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1pd_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1refclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1refclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1reset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1reset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpllrsvd2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpllrsvd2_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpllrsvd3_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpllrsvd3_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx8b10ben_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx8b10ben_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbufreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufstatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbufstatus_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbyteisaligned_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbyteisaligned_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbyterealign_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbyterealign_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrlock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrlock_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxclkcorcnt_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxclkcorcnt_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadet_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcommadet_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadeten_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcommadeten_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl0_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl0_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl1_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl1_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl2_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl2_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl3_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl3_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdata_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfeagchold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfeagchold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfecfokhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfecfokhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfekhhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfekhhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfelfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfelfhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap2hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap2hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap3hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap3hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap4hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap4hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap5hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap5hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap6hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap6hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap7hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap7hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap8hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap8hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap9hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap9hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap10hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap10hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap11hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap11hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap12hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap12hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap13hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap13hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap14hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap14hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap15hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap15hold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfeuthold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfeuthold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfevphold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfevphold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdlysresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdlysresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxelecidle_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxelecidle_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmgchold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmgchold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmhfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmhfhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmlfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmlfhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmoshold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmoshold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxmcommaalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxmcommaalignen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoshold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoshold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoutclk_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpcommaalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpcommaalignen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpd_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxphaligndone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxphaligndone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmaresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpmaresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpolarity_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpolarity_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbscntreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbscntreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbserr_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbserr_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbslocked_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbslocked_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbssel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbssel_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprgdivresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprgdivresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprogdivreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprogdivreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxrate_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxrate_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxratedone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxratedone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxratemode_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxratemode_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxslide_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxslide_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxstatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxstatus_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxsyncdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxuserrdy_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxuserrdy_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxusrclk2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxusrclk2_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxusrclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxusrclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxvalid_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx8b10ben_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx8b10ben_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl0_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl0_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl1_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl1_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl2_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdata_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdeemph_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdeemph_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdetectrx_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdetectrx_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdiffctrl_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdiffctrl_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlybypass_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlybypass_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyhold_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyovrden_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyovrden_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlysreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlysresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyupdown_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyupdown_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txelecidle_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txelecidle_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txinhibit_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txinhibit_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txmaincursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txmaincursor_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txmargin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txmargin_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclk_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclksel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclksel_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpd_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphalign_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphalign_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphaligndone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphaligndone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphalignen_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlypd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlypd_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlyreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlyreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlytstclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlytstclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinit_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphinit_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinitdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphinitdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphovrden_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphovrden_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpmaresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpmaresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpostcursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpostcursor_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbsforceerr_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprbsforceerr_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbssel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprbssel_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprecursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprecursor_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprgdivresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprgdivresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprogdivreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprogdivreset_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txrate_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txrate_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txresetdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txswing_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txswing_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncallin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncallin_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncdone_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncin_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncmode_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncmode_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncout_us_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txuserrdy_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txuserrdy_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txusrclk2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txusrclk2_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txusrclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txusrclk_us_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_gt_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_gt_if</spirit:name>
|
|
<spirit:displayName>pcie4_gt_if</spirit:displayName>
|
|
<spirit:description>GT Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4" spirit:name="pcie4_gt_if_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtce_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtce_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtcemask_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtcemask_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtdiv_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtdiv_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtreset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtreset_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>bufgtrstmask_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>bufgtrstmask_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpllfreqlock_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpllfreqlock_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cplllock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cplllock_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpllpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpllpd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cpllreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cpllreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonfiforeset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonfiforeset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonitorclk_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dmonitorout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>dmonitorout_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpaddr_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpaddr_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpclk_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpdi_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpdi_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpdo_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpdo_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drprdy_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drprdy_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drprst_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drprst_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>drpwe_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>drpwe_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_int_clock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_int_clock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_pclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_pclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_phy_userclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_phy_userclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_rst_idle</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_rst_idle</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ext_phy_clk_txoutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_phy_clk_txoutclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eyescanreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>eyescanreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtpowergood_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtpowergood_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrefclk0_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrefclk0_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrefclk00_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrefclk00_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrefclk01_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrefclk01_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtrxreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtrxreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gttxreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gttxreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_reset_rx_done_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_reset_rx_done_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_reset_tx_done_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_reset_tx_done_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_userclk_rx_active_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_userclk_rx_active_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_active_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>gtwiz_userclk_tx_active_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>loopback_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>loopback_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieeqrxeqadaptdone_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieeqrxeqadaptdone_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierategen3_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierategen3_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateidle_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateidle_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpll0_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpll0_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpll1_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpll1_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpllpd_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpllpd_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierateqpllreset_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierateqpllreset_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcierstidle_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcierstidle_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pciersttxsyncstart_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pciersttxsyncstart_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pciesynctxsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pciesynctxsyncdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieusergen3rdy_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieusergen3rdy_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserphystatusrst_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserphystatusrst_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratedone_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserratedone_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pcieuserratestart_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcieuserratestart_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>phystatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>phystatus_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0freqlock_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0freqlock_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0lock_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0outclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0outrefclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0pd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0pd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll0reset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll0reset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1freqlock_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1freqlock_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1lock_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1outclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1outrefclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1pd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1pd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpll1reset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll1reset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rcalenb_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rcalenb_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>resetovrd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>resetovrd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx8b10ben_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rx8b10ben_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbufreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbufstatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbufstatus_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbyteisaligned_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbyteisaligned_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxbyterealign_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxbyterealign_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrfreqreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrfreqreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrlock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrlock_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcdrreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcdrreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxclkcorcnt_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxclkcorcnt_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadet_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcommadet_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxcommadeten_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxcommadeten_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl0_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl0_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl1_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl1_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl2_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl2_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxctrl3_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxctrl3_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdata_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfeagchold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfeagchold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfecfokhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfecfokhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfekhhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfekhhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfelfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfelfhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfelpmreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfelpmreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap2hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap2hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap3hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap3hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap4hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap4hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap5hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap5hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap6hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap6hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap7hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap7hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap8hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap8hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap9hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap9hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap10hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap10hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap11hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap11hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap12hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap12hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap13hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap13hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap14hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap14hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfetap15hold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfetap15hold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfeuthold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfeuthold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdfevphold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdfevphold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxdlysresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxdlysresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxelecidle_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxelecidle_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmgchold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmgchold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmhfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmhfhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmlfhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmlfhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxlpmoshold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxlpmoshold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxmcommaalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxmcommaalignen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoshold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoshold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoutclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclkfabric_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoutclkfabric_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclkpcs_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxoutclkpcs_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpcommaalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpcommaalignen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpcsreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpcsreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxphaligndone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxphaligndone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmareset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpmareset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpmaresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpmaresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxpolarity_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxpolarity_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbscntreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbscntreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbserr_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbserr_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbslocked_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbslocked_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprbssel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprbssel_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxprogdivreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxprogdivreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxrate_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxrate_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxratedone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxratedone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxratemode_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxratemode_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxrecclkout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxrecclkout_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxslide_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxslide_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxstatus_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxstatus_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxsyncdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxtermination_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxtermination_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxuserrdy_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxuserrdy_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxusrclk2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxusrclk2_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxusrclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxusrclk_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>rxvalid_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx8b10ben_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>tx8b10ben_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl0_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl0_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl1_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl1_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txctrl2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txctrl2_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdata_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdata_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdeemph_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdeemph_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdetectrx_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdetectrx_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdiffctrl_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdiffctrl_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlybypass_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlybypass_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyhold_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyhold_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyovrden_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyovrden_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlysreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlysresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlysresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txdlyupdown_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txdlyupdown_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txelecidle_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txelecidle_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txmaincursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txmaincursor_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txmargin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txmargin_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclk_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclkfabric_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclkfabric_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclkpcs_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclkpcs_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclksel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txoutclksel_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpcsreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpcsreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpdelecidlemode_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpdelecidlemode_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphalign_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphalign_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphaligndone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphaligndone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphalignen_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphalignen_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlypd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlypd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlyreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlyreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphdlytstclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphdlytstclk_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinit_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphinit_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphinitdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphinitdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txphovrden_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txphovrden_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpisopd_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpisopd_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpmareset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpmareset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpmaresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpmaresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txpostcursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txpostcursor_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbsforceerr_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprbsforceerr_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprbssel_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprbssel_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprecursor_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprecursor_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprgdivresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprgdivresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txprogdivreset_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txprogdivreset_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txrate_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txrate_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txresetdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txresetdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txswing_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txswing_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncallin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncallin_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncdone_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncdone_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncin_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncin_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncmode_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncmode_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txsyncout_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txsyncout_usp_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txuserrdy_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txuserrdy_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txusrclk2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txusrclk2_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txusrclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>txusrclk_usp_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_gt_if" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_ext_ch_gt</spirit:name>
|
|
<spirit:displayName>pcie_ext_ch_gt</spirit:displayName>
|
|
<spirit:description>GT DRP interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DI</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpdi</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DO</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpdo</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DRDY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drprdy</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DWE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpwe</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_ch_gt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_ext</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_ext</spirit:displayName>
|
|
<spirit:description>Configuration Extend Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie3_cfg_ext_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>function_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_function_number</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>read_data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_read_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>read_data_valid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_read_data_valid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>read_received</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_read_received</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>register_number</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_register_number</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_byte_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_write_byte_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_write_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>write_received</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_ext_write_received</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_ext" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.ext_ch_gt_drpclk</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_ch_gt_drpclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.ASSOCIATED_BUSIF">pcie_ext_ch_gt</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.FREQ_HZ">100000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.ASSOCIATED_RESET"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.EXT_CH_GT_DRPCLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.ext_ch_gt_drpclk" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_ext_pipe_rp_usp</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_rp_usp</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_rp_usp" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_ext_pipe_ep_usp</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_ep_usp</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_ep_usp" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_ext_pipe_ep_legacy_usp</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_ep_legacy_usp</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_8</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_8_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_9</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_9_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_10</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_10_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_11</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_11_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_12</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_12_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_13</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_13_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_14</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_14_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_15</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_15_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_ext_pipe_ep_legacy_usp" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_ext_pipe_rp</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_rp</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_rp" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_ext_pipe_ep</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_ep</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_ep" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_ext_pipe_ep_legacy</spirit:name>
|
|
<spirit:displayName>pcie3_ext_pipe_ep_legacy</spirit:displayName>
|
|
<spirit:description>PCIE3 External PIPE Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_ext_pipe_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_IN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>COMMANDS_OUT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_4</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_5</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_6</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TX_7</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_ext_pipe_ep_legacy" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.DEV_PORT_TYPE')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_c2h_0</spirit:name>
|
|
<spirit:displayName>dsc_bypass_c2h_0</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ctl_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_len_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_load_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_src_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_c2h_1</spirit:name>
|
|
<spirit:displayName>dsc_bypass_c2h_1</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ctl_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_len_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_load_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_src_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_c2h_2</spirit:name>
|
|
<spirit:displayName>dsc_bypass_c2h_2</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ctl_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_len_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_load_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_src_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_c2h_3</spirit:name>
|
|
<spirit:displayName>dsc_bypass_c2h_3</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ctl_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_len_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_load_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_dsc_byp_src_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_c2h_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_h2c_0</spirit:name>
|
|
<spirit:displayName>dsc_bypass_h2c_0</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ctl_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_len_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_load_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_src_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_h2c_1</spirit:name>
|
|
<spirit:displayName>dsc_bypass_h2c_1</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ctl_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_len_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_load_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_src_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_h2c_2</spirit:name>
|
|
<spirit:displayName>dsc_bypass_h2c_2</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ctl_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_len_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_load_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_src_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dsc_bypass_h2c_3</spirit:name>
|
|
<spirit:displayName>dsc_bypass_h2c_3</spirit:displayName>
|
|
<spirit:description>Descriptor Bypass Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="dsc_bypass_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ctl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ctl_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_dst_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_len</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_len_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_load</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_load_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dsc_byp_src_addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_dsc_byp_src_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dsc_bypass_h2c_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dma_status_ports</spirit:name>
|
|
<spirit:displayName>dma_status_ports</spirit:displayName>
|
|
<spirit:description>XDMA Status Ports Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_status_ports" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_status_ports_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>c2h_sts0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_sts_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>c2h_sts1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_sts_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>c2h_sts2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_sts_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>c2h_sts3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>c2h_sts_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>h2c_sts0</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_sts_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>h2c_sts1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_sts_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>h2c_sts2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_sts_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>h2c_sts3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>h2c_sts_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dma_status_ports" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cap</spirit:name>
|
|
<spirit:displayName>cap</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cap_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>GNT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cap_gnt</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>REL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cap_rel</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>REQ</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cap_req</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cap" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) == "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>startup</spirit:name>
|
|
<spirit:displayName>startup</spirit:displayName>
|
|
<spirit:description>STARTUP Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfgclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_cfgclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfgmclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_cfgmclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>di</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_di</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>do</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_do</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dts</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_dts</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>eos</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_eos</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fcsbo</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_fcsbo</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fcsbts</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_fcsbts</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gsr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_gsr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gts</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_gts</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>keyclearb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_keyclearb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pack</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_pack</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>preq</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_preq</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>userdoneo</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_usrdoneo</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>usrcclko</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_usrcclko</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>usrclkts</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_usrcclkts</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>usrdonets</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>startup_usrdonets</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.startup" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>atspri_s_axis_rq</spirit:name>
|
|
<spirit:displayName>atspri_s_axis_rq</spirit:displayName>
|
|
<spirit:description>The Requestor Request interface received requests TLP's from the Client Application</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_s_axis_rq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.atspri_s_axis_rq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>atspri_m_axis_cq</spirit:name>
|
|
<spirit:displayName>atspri_m_axis_cq</spirit:displayName>
|
|
<spirit:description>The Completer Request interface is used to transmit Completion TLP's to the Client Application</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>atspri_m_axis_cq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.atspri_m_axis_cq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cfg_status_ats</spirit:name>
|
|
<spirit:displayName>cfg_status_ats</spirit:displayName>
|
|
<spirit:description>Configuration Status Interface For ATS</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_ats" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_ats_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_ats_en</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_ats_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_ats_stu</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_ats_stu</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cfg_status_ats" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cfg_status_pri</spirit:name>
|
|
<spirit:displayName>cfg_status_pri</spirit:displayName>
|
|
<spirit:description>Configuration Status Interface For PRI</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_pri" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie3_7x" spirit:name="cfg_status_pri_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_clr_s</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_clr_s</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_ost_pr_alloc</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_ost_pr_alloc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_pr_en</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_pr_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_pr_rf</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_pr_rf</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_pr_rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_pr_rst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_pr_uprgi</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_pr_uprgi</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_set_rf</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_set_rf</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_set_s</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_set_s</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cfg_status_set_uprgi</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_status_set_uprgi</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cfg_status_pri" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>dma_debug_ports</spirit:name>
|
|
<spirit:displayName>XDMA Debug Ports</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_debug_ports" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="xdma_debug_ports_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tdata_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tkeep_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tkeep_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tlast_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tlast_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tready_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tready_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tuser_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tuser_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cc_tvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_cc_tvalid_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tdata_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tkeep_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tkeep_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tlast_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tlast_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tready_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tready_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tuser_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tuser_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>cq_tvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_cq_tvalid_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tdata_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tkeep_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tkeep_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tlast_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tlast_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tready_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tready_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tuser_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tuser_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rc_tvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axis_rc_tvalid_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tdata_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tdata_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tkeep_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tkeep_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tlast_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tlast_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tready_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tready_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tuser_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tuser_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rq_tvalid_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axis_rq_tvalid_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.dma_debug_ports" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_us_ext_shared_logic</spirit:name>
|
|
<spirit:displayName>pcie3_us_ext_shared_logic</spirit:displayName>
|
|
<spirit:description>PCIE3 Ultrascale External Shared Logic Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="ext_shared_logic" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="ext_shared_logic_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1pd</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1pd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1rate</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1refclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1refclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_qpll1reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_ext_shared_logic" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_us_int_shared_logic</spirit:name>
|
|
<spirit:displayName>pcie3_us_int_shared_logic</spirit:displayName>
|
|
<spirit:description>PCIE3 Ultrascale Internal Shared Logic Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="int_shared_logic" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="int_shared_logic_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qpll1lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qpll1outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qpll1outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_us_int_shared_logic" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_usp_ext_gtcom</spirit:name>
|
|
<spirit:displayName>pcie4_usp_ext_gtcommon</spirit:displayName>
|
|
<spirit:description>PCIE4 Ultrascale+ External GT COMMON Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="ext_gtcom_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll0lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll0lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll0outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll0outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll0outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll0outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll0pd</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll0pd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll0reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll0reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll1lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll1outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll1outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1pd</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll1pd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpll1reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpll1reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpllxrate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpllxrate</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpllxrcalenb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpllxrcalenb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>exts_qpllxrefclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ext_usp_qpllxrefclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_ext_gtcom" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_usp_int_gtcom</spirit:name>
|
|
<spirit:displayName>pcie4_usp_int_gtcommon</spirit:displayName>
|
|
<spirit:description>PCIE4 Ultrascale+ Internal GT COMMON Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_pcie4_uscaleplus" spirit:name="int_gtcom_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll0lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll0lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll0outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll0outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll0outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll0outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1lock_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll1lock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1outclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll1outclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ints_qpll1outrefclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_usp_qpll1outrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_usp_int_gtcom" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pipe_clock</spirit:name>
|
|
<spirit:displayName>pipe_clock</spirit:displayName>
|
|
<spirit:description>PCIExpress Enternal PIPE Clock interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pipe_clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pipe_clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_dclk_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gen3_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_gen3_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mmcm_lock_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_mmcm_lock_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mmcm_rst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_mmcm_rst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>oobclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_oobclk_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_pclk_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pclk_sel_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_pclk_sel_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxoutclk_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxoutclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxusrclk_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_rxusrclk_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>txoutclk_out</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_txoutclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>userclk1_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_userclk1_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>userclk2_in</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pipe_userclk2_in</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pipe_clock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_sharedlogic_int_clk</spirit:name>
|
|
<spirit:displayName>pcie3_sharedlogic_int_clk</spirit:displayName>
|
|
<spirit:description>PCIe3 Shared logic interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_sharedlogic_int_clk" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_sharedlogic_int_clk_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_dclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>oobclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_oobclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pclk_sel_slave</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_pclk_sel_slave</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pclk_slave</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_pclk_out_slave</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pipe_rxusrclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_pipe_rxusrclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplllock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qplllock_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplloutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qplloutclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplloutrefclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_qplloutrefclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rxoutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_rxoutclk_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>usrclk1</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_userclk1_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>usrclk2</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>int_userclk2_out</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_sharedlogic_int_clk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie3_qpll_drp</spirit:name>
|
|
<spirit:displayName>pcie3_qpll_drp</spirit:displayName>
|
|
<spirit:description>PCIe Gen3 external gt_common Interface</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_qpll_drp" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="pcie_qpll_drp_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>clk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_clk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>crscode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_crscode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_done</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fsm</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_fsm</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>gen3</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_gen3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ovrd</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_ovrd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplld</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_qplld</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplllock</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_qplllock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplloutclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_qplloutclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qplloutrefclk</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_qplloutrefclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>qpllreset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_qpllreset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_rst_n</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>start</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>qpll_drp_start</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie3_qpll_drp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_msix_ext_usp</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msix_ext_usp</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_fail</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msi_sent</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_msix_ext_usp" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie_cfg_msix_ext_us</spirit:name>
|
|
<spirit:displayName>pcie4_cfg_msix_ext_us</spirit:displayName>
|
|
<spirit:description>PCIE MSI-X Interrupt</spirit:description>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_xdma" spirit:name="pcie_cfg_external_msix_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>address</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_address</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>data</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fail</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_fail</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>int_vector</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_int</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>mask</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_mask</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sent</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cfg_interrupt_msix_sent</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie_cfg_msix_ext_us" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE") and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>CLK.s_aclk</spirit:name>
|
|
<spirit:displayName>CLK.s_aclk</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_aclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.FREQ_HZ">250000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.ASSOCIATED_RESET">s_aresetn</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.ASSOCIATED_PORT"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.S_ACLK.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK.s_aclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>RST.s_aresetn</spirit:name>
|
|
<spirit:displayName>RST.s_aresetn</spirit:displayName>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST.S_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.S_ARESETN.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.RST.s_aresetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXI</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARQOS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arqos</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_aruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWQOS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awqos</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s_axi_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PROTOCOL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ADDR_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>READ_WRITE_MODE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_LOCK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_PROT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_CACHE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_QOS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_REGION</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_WSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_BRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_RRESP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_BURST_LENGTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_READ_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_WRITE_THREADS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cxs_tx</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_ACK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_active_ack_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_REQ</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_active_req_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_cntl_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_cntl_chk_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdgnt_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdgnt_chk_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdrtn_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdrtn_chk_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_data_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_data_chk_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEACT_HINT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_deact_hint_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_valid_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_valid_chk_tx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_FLIT_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_TX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))">64</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_PKT_PER_FLIT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_TX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512 ) ? 4 : 2)">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATACHECK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.DATACHECK">NONE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_TX.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cxs_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>cxs_rx</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_ACK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_active_ack_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_REQ</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_active_req_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_cntl_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_cntl_chk_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdgnt_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdgnt_chk_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdrtn_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_crdrtn_chk_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_data_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_data_chk_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEACT_HINT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_deact_hint_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_valid_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>cxs0_valid_chk_rx</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_FLIT_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_RX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))">64</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_PKT_PER_FLIT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.CXS_RX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512 ) ? 4 : 2)">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATACHECK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.DATACHECK">NONE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CXS_RX.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.cxs_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cxs_tx</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_ACK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_active_ack_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_REQ</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_active_req_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_cntl_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_cntl_chk_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdgnt_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdgnt_chk_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdrtn_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdrtn_chk_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_data_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_data_chk_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEACT_HINT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_deact_hint_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_valid_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_valid_chk_tx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_FLIT_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))">64</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_PKT_PER_FLIT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512 ) ? 4 : 2)">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATACHECK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.DATACHECK">NONE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_TX.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cxs_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>pcie4_cxs_rx</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="cxs_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_ACK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_active_ack_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ACTIVE_REQ</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_active_req_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_cntl_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CNTL_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_cntl_chk_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdgnt_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDGNT_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdgnt_chk_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdrtn_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CRDRTN_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_crdrtn_chk_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_data_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DATA_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_data_chk_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>DEACT_HINT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_deact_hint_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_valid_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>VALID_CHK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>pcie4_cxs0_valid_chk_rx_sd</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_FLIT_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.DATA_FLIT_WIDTH" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))">64</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_PKT_PER_FLIT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.MAX_PKT_PER_FLIT" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512 ) ? 4 : 2)">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATACHECK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.DATACHECK">NONE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PCIE4_CXS_RX.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pcie4_cxs_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc0_ats_m_axis_cq</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_cq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_m_axis_cq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc0_ats_m_axis_rc</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_m_axis_rc_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_m_axis_rc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc0_ats_s_axis_cc</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_cc_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_s_axis_cc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc0_ats_s_axis_rq</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc0_ats_s_axis_rq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc0_ats_s_axis_rq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc1_ats_m_axis_cq</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_cq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_m_axis_cq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc1_ats_m_axis_rc</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_m_axis_rc_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_m_axis_rc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc1_ats_s_axis_cc</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_cc_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_s_axis_cc" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>sc1_ats_s_axis_rq</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TKEEP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tkeep</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>TVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>sc1_ats_s_axis_rq_tvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDATA_NUM_BYTES">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TDEST_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDEST_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TID_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TUSER_WIDTH">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TREADY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TREADY">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TSTRB</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TSTRB">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TKEEP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TKEEP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HAS_TLAST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TLAST">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>FREQ_HZ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.FREQ_HZ">100000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHASE</spirit:name>
|
|
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.PHASE">0.0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.CLK_DOMAIN"/>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LAYERED_METADATA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.LAYERED_METADATA">undef</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INSERT_VIP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.INSERT_VIP">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.sc1_ats_s_axis_rq" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>usr_flr</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_qdma" spirit:name="usr_flr" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_qdma" spirit:name="usr_flr_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>clear</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>usr_flr_clr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>done_fnc</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>usr_flr_done_fnc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>done_vld</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>usr_flr_done_vld</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>fnc</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>usr_flr_fnc</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>set</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>usr_flr_set</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.usr_flr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true" and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:addressSpaces>
|
|
<spirit:addressSpace>
|
|
<spirit:name>M_AXI</spirit:name>
|
|
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:pow(2,id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">16777216T</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
</spirit:addressSpace>
|
|
<spirit:addressSpace>
|
|
<spirit:name>M_AXI_LITE</spirit:name>
|
|
<spirit:range spirit:format="long">4G</spirit:range>
|
|
<spirit:width spirit:format="long">32</spirit:width>
|
|
</spirit:addressSpace>
|
|
<spirit:addressSpace>
|
|
<spirit:name>M_AXI_BYPASS</spirit:name>
|
|
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:pow(2,id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">16777216T</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
</spirit:addressSpace>
|
|
<spirit:addressSpace>
|
|
<spirit:name>M_AXI_B</spirit:name>
|
|
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:pow(2,id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">16777216T</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
</spirit:addressSpace>
|
|
</spirit:addressSpaces>
|
|
<spirit:memoryMaps>
|
|
<spirit:memoryMap>
|
|
<spirit:name>S_AXI_LITE</spirit:name>
|
|
<spirit:addressBlock>
|
|
<spirit:name>CTL0</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 1) ? spirit:pow(2,16) : spirit:pow(2,29))">65536</spirit:range>
|
|
<spirit:width spirit:format="long">32</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_LITE.CTL0.OFFSET_BASE_PARAM">baseaddr</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_LITE.CTL0.OFFSET_HIGH_PARAM">highaddr</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:addressBlock>
|
|
</spirit:memoryMap>
|
|
<spirit:memoryMap>
|
|
<spirit:name>S_AXI_B</spirit:name>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR0</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR0.OFFSET_BASE_PARAM">axibar_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR0.OFFSET_HIGH_PARAM">axibar_highaddr_0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR0" xilinx:dependency="spirit:decode((id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR1</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR1.OFFSET_BASE_PARAM">axibar_1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR1.OFFSET_HIGH_PARAM">axibar_highaddr_1</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR2</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR2.OFFSET_BASE_PARAM">axibar_2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR2.OFFSET_HIGH_PARAM">axibar_highaddr_2</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR3</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR3.OFFSET_BASE_PARAM">axibar_3</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR3.OFFSET_HIGH_PARAM">axibar_highaddr_3</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR4</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR4.OFFSET_BASE_PARAM">axibar_4</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR4.OFFSET_HIGH_PARAM">axibar_highaddr_4</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
<spirit:addressBlock>
|
|
<spirit:name>BAR5</spirit:name>
|
|
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long" spirit:resolve="generated" spirit:dependency="spirit:pow(2,20)">1048576</spirit:range>
|
|
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH'))">64</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:access>read-write</spirit:access>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR5.OFFSET_BASE_PARAM">axibar_5</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_B.BAR5.OFFSET_HIGH_PARAM">axibar_highaddr_5</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:addressBlockInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_B.BAR5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_AXIBAR_NUM'))>5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:addressBlockInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:addressBlock>
|
|
</spirit:memoryMap>
|
|
</spirit:memoryMaps>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_vhdlinstantiationtemplate</spirit:name>
|
|
<spirit:displayName>VHDL Instantiation Template</spirit:displayName>
|
|
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
|
|
<spirit:language>vhdl</spirit:language>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Wed Apr 30 16:22:12 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:2e780eae</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_elaborateports</spirit:name>
|
|
<spirit:displayName>Elaborate Ports</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:8e761f64</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_elaboratesubcores</spirit:name>
|
|
<spirit:displayName>Elaborate Sub-Cores</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:elaborate.subcores</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_elaboratesubcores_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Wed Apr 30 16:23:16 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:829d8866</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
|
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>xdma_0_core_top</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Thu May 01 10:31:09 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:021da178</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
|
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:021da178</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
|
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>xdma_0</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Thu May 01 10:31:09 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:021da178</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_implementation</spirit:name>
|
|
<spirit:displayName>Implementation</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Thu May 01 10:31:09 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:021da178</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_externalfiles</spirit:name>
|
|
<spirit:displayName>External Files</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>GENtimestamp</spirit:name>
|
|
<spirit:value>Thu May 01 10:33:56 UTC 2025</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>outputProductCRC</spirit:name>
|
|
<spirit:value>9:021da178</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
|
<spirit:name>sys_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sys_clk_ce_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_ce_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_SYS_CLK_BUFG')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sys_clk_gt</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_clk_gt" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sys_rst_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sys_rst_n" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.VERSAL')) != "TRUE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dma_bridge_resetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dma_bridge_resetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SOFT_RESET_EN')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>config_space_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.config_space_enable" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_SPACE_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ltssm_state</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ltssm_state" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "FALSE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>user_lnk_up</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_lnk_up" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pci_exp_txp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pci_exp_txp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "FALSE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pci_exp_txn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pci_exp_txn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "FALSE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pci_exp_rxp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pci_exp_rxp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "FALSE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pci_exp_rxn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pci_exp_rxn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "FALSE")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_subsys_vend_id</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID'))" spirit:bitStringLength="16">0x10EE</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_subsys_vend_id" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_vend_id</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF0_VENDOR_ID'))" spirit:bitStringLength="16">0x10EE</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_vend_id" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_dev_id_pf0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF0_DEVICE_ID'))" spirit:bitStringLength="16">0x7021</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_dev_id_pf0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_dev_id_pf1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF1_DEVICE_ID'))" spirit:bitStringLength="16">0x1041</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_dev_id_pf1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_dev_id_pf2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF2_DEVICE_ID'))" spirit:bitStringLength="16">0x1040</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_dev_id_pf2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_dev_id_pf3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF3_DEVICE_ID'))" spirit:bitStringLength="16">0x1039</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_dev_id_pf3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_rev_id_pf0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF0_REVISION_ID'))" spirit:bitStringLength="8">0x00</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_rev_id_pf0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 0 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_rev_id_pf1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF1_REVISION_ID'))" spirit:bitStringLength="8">0x00</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_rev_id_pf1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_rev_id_pf2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF2_REVISION_ID'))" spirit:bitStringLength="8">0x00</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_rev_id_pf2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_rev_id_pf3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF3_REVISION_ID'))" spirit:bitStringLength="8">0x00</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_rev_id_pf3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_subsys_id_pf0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF0_SUBSYSTEM_ID'))" spirit:bitStringLength="16">0x0007</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_subsys_id_pf0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 0 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_subsys_id_pf1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF1_SUBSYSTEM_ID'))" spirit:bitStringLength="16">0x0007</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_subsys_id_pf1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 1 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_subsys_id_pf2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF2_SUBSYSTEM_ID'))" spirit:bitStringLength="16">0x0007</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_subsys_id_pf2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 2 or spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_subsys_id_pf3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="bitString" spirit:resolve="dependent" spirit:dependency="spirit:decode(id('MODELPARAM_VALUE.PF3_SUBSYSTEM_ID'))" spirit:bitStringLength="16">0x0007</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_subsys_id_pf3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE_ID_IF')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.TL_PF_ENABLE_REG')) = 3)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>axi_aclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>axi_aresetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>axi_ctl_aclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.axi_ctl_aclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ACLK_LOOPBACK')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>axi_ctl_aresetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.axi_ctl_aresetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_irq_req</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.USRINT_EXPN')) = "TRUE") ? 23 : (spirit:decode(id('MODELPARAM_VALUE.XDMA_NUM_USR_IRQ')) - 1))">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_irq_req" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_irq_function_number</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.XDMA_NUM_USR_IRQ'))*2) - 1)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_irq_function_number" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true" and spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_irq_ack</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.USRINT_EXPN')) = "TRUE") ? 23 : (spirit:decode(id('MODELPARAM_VALUE.XDMA_NUM_USR_IRQ')) - 1))">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_irq_ack" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true")">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>msi_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.msi_enable" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>msix_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.msix_enable" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>msi_vector_width</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.msi_vector_width" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_UPSTREAM_FACING')) = "true") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_bid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_bid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_bresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_bvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_ruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_ruser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awlock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_awcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_awcache" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wstrb" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_wvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_bready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_araddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arlock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_arcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_arcache" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axi_rready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 1 and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_awaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_awuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">10</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_awuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_awprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_awvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_awready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_wdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_wstrb" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_wvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_wready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_bvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_bresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_bready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_araddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_aruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">10</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_aruser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_arprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_arvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_arready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_rdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_rresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_rvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axil_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axil_rready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_MASTER')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_addr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">18</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_addr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_write</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_write" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_write_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_write_data" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_byte_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_byte_enable" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read_data" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read_write_done</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read_write_done" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_type1_cfg_reg_access</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_type1_cfg_reg_access" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ) and spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULTQ_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_addr_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">9</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_addr_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_write_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_write_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_function_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_function_number_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_write_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_write_data_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_byte_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_byte_enable_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read_data_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_read_write_done_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_read_write_done_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_mgmt_type1_cfg_reg_access_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_mgmt_type1_cfg_reg_access_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_MGMT_IF')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE") )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_rdy</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_rdy" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_do</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_do" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_en" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_we</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_we" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_addr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">10</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_addr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drp_di</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drp_di" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PCIE3_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>common_commands_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">25</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.common_commands_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_0_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_0_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_1_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_1_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_2_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_2_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_3_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_3_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_4_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_4_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_5_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_5_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_6_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_6_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_7_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_7_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_8_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_8_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_9_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_9_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_10_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_10_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_11_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_11_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_12_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_12_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_13_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_13_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_14_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_14_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rx_15_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rx_15_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>common_commands_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">25</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.common_commands_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_0_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_0_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_1_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_1_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_2_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_2_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_3_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_3_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_4_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_4_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_5_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_5_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_6_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_6_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_7_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_7_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_8_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_8_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_9_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_9_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_10_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_10_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_11_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_11_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_12_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_12_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_13_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_13_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_14_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_14_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_tx_15_sigs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">83</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_tx_15_sigs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_SIM')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awaddr" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awlen" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_AWUSER_WIDTH')) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awsize" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awburst" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awprot" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awvalid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awready" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2)and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awlock" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_awcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_awcache" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wdata" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wstrb" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wlast" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wvalid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wready" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_wuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_wuser" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_bid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_bid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_bresp" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0)and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_bvalid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_bready" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0)and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_araddr" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arlen" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_aruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ARUSER_WIDTH')) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_aruser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arsize" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arburst" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arprot" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arvalid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arready" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arlock" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_arcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_arcache" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0)and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rdata" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_ruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_ruser" xilinx:dependency="((((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rresp" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rlast" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rvalid" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axib_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axib_rready" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.XDMA_AXIST_BYPASS')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 1 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")) or ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0) and spirit:decode(id('MODELPARAM_VALUE.EN_AXI_MASTER_IF')) = "TRUE"))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tdata_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tlast_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tlast_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tvalid_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tvalid_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tready_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tuser_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tuser_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tkeep_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tkeep_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tdata_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tlast_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tlast_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tvalid_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tvalid_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tready_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tuser_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tuser_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tkeep_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tkeep_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tdata_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tlast_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tlast_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tvalid_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tvalid_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tready_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tuser_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tuser_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tkeep_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tkeep_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tdata_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tlast_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tlast_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tvalid_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tvalid_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tready_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tuser_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tuser_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tkeep_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tkeep_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tdata_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tdata_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tlast_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tlast_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tvalid_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tvalid_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tready_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tready_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tuser_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tuser_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tkeep_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tkeep_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tdata_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tdata_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tlast_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tlast_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tvalid_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tvalid_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tready_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tready_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tuser_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tuser_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tkeep_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tkeep_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tdata_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tdata_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tlast_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tlast_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tvalid_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tvalid_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tready_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tready_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tuser_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tuser_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_c2h_tkeep_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_c2h_tkeep_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tdata_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tdata_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tlast_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tlast_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tvalid_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tvalid_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tready_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tready_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tuser_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tuser_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1 and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_h2c_tkeep_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_h2c_tkeep_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXI_INTF_MM')) = 0 and spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHELL_BRIDGE')) = 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_awaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_awprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_awvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_awready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_wdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_wstrb" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_wvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_wready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_bvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_bresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_bready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_araddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_arprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_arvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_arready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_rdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_rresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_rvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axil_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axil_rready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.XDMA_AXILITE_SLAVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ready_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_src_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_src_addr_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_dst_addr_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_len_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_len_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ctl_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ctl_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_load_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_load_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ready_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_src_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_src_addr_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_dst_addr_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_len_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_len_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ctl_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ctl_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_load_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_load_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ready_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ready_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_src_addr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_src_addr_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_dst_addr_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_len_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_len_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ctl_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ctl_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_load_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_load_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ready_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ready_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_src_addr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_src_addr_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_dst_addr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_dst_addr_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_len_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_len_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_ctl_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_ctl_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_dsc_byp_load_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_dsc_byp_load_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.WR_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ready_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_src_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_src_addr_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_dst_addr_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_len_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_len_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ctl_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ctl_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_load_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_load_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH0_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ready_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_src_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_src_addr_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_dst_addr_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_len_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_len_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ctl_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ctl_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_load_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_load_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH1_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ready_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ready_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_src_addr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_src_addr_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_dst_addr_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_len_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_len_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ctl_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ctl_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_load_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_load_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH2_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ready_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ready_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_src_addr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_src_addr_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_dst_addr_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_dst_addr_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_len_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">27</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_len_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_ctl_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_ctl_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_dsc_byp_load_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_dsc_byp_load_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.RD_CH3_ENABLED')) = "TRUE"">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_sts_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_sts_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_sts_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_sts_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_0')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_sts_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_sts_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_sts_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_sts_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_1')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_sts_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_sts_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_sts_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_sts_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_2')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>c2h_sts_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.c2h_sts_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_WCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>h2c_sts_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.h2c_sts_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_RCHNL_3')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.XDMA_STS_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_negotiated_width_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_negotiated_width_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_current_speed_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_current_speed_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ltssm_state_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ltssm_state_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_cor_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_cor_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_fatal_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_fatal_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_nonfatal_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_nonfatal_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_local_error_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_local_error_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_local_error_valid_o</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_local_error_valid_o" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txprbssel</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txprbssel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxprbssel</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxprbssel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txprbsforceerr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txprbsforceerr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxprbscntreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxprbscntreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_loopback</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_loopback" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxprbserr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxprbserr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txinhibit</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txinhibit" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rst_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rst_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_qrst_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_qrst_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rate_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rate_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_sync_fsm_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 6) - 1)">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_sync_fsm_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_sync_fsm_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 7) - 1)">6</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_sync_fsm_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_drp_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 7) - 1)">6</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_drp_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rst_idle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rst_idle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_qrst_idle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_qrst_idle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rate_idle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rate_idle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_eyescandataerror</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_eyescandataerror" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxstatus</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxstatus" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_dmonitorout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 15) - 1)">14</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_dmonitorout" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_cpll_lock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_cpll_lock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_qpll_lock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))/8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_qpll_lock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxpmaresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxpmaresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxbufstatus</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxbufstatus" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txphaligndone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txphaligndone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txphinitdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txphinitdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txdlysresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) ) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txdlysresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxphaligndone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) ) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxphaligndone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxdlysresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) ) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxdlysresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxsyncdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxsyncdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxdisperr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxdisperr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxnotintable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxnotintable" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxcommadet</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxcommadet" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_ch_drp_rdy</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_ch_drp_rdy" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_5</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_5" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_6</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_6" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_7</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_7" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_8</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_8" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_9</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_9" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_pcieuserratedone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_pcieuserratedone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_loopback</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_loopback" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txprbsforceerr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txprbsforceerr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txinhibit</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txinhibit" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txprbssel</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txprbssel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxprbssel</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxprbssel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxprbscntreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxprbscntreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txelecidle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txelecidle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxpmaresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxpmaresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txphaligndone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txphaligndone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txphinitdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txphinitdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txdlysresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txdlysresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxphaligndone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxphaligndone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxdlysresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxdlysresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxsyncdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxsyncdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_eyescandataerror</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_eyescandataerror" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxprbserr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxprbserr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_dmonfiforeset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_dmonfiforeset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_dmonitorclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_dmonitorclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_dmonitorout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")?((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 17) - 1):((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1))">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_dmonitorout" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxcommadet</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxcommadet" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_phystatus</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_phystatus" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxcdrlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxcdrlock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_pcierateidle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_pcierateidle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_pcieuserratestart</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_pcieuserratestart" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_gtpowergood</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_gtpowergood" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_cplllock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_cplllock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxoutclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxoutclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxrecclkout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxrecclkout" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_qpll1lock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")?(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH'))/8)+1) - 1):((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4))">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_qpll1lock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxstatus</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxstatus" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxbufstatus</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxbufstatus" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_bufgtdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_bufgtdiv" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_txeq_ctrl</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_txeq_ctrl" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_txeq_preset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_txeq_preset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_rst_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_rst_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_txeq_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_txeq_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_rxeq_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_rxeq_fsm" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_rst_idle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_rst_idle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_rrst_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_rrst_n" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_prst_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_prst_n" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" or ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1)- 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpwe</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1)- 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpwe" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) ? ((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 10)- 1) : ((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 9)- 1))">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpdi</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16)- 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpdi" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drprdy</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1)- 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drprdy" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_ch_gt_drpdo</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16)- 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_ch_gt_drpdo" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXT_CH_GT_DRP')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcap_design_switch</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcap_design_switch" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcap_eos_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.mcap_eos_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_cfgclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_cfgclk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_cfgmclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_cfgmclk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_di</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_di" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_eos</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_eos" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_preq</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_preq" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_do</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_do" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_dts</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_dts" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_fcsbo</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_fcsbo" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_fcsbts</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_fcsbts" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_gsr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_gsr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_gts</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_gts" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_keyclearb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_keyclearb" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_pack</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_pack" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_usrcclko</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_usrcclko" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_usrcclkts</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_usrcclkts" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_usrdoneo</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_usrdoneo" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>startup_usrdonets</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.startup_usrdonets" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") and (spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "PR") and (spirit:decode(id('MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE')) = "FALSE") and ((spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") || ((spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) = "TANDEM_PROM") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) = "TRUE"))))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cap_req</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_req" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) == "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cap_gnt</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_gnt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) == "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cap_rel</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cap_rel" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MCAP_ENABLEMENT')) != "NONE") && (spirit:decode(id('MODELPARAM_VALUE.TANDEM_RFSOC')) == "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 32) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 136 : 61) : 59)">59</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_s_axis_rq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_s_axis_rq_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 32) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 182 : 87) : 84)">84</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>atspri_m_axis_cq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.atspri_m_axis_cq_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_ats_stu</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_ats_stu" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_ats_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_ats_en" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_pr_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_pr_en" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_pr_rst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_pr_rst" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_pr_uprgi</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_pr_uprgi" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_set_uprgi</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_set_uprgi" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_pr_rf</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_pr_rf" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_set_rf</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_set_rf" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_set_s</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_set_s" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_clr_s</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_clr_s" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_status_ost_pr_alloc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_status_ost_pr_alloc" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_ATS_ENABLE')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.C_PRI_ENABLE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_read_received</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_read_received" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_write_received</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_write_received" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_register_number</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">9</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_register_number" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_function_number</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_function_number" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_write_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_write_data" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_write_byte_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_write_byte_enable" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_read_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_read_data" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ext_read_data_valid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ext_read_data_valid" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.CFG_EXT_IF')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.LEGACY_CFG_EXT_IF')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tdata_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tdata_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tlast_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tlast_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tuser_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 136 : 61) : 59)">59</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tuser_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tkeep_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tkeep_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tready_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tready_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rq_tvalid_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rq_tvalid_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tdata_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tdata_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tuser_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 160 : 74 )">74</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tuser_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tlast_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tlast_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tkeep_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tkeep_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tvalid_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tvalid_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rc_tready_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rc_tready_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tdata_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tdata_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tuser_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 182 : 87) : 84)">84</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tuser_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tlast_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tlast_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tkeep_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tkeep_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tvalid_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tvalid_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cq_tready_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cq_tready_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tdata_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tdata_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tuser_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 80 : 32)">32</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tuser_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tlast_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tlast_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tkeep_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tkeep_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tvalid_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tvalid_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cc_tready_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cc_tready_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.EN_DEBUG_PORTS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_pclk_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_pclk_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxusrclk_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxusrclk_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxoutclk_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxoutclk_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_dclk_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_dclk_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_userclk1_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_userclk1_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_userclk2_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_userclk2_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_oobclk_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_oobclk_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_mmcm_lock_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_mmcm_lock_in" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_txoutclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_txoutclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_rxoutclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_rxoutclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_mmcm_rst_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_mmcm_rst_n" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_pclk_sel_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_pclk_sel_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_gen3_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_gen3_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1refclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1refclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1rate</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8) * 3)+3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1rate" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1pd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1pd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1lock_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1outclk_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_qpll1outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_qpll1outrefclk_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qpll1lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qpll1lock_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qpll1outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qpll1outrefclk_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qpll1outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qpll1outclk_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_pclk_out_slave</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_pclk_out_slave" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_pipe_rxusrclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_pipe_rxusrclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_rxoutclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_rxoutclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_dclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_dclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_userclk1_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_userclk1_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_userclk2_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_userclk2_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_oobclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_oobclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qplllock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qplllock_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qplloutclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qplloutclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_qplloutrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_qplloutrefclk_out" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_pclk_sel_slave</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_pclk_sel_slave" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_crscode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_crscode" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_fsm</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">17</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_fsm" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_done</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_done" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_reset" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_qplllock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_qplllock" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_qplloutclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_qplloutclk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_qplloutrefclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_qplloutrefclk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_qplld</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_qplld" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_qpllreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_qpllreset" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_clk" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_rst_n</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_rst_n" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_ovrd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_ovrd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_gen3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_gen3" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll_drp_start</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll_drp_start" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "FALSE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) or (spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_qpll0lock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_qpll0lock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_gen34_eios_det</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_gen34_eios_det" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txoutclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txoutclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txoutclkfabric</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txoutclkfabric" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxoutclkfabric</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxoutclkfabric" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txoutclkpcs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txoutclkpcs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxoutclkpcs</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxoutclkpcs" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txpmareset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txpmareset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxpmareset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxpmareset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txpcsreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txpcsreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxpcsreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxpcsreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxbufreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxbufreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxcdrreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxcdrreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxdfelpmreset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxdfelpmreset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txprogdivresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txprogdivresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txpmaresetdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txpmaresetdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_txsyncdone</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_txsyncdone" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_rxprbslocked</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_rxprbslocked" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpllxrefclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpllxrefclk" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpllxrate</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4) + 1) * 3) -1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpllxrate" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpllxrcalenb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpllxrcalenb" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll0pd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll0pd" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll0reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll0reset" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll0lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll0lock_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll0outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll0outclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll0outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll0outrefclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll0lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll0lock_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll0outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll0outrefclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll0outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll0outclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll1pd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll1pd" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll1reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll1reset" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll1lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll1lock_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll1outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll1outclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_usp_qpll1outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_usp_qpll1outrefclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll1lock_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll1lock_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll1outrefclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll1outrefclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>int_usp_qpll1outclk_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.int_usp_qpll1outclk_out" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.GTCOM_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>free_run_clock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.free_run_clock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DRP_CLK_SEL')) = 1)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msi_vec0to31</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msi_vec0to31" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH'))>1)) and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msi_vec32to63</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msi_vec32to63" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH'))>1)) and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msix_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msix_0" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msix_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msix_1" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msix_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msix_2" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>interrupt_out_msix_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt_out_msix_3" xilinx:dependency="((spirit:decode((id('MODELPARAM_VALUE.MSIX_RX_DECODE_EN')) = "TRUE")))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and ((spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" )))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awregion</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awregion" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wstrb" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_ruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')/8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_ruser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.C_PARITY_PROP')) = 1))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_bready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_araddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arregion</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arregion" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_awready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_wready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_bid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_bid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_bresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_bvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_arready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ID_WIDTH')) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axib_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axib_rvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.EN_AXI_SLAVE_IF')) = "TRUE" and (spirit:decode(id('MODELPARAM_VALUE.DMA_EN')) = 0 or spirit:decode(id('MODELPARAM_VALUE.FUNC_MODE')) = 2 or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_function_status</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") ? 15 : 7 )">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_function_status" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_max_read_req</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_max_read_req" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_max_payload</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? 1 : 2 )">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_max_payload" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_flr_in_process</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_flr_in_process" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_flr_done</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_flr_done" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_vf_flr_in_process</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">251</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_vf_flr_in_process" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_vf_flr_func_num</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_vf_flr_func_num" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_vf_flr_done</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_vf_flr_done" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_enable" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrefclk01_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrefclk01_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrefclk00_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrefclk00_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpll0_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4) + 1) * 3) -1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpll0_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpll1_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4) + 1) * 3) -1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpll1_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0pd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0pd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0reset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0reset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1pd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1pd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1reset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1reset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0lock_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0lock_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0outclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0outclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0outrefclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0outrefclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1lock_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1lock_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1outclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1outclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1outrefclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1outrefclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0freqlock_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0freqlock_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1freqlock_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1freqlock_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpllpd_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpllpd_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpllreset_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpllreset_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) != 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_reset_rx_done_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_reset_rx_done_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_reset_tx_done_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_reset_tx_done_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_userclk_rx_active_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_userclk_rx_active_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_userclk_tx_active_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_userclk_tx_active_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>loopback_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.loopback_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbssel_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbssel_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxrate_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxrate_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl0_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl0_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl1_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl1_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl2_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl2_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdata_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 128) - 1)">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdata_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdeemph_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdeemph_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdiffctrl_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdiffctrl_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprbssel_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprbssel_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprecursor_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprecursor_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txrate_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txrate_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txmaincursor_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 7) - 1)">6</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txmaincursor_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txmargin_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txmargin_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclksel_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclksel_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpostcursor_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpostcursor_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cpllfreqlock_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpllfreqlock_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rcalenb_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1 )/4)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rcalenb_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cpllpd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpllpd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cpllreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpllreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonfiforeset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonfiforeset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonitorclk_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonitorclk_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>eyescanreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.eyescanreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrefclk0_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrefclk0_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrxreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrxreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gttxreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gttxreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpisopd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpisopd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieeqrxeqadaptdone_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieeqrxeqadaptdone_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierstidle_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierstidle_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pciersttxsyncstart_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pciersttxsyncstart_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserratedone_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserratedone_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>resetovrd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.resetovrd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rx8b10ben_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx8b10ben_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbufreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbufreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrfreqreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrfreqreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcommadeten_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcommadeten_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfeagchold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfeagchold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfecfokhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfecfokhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfekhhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfekhhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfelfhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfelfhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfelpmreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfelpmreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap10hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap10hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap11hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap11hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap12hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap12hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap13hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap13hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap14hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap14hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap15hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap15hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap2hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap2hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap3hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap3hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap4hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap4hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap5hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap5hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap6hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap6hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap7hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap7hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap8hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap8hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap9hold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap9hold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfeuthold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfeuthold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfevphold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfevphold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmgchold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmgchold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmhfhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmhfhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmlfhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmlfhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmoshold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmoshold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxmcommaalignen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxmcommaalignen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoshold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoshold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpcommaalignen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpcommaalignen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpcsreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpcsreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpmareset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpmareset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpolarity_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpolarity_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbscntreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbscntreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprogdivreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprogdivreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxslide_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxslide_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxtermination_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxtermination_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxuserrdy_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxuserrdy_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxusrclk2_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxusrclk2_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxusrclk_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxusrclk_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>tx8b10ben_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.tx8b10ben_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdetectrx_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdetectrx_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlybypass_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlybypass_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyhold_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyhold_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyovrden_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyovrden_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlysreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlysreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyupdown_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyupdown_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txelecidle_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txelecidle_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpcsreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpcsreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphalign_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphalign_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphalignen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphalignen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlypd_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlypd_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlyreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlyreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlytstclk_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlytstclk_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphinit_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphinit_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphovrden_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphovrden_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxratemode_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxratemode_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpmareset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpmareset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprbsforceerr_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprbsforceerr_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprogdivreset_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprogdivreset_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpdelecidlemode_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpdelecidlemode_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txswing_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txswing_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncallin_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncallin_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncin_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncin_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncmode_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncmode_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txuserrdy_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txuserrdy_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txusrclk2_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txusrclk2_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txusrclk_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txusrclk_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxclkcorcnt_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxclkcorcnt_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtcemask_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtcemask_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtrstmask_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtrstmask_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbufstatus_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbufstatus_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxstatus_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxstatus_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl2_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl2_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl3_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl3_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtdiv_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 9) - 1)">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtdiv_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonitorout_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonitorout_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl0_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl0_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl1_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl1_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdata_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 128) - 1)">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdata_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtreset_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtreset_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtce_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtce_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cplllock_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cplllock_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtpowergood_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtpowergood_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierategen3_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierategen3_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateidle_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateidle_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pciesynctxsyncdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pciesynctxsyncdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieusergen3rdy_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieusergen3rdy_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserphystatusrst_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserphystatusrst_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserratestart_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserratestart_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phystatus_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phystatus_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbyteisaligned_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbyteisaligned_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbyterealign_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbyterealign_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrlock_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrlock_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcommadet_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcommadet_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxphaligndone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxphaligndone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpmaresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpmaresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdlysresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdlysresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxelecidle_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxelecidle_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoutclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoutclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoutclkfabric_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoutclkfabric_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoutclkpcs_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoutclkpcs_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbserr_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbserr_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbslocked_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbslocked_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxratedone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxratedone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxrecclkout_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxrecclkout_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxsyncdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxsyncdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlysresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlysresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxvalid_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxvalid_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclk_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclk_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclkfabric_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclkfabric_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclkpcs_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclkpcs_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphaligndone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphaligndone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphinitdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphinitdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpmaresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpmaresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprgdivresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprgdivresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txresetdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txresetdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncdone_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncdone_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncout_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncout_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpaddr_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 10) - 1)">9</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpaddr_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpen_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpen_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpdi_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpdi_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpwe_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpwe_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drprst_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drprst_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_bufg_gt_ce</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_bufg_gt_ce" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_bufg_gt_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_bufg_gt_reset" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_rst_idle</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_rst_idle" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_txoutclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_txoutclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_bufgtcemask</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_bufgtcemask" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_gt_bufgtrstmask</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_gt_bufgtrstmask" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_bufgtdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_bufgtdiv" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_pclk2_gt</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_pclk2_gt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_int_clock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_int_clock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_pclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_pclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_phy_pclk2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_pclk2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_phy_coreclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_coreclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_phy_userclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_userclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_phy_clk_phy_mcapclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_phy_clk_phy_mcapclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpdo_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpdo_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drprdy_usp_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drprdy_usp_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpclk_usp_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpclk_usp_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdlysresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdlysresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxelecidle_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxelecidle_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoutclk_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoutclk_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxphaligndone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxphaligndone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpmaresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpmaresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbserr_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbserr_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbslocked_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbslocked_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprgdivresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprgdivresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxratedone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxratedone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxsyncdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxsyncdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxvalid_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxvalid_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlysresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlysresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclk_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclk_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphaligndone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphaligndone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphinitdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphinitdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpmaresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpmaresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprgdivresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprgdivresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txresetdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txresetdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncout_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncout_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cplllock_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cplllock_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>eyescandataerror_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.eyescandataerror_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtpowergood_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtpowergood_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierategen3_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierategen3_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateidle_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateidle_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pciesynctxsyncdone_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pciesynctxsyncdone_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieusergen3rdy_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieusergen3rdy_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserphystatusrst_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserphystatusrst_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserratestart_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserratestart_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phystatus_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phystatus_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbyteisaligned_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbyteisaligned_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbyterealign_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbyterealign_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrlock_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrlock_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcommadet_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcommadet_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gthtxn_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gthtxn_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gthtxp_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gthtxp_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drprdy_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drprdy_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpllpd_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpllpd_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierateqpllreset_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierateqpllreset_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxclkcorcnt_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxclkcorcnt_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtce_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtce_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtcemask_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtcemask_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtreset_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtreset_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtrstmask_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtrstmask_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbufstatus_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbufstatus_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxstatus_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxstatus_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl2_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl2_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl3_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl3_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>bufgtdiv_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 9) - 1)">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.bufgtdiv_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcsrsvdout_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 12) - 1)">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcsrsvdout_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpdo_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpdo_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl0_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl0_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxctrl1_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxctrl1_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonitorout_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 17) - 1)">16</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonitorout_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdata_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 128) - 1)">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdata_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_reset_rx_done_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_reset_rx_done_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_reset_tx_done_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_reset_tx_done_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_userclk_rx_active_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_userclk_rx_active_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_userclk_tx_active_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_userclk_tx_active_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtwiz_userclk_tx_reset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtwiz_userclk_tx_reset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cpllpd_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpllpd_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfeagchold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfeagchold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfecfokhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfecfokhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfelfhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfelfhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfekhhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfekhhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap2hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap2hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap3hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap3hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap4hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap4hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap5hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap5hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap6hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap6hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap7hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap7hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap8hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap8hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap9hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap9hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap10hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap10hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap11hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap11hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap12hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap12hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap13hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap13hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap14hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap14hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfetap15hold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfetap15hold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfeuthold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfeuthold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxdfevphold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxdfevphold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxoshold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxoshold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmgchold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmgchold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmhfhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmhfhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmlfhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmlfhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmoshold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmoshold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cpllreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cpllreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonfiforeset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonfiforeset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>dmonitorclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.dmonitorclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpwe_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpwe_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>eyescanreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.eyescanreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gthrxn_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gthrxn_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gthrxp_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gthrxp_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrefclk0_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrefclk0_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrxreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrxreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gttxreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gttxreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieeqrxeqadaptdone_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieeqrxeqadaptdone_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcierstidle_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcierstidle_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pciersttxsyncstart_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pciersttxsyncstart_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcieuserratedone_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcieuserratedone_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rx8b10ben_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rx8b10ben_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxbufreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxbufreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcdrhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcdrhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxcommadeten_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxcommadeten_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxlpmen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxlpmen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxmcommaalignen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxmcommaalignen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpcommaalignen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpcommaalignen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpolarity_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpolarity_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbscntreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbscntreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprogdivreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprogdivreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxratemode_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxratemode_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxslide_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxslide_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxuserrdy_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxuserrdy_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxusrclk2_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxusrclk2_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxusrclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxusrclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>tx8b10ben_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.tx8b10ben_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdeemph_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdeemph_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdetectrx_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdetectrx_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlybypass_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlybypass_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyhold_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyhold_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyovrden_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyovrden_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlysreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlysreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdlyupdown_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdlyupdown_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txelecidle_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txelecidle_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txinhibit_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txinhibit_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphalign_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphalign_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphalignen_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphalignen_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlypd_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlypd_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlyreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlyreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphdlytstclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphdlytstclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphinit_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphinit_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txphovrden_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txphovrden_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprbsforceerr_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprbsforceerr_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprogdivreset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprogdivreset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txswing_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txswing_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncallin_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncallin_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncin_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncin_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txsyncmode_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txsyncmode_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txuserrdy_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txuserrdy_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txusrclk2_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txusrclk2_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txusrclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txusrclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxpd_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxpd_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpd_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 2) - 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpd_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>loopback_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.loopback_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxrate_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxrate_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txrate_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txrate_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txmargin_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txmargin_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txoutclksel_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 3) - 1)">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txoutclksel_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rxprbssel_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rxprbssel_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdiffctrl_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdiffctrl_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprbssel_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 4) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprbssel_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txprecursor_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txprecursor_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txpostcursor_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txpostcursor_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txmaincursor_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 7) - 1)">6</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txmaincursor_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl2_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl2_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpaddr_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 9) - 1)">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpaddr_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>drpdi_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.drpdi_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcsrsvdin_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcsrsvdin_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl0_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl0_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txctrl1_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 16) - 1)">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txctrl1_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>txdata_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) * 128) - 1)">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.txdata_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0clk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0clk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll0refclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll0refclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1clk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1clk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1refclk_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1refclk_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 0 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gtrefclk01_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gtrefclk01_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1pd_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1pd_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1reset_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1reset_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1lock_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1lock_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1outclk_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1outclk_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpll1outrefclk_us_out</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8)+1) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpll1outrefclk_us_out" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpllrsvd2_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8) * 5)+5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpllrsvd2_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>qpllrsvd3_us_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((((spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) / 8) * 5)+5) - 1)">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.qpllrsvd3_us_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.GTWIZ_IN_CORE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SHARED_LOGIC')) = 1 and spirit:decode(id('MODELPARAM_VALUE.PLL_TYPE')) = 2)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_enable" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and (( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")) or spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE") and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_mask</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_mask" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and (( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_data" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and (( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_address</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_address" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and (( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_int</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_int" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and (( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE")) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_sent</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_sent" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_fail</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_fail" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_sent</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_sent" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_fail</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_fail" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.MSIX_IMPL_EXT')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "FALSE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "FALSE" )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_bar_size_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">6</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_bar_size_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_function_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_function_number_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar0_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar0_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar1_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar1_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar2_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar2_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar3_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar3_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar4_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar4_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rbar_write_enable_bar5_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rbar_write_enable_bar5_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.RBAR_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and ( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ltssm_state_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ltssm_state_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>user_lnk_up_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_lnk_up_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>phy_rdy_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.phy_rdy_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_function_status_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) or spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE')) = "TRUE") ? 15 : 7 )">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_function_status_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_max_read_req_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_max_read_req_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_max_payload_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? 1 : 2 )">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_max_payload_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_flr_done_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_flr_done_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_flr_in_process_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_flr_in_process_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.VERSAL_PART_TYPE')) != "H10")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tdata_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tdata_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tlast_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tlast_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tuser_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 136 : 61) : 59)">59</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tuser_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tkeep_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tkeep_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tready_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tready_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_rq_tvalid_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_rq_tvalid_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tdata_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tdata_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tuser_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 160 : 74 )">74</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tuser_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tlast_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tlast_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tkeep_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tkeep_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tvalid_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tvalid_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_rc_tready_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_rc_tready_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tdata_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tdata_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tuser_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 182 : 87) : 84)">84</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tuser_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tlast_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tlast_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tkeep_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tkeep_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tvalid_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tvalid_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axis_cq_tready_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.m_axis_cq_tready_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tdata_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tdata_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tuser_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 80 : 32)">32</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tuser_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tlast_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tlast_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tkeep_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/32)- 1)">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tkeep_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tvalid_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tvalid_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axis_cc_tready_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axis_cc_tready_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>user_clk_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>user_reset_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_reset_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_cq_np_req_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_cq_np_req_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_cq_np_req_count_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_cq_np_req_count_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_tfc_nph_av_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_tfc_nph_av_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_tfc_npd_av_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_tfc_npd_av_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_rq_seq_num_vld0_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_rq_seq_num_vld0_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_rq_seq_num0_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_rq_seq_num0_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_rq_seq_num_vld1_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_rq_seq_num_vld1_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie_rq_seq_num1_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">5</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie_rq_seq_num1_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_fc_nph_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_fc_nph_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_fc_sel_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_fc_sel_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_phy_link_down_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_phy_link_down_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_phy_link_status_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_phy_link_status_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_negotiated_width_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_negotiated_width_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_current_speed_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_current_speed_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_pl_status_change_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_pl_status_change_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_hot_reset_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_hot_reset_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ds_port_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ds_port_number_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ds_bus_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ds_bus_number_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ds_device_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ds_device_number_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_ds_function_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_ds_function_number_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_uncor_in_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_uncor_in_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_config_space_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_config_space_enable_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_cor_in_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_cor_in_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_link_training_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_link_training_enable_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_vf_flr_in_process_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) - 1 )">251</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_vf_flr_in_process_sd" xilinx:dependency="(( spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) > 0) and spirit:decode(id('MODELPARAM_VALUE.VERSAL_PART_TYPE')) != "H10")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_dsn_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_dsn_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_int_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_int_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_sent_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_sent_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_pending_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_pending_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_enable_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_mask_update_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_mask_update_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_data_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_int_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_int_sd" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) or (spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 1 )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_pending_status_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_data_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_pending_status_data_enable_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_pending_status_function_num_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_pending_status_function_num_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_attr_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_attr_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_tph_present_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_tph_present_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_tph_type_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_tph_type_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_tph_st_tag_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">8</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_tph_st_tag_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_function_number_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_function_number_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_sent_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_sent_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msi_fail_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msi_fail_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSI_ENABLED')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_int_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_int_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_data_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 0 ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_address_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_address_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 0 ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_vec_pending_sd" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 1 )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_vec_pending_status_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_vec_pending_status_sd" xilinx:dependency="(((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.MSIX_PCIE_INTERNAL')) = 1 )) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_enable_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_mask_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_mask_sd" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" ) and (spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_vf_enable_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) - 1)">251</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_vf_enable_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) > 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_interrupt_msix_vf_mask_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) - 1)">251</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_interrupt_msix_vf_mask_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.MSIX_ENABLED')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.SRIOV_ACTIVE_VFS')) > 0)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_cor_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_cor_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_nonfatal_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_nonfatal_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_err_fatal_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_err_fatal_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_local_error_out_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_local_error_out_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_received_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_received_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_received_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_received_data_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_received_type_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_received_type_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_transmit_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_transmit_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_transmit_type_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_transmit_type_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_transmit_data_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_transmit_data_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cfg_msg_transmit_done_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cfg_msg_transmit_done_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>rd_interrupt</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rd_interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>wr_interrupt</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.wr_interrupt" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ats_pri_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ats_pri_en" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>gt_drp_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gt_drp_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE" && spirit:decode(id('MODELPARAM_VALUE.ENABLE_MORE')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.core_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE" && (spirit:decode(id('MODELPARAM_VALUE.ENABLE_MORE')) = "TRUE"))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_active_req_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_active_req_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_active_ack_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_active_ack_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_deact_hint_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_deact_hint_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_valid_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_valid_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdgnt_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdgnt_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdrtn_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdrtn_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_cntl_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 35 : 13)">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_cntl_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_data_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 511 : 255)">255</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_data_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_valid_chk_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_valid_chk_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdgnt_chk_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdgnt_chk_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdrtn_chk_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdrtn_chk_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_cntl_chk_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_cntl_chk_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_data_chk_tx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 63 : 31)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_data_chk_tx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_active_req_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_active_req_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_active_ack_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_active_ack_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_deact_hint_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_deact_hint_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_valid_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_valid_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdgnt_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdgnt_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdrtn_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdrtn_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_cntl_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 35 : 13)">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_cntl_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_data_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 511 : 255)">255</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_data_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_valid_chk_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_valid_chk_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdgnt_chk_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdgnt_chk_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_crdrtn_chk_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_crdrtn_chk_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_cntl_chk_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_cntl_chk_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>cxs0_data_chk_rx</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 63 : 31)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.cxs0_data_chk_rx" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_active_req_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_active_req_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_active_ack_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_active_ack_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_deact_hint_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_deact_hint_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_valid_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_valid_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdgnt_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdgnt_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdrtn_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdrtn_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_cntl_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 35 : 13)">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_cntl_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_data_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 511 : 255)">255</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_data_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_valid_chk_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_valid_chk_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdgnt_chk_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdgnt_chk_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdrtn_chk_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdrtn_chk_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_cntl_chk_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_cntl_chk_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_data_chk_tx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 63 : 31)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_data_chk_tx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_active_req_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_active_req_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_active_ack_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_active_ack_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_deact_hint_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_deact_hint_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_valid_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_valid_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdgnt_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdgnt_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdrtn_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdrtn_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_cntl_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 35 : 13)">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_cntl_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_data_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 511 : 255)">255</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_data_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_valid_chk_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_valid_chk_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdgnt_chk_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdgnt_chk_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_crdrtn_chk_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_crdrtn_chk_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_cntl_chk_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_cntl_chk_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pcie4_cxs0_data_chk_rx_sd</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 63 : 31)">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pcie4_cxs0_data_chk_rx_sd" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ccix_optimized_tlp_tx_and_rx_enable_in</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ccix_optimized_tlp_tx_and_rx_enable_in" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) != "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_aclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_aclk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_aresetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_aresetn" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_araddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arcache" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arlock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arqos</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arqos" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_aruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_aruser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">13</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awaddr" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awburst" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awcache" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awlen" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awlock" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awprot" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awqos</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awqos" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awsize" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_bid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wstrb" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s_axi_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_DVSEC')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit::decode(id('MODELPARAM_VALUE.SPLIT_DMA')) != "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_rq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 136 : 61) : 59)">59</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_rq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_rc_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 160 : 74 )">74</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_rc_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tvalid">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tlast">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_s_axis_cc_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 80 : 32)">32</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_s_axis_cc_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tready">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc0_ats_m_axis_cq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 182 : 87) : 84)">84</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc0_ats_m_axis_cq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_rq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 136 : 61) : 59)">59</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_rq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_rc_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 160 : 74 )">74</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_rc_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_s_axis_cc_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" ) and spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 80 : 32)">32</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_s_axis_cc_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tvalid" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tready" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) - 1)">63</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tdata" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tkeep</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) / 8) - 1)">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tkeep" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tlast" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>sc1_ats_m_axis_cq_tuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((( spirit:decode(id('MODELPARAM_VALUE.ULTRASCALE_PLUS')) = "TRUE" or spirit:decode(id('MODELPARAM_VALUE.VERSAL')) = "TRUE" )) ? ((spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')) = 512) ? 182 : 87) : 84)">84</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.sc1_ats_m_axis_cq_tuser" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.CCIX_ENABLE')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PCIE_BLK_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.C_NUM_OF_SC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.ENABLE_ATS_SWITCH')) = "TRUE" )">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ctl_in_tx0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ctl_in_tx0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ctl_in_tx1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ctl_in_tx1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ctl_in_rx0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ctl_in_rx0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ctl_in_rx1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ctl_in_rx1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ltssm_rec_spd_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ltssm_rec_spd_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ltssm_pol_act</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ltssm_pol_act" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_ctl_vec4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">3</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_ctl_vec4" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_mux_ctl</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_mux_ctl" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_128_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_128_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_ext_16_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_ext_16_0" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_128_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_128_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_ext_16_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_ext_16_1" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_128_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_128_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_ext_16_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_ext_16_2" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_128_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">127</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_128_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_debug_out_ext_16_3</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_debug_out_ext_16_3" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_inject_tx_status</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_inject_tx_status" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>pipe_debug_inject_rx_status</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.pipe_debug_inject_rx_status" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.PIPE_DEBUG_EN')) = "TRUE" and spirit:decode(id('MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH')) <= 8)">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_flr_fnc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_flr_fnc" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_flr_set</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_flr_set" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_flr_clr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_flr_clr" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_flr_done_fnc</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_flr_done_fnc" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>usr_flr_done_vld</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.usr_flr_done_vld" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.FLR_ENABLE')) = "TRUE") and spirit:decode(id('MODELPARAM_VALUE.MULT_PF_DES')) = "TRUE")">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
|
<spirit:name>COMPONENT_NAME</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COMPONENT_NAME">xdma_0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PL_UPSTREAM_FACING</spirit:name>
|
|
<spirit:displayName>Pl Upstream Facing</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_UPSTREAM_FACING">true</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>TL_LEGACY_MODE_ENABLE</spirit:name>
|
|
<spirit:displayName>Tl Legacy Mode Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_LEGACY_MODE_ENABLE">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PCIE_BLK_LOCN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_BLK_LOCN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PL_LINK_CAP_MAX_LINK_WIDTH</spirit:name>
|
|
<spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_WIDTH">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PL_LINK_CAP_MAX_LINK_SPEED</spirit:name>
|
|
<spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PL_LINK_CAP_MAX_LINK_SPEED">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>REF_CLK_FREQ</spirit:name>
|
|
<spirit:displayName>Ref Clk Freq</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REF_CLK_FREQ">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DRP_CLK_SEL</spirit:name>
|
|
<spirit:displayName>DRP CLK SEL</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DRP_CLK_SEL">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FREE_RUN_FREQ</spirit:name>
|
|
<spirit:displayName>Ref Clk Freq</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FREE_RUN_FREQ">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>AXI_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ADDR_WIDTH">64</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>AXI_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>AXI data width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_DATA_WIDTH">64</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>CORE_CLK_FREQ</spirit:name>
|
|
<spirit:displayName>Core Clk Freq</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CORE_CLK_FREQ">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PLL_TYPE</spirit:name>
|
|
<spirit:displayName>PLL Type</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PLL_TYPE">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>USER_CLK_FREQ</spirit:name>
|
|
<spirit:displayName>User Clk Freq</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USER_CLK_FREQ">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SILICON_REV</spirit:name>
|
|
<spirit:displayName>Silicon Revision</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SILICON_REV">Pre-Production</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PIPE_SIM</spirit:name>
|
|
<spirit:displayName>Enable External PIPE Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_SIM">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VDM_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VDM_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EXT_CH_GT_DRP</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_CH_GT_DRP">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PCIE3_DRP</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE3_DRP">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>DEDICATE_PERST</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEDICATE_PERST">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>SYS_RESET_POLARITY</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYS_RESET_POLARITY">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MCAP_ENABLEMENT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MCAP_ENABLEMENT">NONE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EXT_STARTUP_PRIMITIVE</spirit:name>
|
|
<spirit:displayName>EXT STARTUP PRIMITIVE</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_STARTUP_PRIMITIVE">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>pf0 Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf0 Device Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_DEVICE_ID" spirit:bitStringLength="16">0x7021</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf0 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_SUBSYSTEM_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>Pf0 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf0 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_CLASS_CODE</spirit:name>
|
|
<spirit:displayName>Pf0 Class Code</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_CLASS_CODE" spirit:bitStringLength="24">0x058000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>pf1 Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Device Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_DEVICE_ID" spirit:bitStringLength="16">0x1041</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_SUBSYSTEM_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID" spirit:bitStringLength="16">0x10EE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_CLASS_CODE</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_CLASS_CODE" spirit:bitStringLength="24">0x070001</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF2_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf2 Device Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_DEVICE_ID" spirit:bitStringLength="16">0x1040</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF2_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf2 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF3_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Device Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_DEVICE_ID" spirit:bitStringLength="16">0x1039</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF3_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_REVISION_ID" spirit:bitStringLength="8">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:bitStringLength="16">0x0007</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>AXILITE_MASTER_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_MASTER_APERTURE_SIZE" spirit:bitStringLength="8">0x0D</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>AXILITE_MASTER_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXILITE_MASTER_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>XDMA_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_APERTURE_SIZE" spirit:bitStringLength="8">0x09</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>XDMA_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>AXIST_BYPASS_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIST_BYPASS_APERTURE_SIZE" spirit:bitStringLength="8">0x0D</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>AXIST_BYPASS_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIST_BYPASS_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_INTERRUPT_PIN</spirit:name>
|
|
<spirit:displayName>pf1 Interrupt Pin</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_INTERRUPT_PIN" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PF0_MSI_CAP_MULTIMSGCAP</spirit:name>
|
|
<spirit:displayName>pf0 Msi Cap Multimsgcap</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSI_CAP_MULTIMSGCAP">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_COMP_TIMEOUT</spirit:name>
|
|
<spirit:displayName>c_comp_timeout</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_COMP_TIMEOUT">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_TIMEOUT0_SEL</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT0_SEL" spirit:bitStringLength="4">0xE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_TIMEOUT1_SEL</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT1_SEL" spirit:bitStringLength="4">0xF</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_TIMEOUT_MULT</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TIMEOUT_MULT" spirit:bitStringLength="3">0x3</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_OLD_BRIDGE_TIMEOUT</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OLD_BRIDGE_TIMEOUT">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>SHARED_LOGIC</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_CLK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_CLK">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_BOTH</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_BOTH">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_GTC</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_GTC">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_GTC_7XG2</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_GTC_7XG2">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_CLK_7XG2</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_CLK_7XG2">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SHARED_LOGIC_BOTH_7XG2</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHARED_LOGIC_BOTH_7XG2">false</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_TRANSCEIVER_STATUS_PORTS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_TRANSCEIVER_STATUS_PORTS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>IS_BOARD_PROJECT</spirit:name>
|
|
<spirit:displayName>Is Board Flow Enabled</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IS_BOARD_PROJECT">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_GT_SELECTION</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_GT_SELECTION">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SELECT_QUAD</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SELECT_QUAD">GTH_Quad_128</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ULTRASCALE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ULTRASCALE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ULTRASCALE_PLUS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ULTRASCALE_PLUS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VERSAL</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VERSAL">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>V7_GEN3</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.V7_GEN3">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MSI_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSI_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DEV_PORT_TYPE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEV_PORT_TYPE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_AXI_INTF_MM</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXI_INTF_MM">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_PCIE_64BIT_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_PCIE_64BIT_EN">xdma_pcie_64bit_en</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_AXILITE_MASTER</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXILITE_MASTER">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_AXIST_BYPASS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXIST_BYPASS">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_RNUM_CHNL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_RNUM_CHNL">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_WNUM_CHNL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_WNUM_CHNL">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_AXILITE_SLAVE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_AXILITE_SLAVE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_NUM_USR_IRQ</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NUM_USR_IRQ">16</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_RNUM_RIDS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_RNUM_RIDS">32</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_WNUM_RIDS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_WNUM_RIDS">16</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>EGW_IS_PARENT_IP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EGW_IS_PARENT_IP">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ID_WIDTH">4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_AXIBAR_NUM</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_NUM" spirit:minimum="0" spirit:maximum="6" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>C_FAMILY</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>XDMA_NUM_PCIE_TAG</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NUM_PCIE_TAG">32</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_AXI_MASTER_IF</spirit:name>
|
|
<spirit:displayName>Enable AXI Master IF</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_AXI_MASTER_IF">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_0</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_0">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_1</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_1">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_2</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_2">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_3</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_3">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_4</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_4">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_5</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_5">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_6</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_6">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_WCHNL_7</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_WCHNL_7">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_0</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_0">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_1</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_1">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_2</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_2">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_3</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_3">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_4</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_4">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_5</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_5">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_6</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_6">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_RCHNL_7</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_RCHNL_7">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_DSC_BYPASS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_DSC_BYPASS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_METERING_ON</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_METERING_ON">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RX_DETECT</spirit:name>
|
|
<spirit:displayName>Receiver Detect</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RX_DETECT">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>C_ATS_ENABLE</spirit:name>
|
|
<spirit:displayName>ATS Extended Capability Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_ATS_CAP_NEXTPTR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PR_CAP_NEXTPTR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PR_CAP_NEXTPTR" spirit:bitStringLength="12">0x000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>C_PRI_ENABLE</spirit:name>
|
|
<spirit:displayName>Page Request Extended Capability Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRI_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DSC_BYPASS_RD</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DSC_BYPASS_RD">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DSC_BYPASS_WR</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DSC_BYPASS_WR">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_STS_PORTS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_STS_PORTS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MSIX_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_ENABLED">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>WR_CH0_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH0_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>WR_CH1_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH1_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>WR_CH2_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH2_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>WR_CH3_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WR_CH3_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RD_CH0_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH0_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RD_CH1_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH1_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RD_CH2_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH2_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RD_CH3_ENABLED</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RD_CH3_ENABLED">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>CFG_MGMT_IF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_MGMT_IF">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>RQ_SEQ_NUM_IGNORE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RQ_SEQ_NUM_IGNORE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>CFG_EXT_IF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_EXT_IF">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>LEGACY_CFG_EXT_IF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LEGACY_CFG_EXT_IF">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_PARITY_CHECK</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_CHECK">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_PARITY_GEN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_GEN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_PARITY_PROP</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PARITY_PROP">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_ECC_ENABLE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ECC_ENABLE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_DEBUG_PORTS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_DEBUG_PORTS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VU9P_BOARD</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VU9P_BOARD">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_JTAG_DBG</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_JTAG_DBG">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_LTSSM_DBG</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_LTSSM_DBG">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_IBERT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_IBERT">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>MM_SLAVE_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MM_SLAVE_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DMA_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_EN">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_4</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_5</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_4</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR_HIGHADDR_5</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR_HIGHADDR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_4</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_AXIBAR2PCIEBAR_5</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AXIBAR2PCIEBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_AXI_SLAVE_IF</spirit:name>
|
|
<spirit:displayName>Enable AXI Slave IF</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_AXI_SLAVE_IF">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_INCLUDE_BAROFFSET_REG</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLUDE_BAROFFSET_REG">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_BASEADDR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_BASEADDR" spirit:bitStringLength="32">0x00001000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_HIGHADDR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HIGHADDR" spirit:bitStringLength="32">0x00001FFF</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_ID_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_NUM_READ</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_NUM_READ">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_NUM_READ</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_READ">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_NUM_READQ</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_READQ">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_NUM_WRITE</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_NUM_WRITE">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_NUM_WRITE</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_WRITE">4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_NUM_WRITE_SCALE</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_NUM_WRITE_SCALE">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MSIX_IMPL_EXT</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_IMPL_EXT">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>AXI_ACLK_LOOPBACK</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_ACLK_LOOPBACK">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR0_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR0_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR1_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR1_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR2_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR2_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR3_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR3_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR4_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR4_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR5_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x05</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_BAR5_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PF0_EXPANSION_ROM_ENABLE</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PCIEBAR_NUM</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIEBAR_NUM" spirit:minimum="0" spirit:maximum="6" spirit:rangeType="long">6</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_4</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_5</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_PCIEBAR2AXIBAR_6</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_6" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>BARLITE1</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE1">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>BARLITE2</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE2">7</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VCU118_BOARD</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VCU118_BOARD">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_ERROR_INJECTION</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_ERROR_INJECTION">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SPLIT_DMA</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SPLIT_DMA">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>USE_STANDARD_INTERFACES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USE_STANDARD_INTERFACES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>DMA_2RP</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_2RP">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>SRIOV_ACTIVE_VFS</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SRIOV_ACTIVE_VFS">252</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PIPE_LINE_STAGE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_LINE_STAGE">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>AXIS_PIPE_LINE_STAGE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXIS_PIPE_LINE_STAGE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MULT_PF_DES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MULT_PF_DES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PF_SWAP</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF_SWAP">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF0_MSIX_TAR_ID</spirit:name>
|
|
<spirit:displayName>PF0 MSIX target ID</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF0_MSIX_TAR_ID" spirit:bitStringLength="6">0x08</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_MSIX_TAR_ID</spirit:name>
|
|
<spirit:displayName>PF1 MSIX target ID</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_MSIX_TAR_ID" spirit:bitStringLength="6">0x09</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RUNBIT_FIX</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RUNBIT_FIX">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>USRINT_EXPN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USRINT_EXPN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>xlnx_ref_board</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.xlnx_ref_board">None</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>GTWIZ_IN_CORE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTWIZ_IN_CORE">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>GTCOM_IN_CORE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GTCOM_IN_CORE">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>INS_LOSS_PROFILE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INS_LOSS_PROFILE">Add-in_Card</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FUNC_MODE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FUNC_MODE">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PF1_ENABLED</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_ENABLED">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DMA_RESET_SOURCE_SEL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_RESET_SOURCE_SEL">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR0_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR0_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR0_CONTROL" spirit:bitStringLength="3">0x4</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR1_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR1_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR1_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR2_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR2_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR2_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR3_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR3_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR3_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR4_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR4_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR4_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR5_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_APERTURE_SIZE" spirit:bitStringLength="8">0x0A</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_BAR5_CONTROL</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Control</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_BAR5_CONTROL" spirit:bitStringLength="3">0x0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_EXPANSION_ROM_APERTURE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf1 Expansion Rom Aperture Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_APERTURE_SIZE" spirit:bitStringLength="9">0x000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PF1_EXPANSION_ROM_ENABLE</spirit:name>
|
|
<spirit:displayName>Pf1 Expansion Rom Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_EXPANSION_ROM_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_0" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_1" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_2" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_3" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_4</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_4" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_5</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_5" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>PF1_PCIEBAR2AXIBAR_6</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PF1_PCIEBAR2AXIBAR_6" spirit:bitStringLength="64">0x0000000000000000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_MSIX_INT_TABLE_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSIX_INT_TABLE_EN">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VU9P_TUL_EX</spirit:name>
|
|
<spirit:displayName>VU9P TUL board</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VU9P_TUL_EX">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PCIE_BLK_TYPE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_BLK_TYPE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>CCIX_ENABLE</spirit:name>
|
|
<spirit:displayName>Ccix Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCIX_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>CCIX_DVSEC</spirit:name>
|
|
<spirit:displayName>Ccix Dvsec Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CCIX_DVSEC">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EXT_SYS_CLK_BUFG</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_SYS_CLK_BUFG">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_NUM_OF_SC</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OF_SC">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>USR_IRQ_EXDES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.USR_IRQ_EXDES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>AXI_VIP_IN_EXDES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_VIP_IN_EXDES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PIPE_DEBUG_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIPE_DEBUG_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_NON_INCREMENTAL_EXDES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_NON_INCREMENTAL_EXDES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>XDMA_ST_INFINITE_DESC_EXDES</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.XDMA_ST_INFINITE_DESC_EXDES">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EXT_XVC_VSEC_ENABLE</spirit:name>
|
|
<spirit:displayName>Tl Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_XVC_VSEC_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ACS_EXT_CAP_ENABLE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ACS_EXT_CAP_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>EN_PCIE_DEBUG_PORTS</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EN_PCIE_DEBUG_PORTS">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>MULTQ_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MULTQ_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DMA_MM</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_MM">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DMA_ST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DMA_ST">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_PCIE_PFS_SUPPORTED</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PCIE_PFS_SUPPORTED">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_SRIOV_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SRIOV_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_EXT_PF0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF0" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_EXT_PF1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_EXT_PF2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_EXT_PF3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_EXT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_INT_PF0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF0" spirit:bitStringLength="6">0x01</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_INT_PF1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_INT_PF2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>BARLITE_INT_PF3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BARLITE_INT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_VFS_PF0</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF0">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_VFS_PF1</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF1">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_VFS_PF2</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF2">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_VFS_PF3</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_VFS_PF3">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FIRSTVF_OFFSET_PF0</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF0">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FIRSTVF_OFFSET_PF1</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF1">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FIRSTVF_OFFSET_PF2</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF2">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>FIRSTVF_OFFSET_PF3</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIRSTVF_OFFSET_PF3">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_EXT_PF0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF0" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_EXT_PF1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF1" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_EXT_PF2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF2" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_EXT_PF3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_EXT_PF3" spirit:bitStringLength="6">0x00</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_INT_PF0</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF0" spirit:bitStringLength="6">0x01</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_INT_PF1</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF1" spirit:bitStringLength="6">0x01</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_INT_PF2</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF2" spirit:bitStringLength="6">0x01</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>VF_BARLITE_INT_PF3</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VF_BARLITE_INT_PF3" spirit:bitStringLength="6">0x01</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_C2H_NUM_CHNL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_C2H_NUM_CHNL">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_H2C_NUM_CHNL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_H2C_NUM_CHNL">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>H2C_XDMA_CHNL</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.H2C_XDMA_CHNL" spirit:bitStringLength="8">0x0F</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C2H_XDMA_CHNL</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C2H_XDMA_CHNL" spirit:bitStringLength="8">0x0F</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>AXISTEN_IF_ENABLE_MSG_ROUTE</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXISTEN_IF_ENABLE_MSG_ROUTE" spirit:bitStringLength="18">0x00000</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_MORE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_MORE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>DISABLE_BRAM_PIPELINE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_BRAM_PIPELINE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>DISABLE_EQ_SYNCHRONIZER</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DISABLE_EQ_SYNCHRONIZER">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>C_ENABLE_RESOURCE_REDUCTION</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_RESOURCE_REDUCTION">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>GEN4_EIEOS_0S7</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.GEN4_EIEOS_0S7">TRUE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S_AXI_SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_SUPPORTS_NARROW_BURST">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ENABLE_ATS_SWITCH</spirit:name>
|
|
<spirit:displayName>ATS Switch Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_ATS_SWITCH">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_ATS_SWITCH_UNIQUE_BDF</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ATS_SWITCH_UNIQUE_BDF">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>BRIDGE_BURST</spirit:name>
|
|
<spirit:displayName>Bridge Burst Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BRIDGE_BURST">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>CFG_SPACE_ENABLE</spirit:name>
|
|
<spirit:displayName>Config Space Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CFG_SPACE_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_LAST_CORE_CAP_ADDR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LAST_CORE_CAP_ADDR" spirit:bitStringLength="12">0x100</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="std_logic_vector">
|
|
<spirit:name>C_VSEC_CAP_ADDR</spirit:name>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VSEC_CAP_ADDR" spirit:bitStringLength="12">0x128</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SOFT_RESET_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SOFT_RESET_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>INTERRUPT_OUT_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.INTERRUPT_OUT_WIDTH">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_MSI_RX_PIN_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSI_RX_PIN_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_MSIX_RX_PIN_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MSIX_RX_PIN_EN">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_INTX_RX_PIN_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTX_RX_PIN_EN">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>MSIX_RX_DECODE_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_RX_DECODE_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>PCIE_ID_IF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCIE_ID_IF">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>TL_PF_ENABLE_REG</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TL_PF_ENABLE_REG">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>AXSIZE_BYTE_ACCESS_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXSIZE_BYTE_ACCESS_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>SPLIT_DMA_SINGLE_PF</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SPLIT_DMA_SINGLE_PF">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>RBAR_ENABLE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RBAR_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_SMMU_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SMMU_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_AWUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_AWUSER_WIDTH">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_M_AXI_ARUSER_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ARUSER_WIDTH">8</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_SLAVE_READ_64OS_EN</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SLAVE_READ_64OS_EN">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>FLR_ENABLE</spirit:name>
|
|
<spirit:displayName>FLR Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FLR_ENABLE">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>SHELL_BRIDGE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHELL_BRIDGE">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>MSIX_PCIE_INTERNAL</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MSIX_PCIE_INTERNAL">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>VERSAL_PART_TYPE</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VERSAL_PART_TYPE">S80</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>TANDEM_RFSOC</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TANDEM_RFSOC">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="string">
|
|
<spirit:name>ERRC_DEC_EN</spirit:name>
|
|
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ERRC_DEC_EN">FALSE</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_007d0a61</spirit:name>
|
|
<spirit:enumeration>250</spirit:enumeration>
|
|
<spirit:enumeration>500</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_04670499</spirit:name>
|
|
<spirit:enumeration>No_ASPM</spirit:enumeration>
|
|
<spirit:enumeration>L0s_Supported</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_08bf412c</spirit:name>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
<spirit:enumeration>256</spirit:enumeration>
|
|
<spirit:enumeration>512</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_0be33969</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
<spirit:enumeration>7</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>9</spirit:enumeration>
|
|
<spirit:enumeration>10</spirit:enumeration>
|
|
<spirit:enumeration>11</spirit:enumeration>
|
|
<spirit:enumeration>12</spirit:enumeration>
|
|
<spirit:enumeration>13</spirit:enumeration>
|
|
<spirit:enumeration>14</spirit:enumeration>
|
|
<spirit:enumeration>15</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_0d378f84</spirit:name>
|
|
<spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
|
|
<spirit:enumeration>Mass_storage_controller</spirit:enumeration>
|
|
<spirit:enumeration>Network_controller</spirit:enumeration>
|
|
<spirit:enumeration>Display_controller</spirit:enumeration>
|
|
<spirit:enumeration>Multimedia_device</spirit:enumeration>
|
|
<spirit:enumeration>Memory_controller</spirit:enumeration>
|
|
<spirit:enumeration>Base_system_peripherals</spirit:enumeration>
|
|
<spirit:enumeration>Input_devices</spirit:enumeration>
|
|
<spirit:enumeration>Docking_stations</spirit:enumeration>
|
|
<spirit:enumeration>Processors</spirit:enumeration>
|
|
<spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Wireless_controller</spirit:enumeration>
|
|
<spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Processing_accelerators</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_0f93492c</spirit:name>
|
|
<spirit:enumeration>Chip-to-Chip</spirit:enumeration>
|
|
<spirit:enumeration>Add-in_Card</spirit:enumeration>
|
|
<spirit:enumeration>Backplane</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_110bd32e</spirit:name>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_1cafa9fb</spirit:name>
|
|
<spirit:enumeration>DMA</spirit:enumeration>
|
|
<spirit:enumeration>AXI_Bridge</spirit:enumeration>
|
|
<spirit:enumeration>DMA_and_Bridge</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_24b724fb</spirit:name>
|
|
<spirit:enumeration>Basic</spirit:enumeration>
|
|
<spirit:enumeration>Advanced</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_2d4b70a0</spirit:name>
|
|
<spirit:enumeration>Bottom</spirit:enumeration>
|
|
<spirit:enumeration>Top</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_2dba17cd</spirit:name>
|
|
<spirit:enumeration>None</spirit:enumeration>
|
|
<spirit:enumeration>Check_Parity</spirit:enumeration>
|
|
<spirit:enumeration>Propagate_Parity</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_34d65ff4</spirit:name>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_35d06715</spirit:name>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_38306dd1</spirit:name>
|
|
<spirit:enumeration>SOFT</spirit:enumeration>
|
|
<spirit:enumeration>HARD</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_3ca2cbc7</spirit:name>
|
|
<spirit:enumeration>BAR_0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_3cee6ea1</spirit:name>
|
|
<spirit:enumeration>16450_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>16550_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>16650_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>16750_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>16850_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>16950_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>Bi_directional_parallel_port</spirit:enumeration>
|
|
<spirit:enumeration>ECP_1.X_compliant_parallel_port</spirit:enumeration>
|
|
<spirit:enumeration>GPIB(IEEE_488.1/2)_controller</spirit:enumeration>
|
|
<spirit:enumeration>Generic_XT_compatible_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>Generic_modem</spirit:enumeration>
|
|
<spirit:enumeration>Hayes_compatible_modem_with_16450_compatible_interface</spirit:enumeration>
|
|
<spirit:enumeration>Hayes_compatible_modem_with_16550_compatible_interface</spirit:enumeration>
|
|
<spirit:enumeration>Hayes_compatible_modem_with_16650_compatible_interface</spirit:enumeration>
|
|
<spirit:enumeration>Hayes_compatible_modem_with_16750_compatible_interface</spirit:enumeration>
|
|
<spirit:enumeration>IEEE_1284_controller</spirit:enumeration>
|
|
<spirit:enumeration>IEEE_1284_target_device</spirit:enumeration>
|
|
<spirit:enumeration>Multiport_serial_controller</spirit:enumeration>
|
|
<spirit:enumeration>Other_communications_device</spirit:enumeration>
|
|
<spirit:enumeration>Parallel_port</spirit:enumeration>
|
|
<spirit:enumeration>Smart_Card</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_4665eb01</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
<spirit:enumeration>7</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_47140c0d</spirit:name>
|
|
<spirit:enumeration>0000</spirit:enumeration>
|
|
<spirit:enumeration>0001</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_4e419c85</spirit:name>
|
|
<spirit:enumeration>Default</spirit:enumeration>
|
|
<spirit:enumeration>Falling_Edge</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_52d29139</spirit:name>
|
|
<spirit:enumeration>Bytes</spirit:enumeration>
|
|
<spirit:enumeration>Kilobytes</spirit:enumeration>
|
|
<spirit:enumeration>Megabytes</spirit:enumeration>
|
|
<spirit:enumeration>Gigabytes</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_55451da8</spirit:name>
|
|
<spirit:enumeration>X1</spirit:enumeration>
|
|
<spirit:enumeration>X2</spirit:enumeration>
|
|
<spirit:enumeration>X4</spirit:enumeration>
|
|
<spirit:enumeration>X8</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_57749bc8</spirit:name>
|
|
<spirit:enumeration>DMA</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_589df8e9</spirit:name>
|
|
<spirit:enumeration>RAM</spirit:enumeration>
|
|
<spirit:enumeration>Other_memory_controller</spirit:enumeration>
|
|
<spirit:enumeration>Flash</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_5e150e6c</spirit:name>
|
|
<spirit:enumeration>50us</spirit:enumeration>
|
|
<spirit:enumeration>50ms</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_5e2921cd</spirit:name>
|
|
<spirit:enumeration>Kilobytes</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_5e45706a</spirit:name>
|
|
<spirit:enumeration>1_vector</spirit:enumeration>
|
|
<spirit:enumeration>2_vectors</spirit:enumeration>
|
|
<spirit:enumeration>4_vectors</spirit:enumeration>
|
|
<spirit:enumeration>8_vectors</spirit:enumeration>
|
|
<spirit:enumeration>16_vectors</spirit:enumeration>
|
|
<spirit:enumeration>32_vectors</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_65982d75</spirit:name>
|
|
<spirit:enumeration>2.5_GT/s</spirit:enumeration>
|
|
<spirit:enumeration>5.0_GT/s</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_6727dfa6</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_6a0870a7</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
<spirit:enumeration>7</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>9</spirit:enumeration>
|
|
<spirit:enumeration>10</spirit:enumeration>
|
|
<spirit:enumeration>11</spirit:enumeration>
|
|
<spirit:enumeration>12</spirit:enumeration>
|
|
<spirit:enumeration>13</spirit:enumeration>
|
|
<spirit:enumeration>14</spirit:enumeration>
|
|
<spirit:enumeration>15</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>17</spirit:enumeration>
|
|
<spirit:enumeration>18</spirit:enumeration>
|
|
<spirit:enumeration>19</spirit:enumeration>
|
|
<spirit:enumeration>20</spirit:enumeration>
|
|
<spirit:enumeration>21</spirit:enumeration>
|
|
<spirit:enumeration>22</spirit:enumeration>
|
|
<spirit:enumeration>23</spirit:enumeration>
|
|
<spirit:enumeration>24</spirit:enumeration>
|
|
<spirit:enumeration>25</spirit:enumeration>
|
|
<spirit:enumeration>26</spirit:enumeration>
|
|
<spirit:enumeration>27</spirit:enumeration>
|
|
<spirit:enumeration>28</spirit:enumeration>
|
|
<spirit:enumeration>29</spirit:enumeration>
|
|
<spirit:enumeration>30</spirit:enumeration>
|
|
<spirit:enumeration>31</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_6eff49bd</spirit:name>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_7a7dde49</spirit:name>
|
|
<spirit:enumeration>true</spirit:enumeration>
|
|
<spirit:enumeration>false</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8112d406</spirit:name>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_847d868a</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8a9e69a3</spirit:name>
|
|
<spirit:enumeration>AXI_Lite_Master</spirit:enumeration>
|
|
<spirit:enumeration>DMA</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8aad6ae4</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8af5a703</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8b5e4915</spirit:name>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_8f346c48</spirit:name>
|
|
<spirit:enumeration>User_Reset</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_914704bd</spirit:name>
|
|
<spirit:enumeration>100_MHz</spirit:enumeration>
|
|
<spirit:enumeration>125_MHz</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_91b49d0b</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
<spirit:enumeration>7</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>9</spirit:enumeration>
|
|
<spirit:enumeration>10</spirit:enumeration>
|
|
<spirit:enumeration>11</spirit:enumeration>
|
|
<spirit:enumeration>12</spirit:enumeration>
|
|
<spirit:enumeration>13</spirit:enumeration>
|
|
<spirit:enumeration>14</spirit:enumeration>
|
|
<spirit:enumeration>15</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_94684ae0</spirit:name>
|
|
<spirit:enumeration>CPLL</spirit:enumeration>
|
|
<spirit:enumeration>QPLL1</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_949abb3f</spirit:name>
|
|
<spirit:enumeration>X0Y0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_96d6a000</spirit:name>
|
|
<spirit:enumeration>Wireless_controller</spirit:enumeration>
|
|
<spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Data_acquisition_and_signal_processing_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Docking_stations</spirit:enumeration>
|
|
<spirit:enumeration>Processing_accelerators</spirit:enumeration>
|
|
<spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
|
|
<spirit:enumeration>Memory_controller</spirit:enumeration>
|
|
<spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Encryption/Decryption_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Display_controller</spirit:enumeration>
|
|
<spirit:enumeration>Multimedia_device</spirit:enumeration>
|
|
<spirit:enumeration>Input_devices</spirit:enumeration>
|
|
<spirit:enumeration>Mass_storage_controller</spirit:enumeration>
|
|
<spirit:enumeration>Processors</spirit:enumeration>
|
|
<spirit:enumeration>Device_does_not_fit_in_any_defined_classes</spirit:enumeration>
|
|
<spirit:enumeration>Bridge_device</spirit:enumeration>
|
|
<spirit:enumeration>Network_controller</spirit:enumeration>
|
|
<spirit:enumeration>Base_system_peripherals</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_9aec9108</spirit:name>
|
|
<spirit:enumeration>Internal</spirit:enumeration>
|
|
<spirit:enumeration>External</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_9e15bd51</spirit:name>
|
|
<spirit:enumeration>CONSTANT</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_9f5580fd</spirit:name>
|
|
<spirit:enumeration>Pre-Production</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_a2753f1e</spirit:name>
|
|
<spirit:enumeration>None</spirit:enumeration>
|
|
<spirit:enumeration>VCU117</spirit:enumeration>
|
|
<spirit:enumeration>VCU119</spirit:enumeration>
|
|
<spirit:enumeration>ZCU117</spirit:enumeration>
|
|
<spirit:enumeration>KCU116</spirit:enumeration>
|
|
<spirit:enumeration>VCU1262</spirit:enumeration>
|
|
<spirit:enumeration>VCU1299</spirit:enumeration>
|
|
<spirit:enumeration>VCU1525</spirit:enumeration>
|
|
<spirit:enumeration>KC705</spirit:enumeration>
|
|
<spirit:enumeration>KC705_REVC</spirit:enumeration>
|
|
<spirit:enumeration>KCU1500</spirit:enumeration>
|
|
<spirit:enumeration>XIL-ACCEL-RD-VU9P</spirit:enumeration>
|
|
<spirit:enumeration>XIL-ACCEL-RD-KU115</spirit:enumeration>
|
|
<spirit:enumeration>VCU1550</spirit:enumeration>
|
|
<spirit:enumeration>XBB1551</spirit:enumeration>
|
|
<spirit:enumeration>AU200</spirit:enumeration>
|
|
<spirit:enumeration>AU250</spirit:enumeration>
|
|
<spirit:enumeration>AU280</spirit:enumeration>
|
|
<spirit:enumeration>AC701</spirit:enumeration>
|
|
<spirit:enumeration>VCK190_ES</spirit:enumeration>
|
|
<spirit:enumeration>VCK190</spirit:enumeration>
|
|
<spirit:enumeration>VMK180</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_a71f3969</spirit:name>
|
|
<spirit:enumeration>AXI_Memory_Mapped</spirit:enumeration>
|
|
<spirit:enumeration>AXI_Stream</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ab8591cd</spirit:name>
|
|
<spirit:enumeration>PCI_Express_Endpoint_device</spirit:enumeration>
|
|
<spirit:enumeration>PCI_Express_Endpoint_device</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
|
<spirit:enumeration>Custom</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ae9f88f6</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_afc413d3</spirit:name>
|
|
<spirit:enumeration>None</spirit:enumeration>
|
|
<spirit:enumeration>Tandem_PROM_(Refer_PG023)</spirit:enumeration>
|
|
<spirit:enumeration>Tandem_PCIe_(Refer_PG023)</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_b0ffef10</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>7</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_bdd7203f</spirit:name>
|
|
<spirit:enumeration>True</spirit:enumeration>
|
|
<spirit:enumeration>False</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_bea500ca</spirit:name>
|
|
<spirit:enumeration>None</spirit:enumeration>
|
|
<spirit:enumeration>MSI-X_External</spirit:enumeration>
|
|
<spirit:enumeration>MSI-X_Internal</spirit:enumeration>
|
|
<spirit:enumeration>MSI-X_AXI4-Stream</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_c15e8c67</spirit:name>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
<spirit:enumeration>64</spirit:enumeration>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
<spirit:enumeration>256</spirit:enumeration>
|
|
<spirit:enumeration>512</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_c3d223d9</spirit:name>
|
|
<spirit:enumeration>Memory</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_c63ab5b1</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>1</spirit:enumeration>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>3</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>5</spirit:enumeration>
|
|
<spirit:enumeration>6</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_c7cd959a</spirit:name>
|
|
<spirit:enumeration>GTH_Quad_128</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ca108395</spirit:name>
|
|
<spirit:enumeration>2</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_cd8829a5</spirit:name>
|
|
<spirit:enumeration>RTL</spirit:enumeration>
|
|
<spirit:enumeration>IPI</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ce4d0c9f</spirit:name>
|
|
<spirit:enumeration>62.5</spirit:enumeration>
|
|
<spirit:enumeration>125</spirit:enumeration>
|
|
<spirit:enumeration>250</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_d1e1a340</spirit:name>
|
|
<spirit:enumeration>Kilobytes</spirit:enumeration>
|
|
<spirit:enumeration>Megabytes</spirit:enumeration>
|
|
<spirit:enumeration>Gigabytes</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_d53faa96</spirit:name>
|
|
<spirit:enumeration>100_MHz</spirit:enumeration>
|
|
<spirit:enumeration>125_MHz</spirit:enumeration>
|
|
<spirit:enumeration>250_MHz</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_d82124da</spirit:name>
|
|
<spirit:enumeration>X99Y99</spirit:enumeration>
|
|
<spirit:enumeration>X0Y3</spirit:enumeration>
|
|
<spirit:enumeration>X0Y6</spirit:enumeration>
|
|
<spirit:enumeration>X1Y0</spirit:enumeration>
|
|
<spirit:enumeration>X1Y2</spirit:enumeration>
|
|
<spirit:enumeration>X1Y3</spirit:enumeration>
|
|
<spirit:enumeration>X1Y4</spirit:enumeration>
|
|
<spirit:enumeration>X1Y5</spirit:enumeration>
|
|
<spirit:enumeration>X1Y6</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_d85ad257</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_df7cde9e</spirit:name>
|
|
<spirit:enumeration>RAM</spirit:enumeration>
|
|
<spirit:enumeration>Flash</spirit:enumeration>
|
|
<spirit:enumeration>Other_memory_controller</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_dff1a45d</spirit:name>
|
|
<spirit:enumeration>Wireless_controller</spirit:enumeration>
|
|
<spirit:enumeration>Satellite_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Data_acquisition_and_signal_processing_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Processing_accelerators</spirit:enumeration>
|
|
<spirit:enumeration>Intelligent_I/O_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Docking_stations</spirit:enumeration>
|
|
<spirit:enumeration>Device_was_built_before_Class_Code_definitions_were_finalized</spirit:enumeration>
|
|
<spirit:enumeration>Memory_controller</spirit:enumeration>
|
|
<spirit:enumeration>Simple_communication_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Serial_bus_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Encryption/Decryption_controllers</spirit:enumeration>
|
|
<spirit:enumeration>Display_controller</spirit:enumeration>
|
|
<spirit:enumeration>Multimedia_device</spirit:enumeration>
|
|
<spirit:enumeration>Input_devices</spirit:enumeration>
|
|
<spirit:enumeration>Mass_storage_controller</spirit:enumeration>
|
|
<spirit:enumeration>Processors</spirit:enumeration>
|
|
<spirit:enumeration>Device_does_not_fit_in_any_defined_classes</spirit:enumeration>
|
|
<spirit:enumeration>Bridge_device</spirit:enumeration>
|
|
<spirit:enumeration>Network_controller</spirit:enumeration>
|
|
<spirit:enumeration>Base_system_peripherals</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_e7c484ae</spirit:name>
|
|
<spirit:enumeration>TRUE</spirit:enumeration>
|
|
<spirit:enumeration>FALSE</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_e7f13338</spirit:name>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
<spirit:enumeration>64</spirit:enumeration>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
<spirit:enumeration>256</spirit:enumeration>
|
|
<spirit:enumeration>512</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_e8b249aa</spirit:name>
|
|
<spirit:enumeration>64_bit</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_e9cf6440</spirit:name>
|
|
<spirit:enumeration>Disabled</spirit:enumeration>
|
|
<spirit:enumeration>32bit_Enabled</spirit:enumeration>
|
|
<spirit:enumeration>64bit_Enabled</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ec64e624</spirit:name>
|
|
<spirit:enumeration>N/A</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_ef28ef63</spirit:name>
|
|
<spirit:enumeration>YES</spirit:enumeration>
|
|
<spirit:enumeration>NO</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_f1174048</spirit:name>
|
|
<spirit:enumeration>NONE</spirit:enumeration>
|
|
<spirit:enumeration>INTA</spirit:enumeration>
|
|
<spirit:enumeration>INTB</spirit:enumeration>
|
|
<spirit:enumeration>INTC</spirit:enumeration>
|
|
<spirit:enumeration>INTD</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_f94ec5c4</spirit:name>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
<spirit:enumeration>64</spirit:enumeration>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
<spirit:enumeration>256</spirit:enumeration>
|
|
<spirit:enumeration>512</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_fc3456a9</spirit:name>
|
|
<spirit:enumeration>Disabled</spirit:enumeration>
|
|
<spirit:enumeration>Enabled</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_fde36331</spirit:name>
|
|
<spirit:enumeration>Kilobytes</spirit:enumeration>
|
|
<spirit:enumeration>Megabytes</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_list_fe1fb7c4</spirit:name>
|
|
<spirit:enumeration>0</spirit:enumeration>
|
|
<spirit:enumeration>4</spirit:enumeration>
|
|
<spirit:enumeration>8</spirit:enumeration>
|
|
<spirit:enumeration>12</spirit:enumeration>
|
|
<spirit:enumeration>16</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_3c87fcdb</spirit:name>
|
|
<spirit:enumeration spirit:text="Include GT Wizard in core">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="Include GT Wizard in example design">0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_53749dec</spirit:name>
|
|
<spirit:enumeration spirit:text="Include Shared Logic in core">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="Include Shared Logic in example design">0</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choice_pairs_6f00a734</spirit:name>
|
|
<spirit:enumeration spirit:text="Include GT COMMON in example design">0</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="Include GT COMMON inside GT Wizard">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="No sharing when inside GT Wizard and PCIe">2</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0.vho</spirit:name>
|
|
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0.veo</spirit:name>
|
|
<spirit:userFileType>verilogTemplate</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_elaboratesubcores_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>ip_0/xdma_0_pcie2_ip.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_0/xdma_0_pcie2_ip.xml</spirit:name>
|
|
<spirit:userFileType>xml</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_1/xdma_v4_1_20_blk_mem_64_reg_be.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_1/xdma_v4_1_20_blk_mem_64_reg_be.xml</spirit:name>
|
|
<spirit:userFileType>xml</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_2/xdma_v4_1_20_blk_mem_64_noreg_be.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_2/xdma_v4_1_20_blk_mem_64_noreg_be.xml</spirit:name>
|
|
<spirit:userFileType>xml</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_3/pcie2_fifo_generator_dma_cpl.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_3/pcie2_fifo_generator_dma_cpl.xml</spirit:name>
|
|
<spirit:userFileType>xml</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_4/pcie2_fifo_generator_tgt_brdg.xci</spirit:name>
|
|
<spirit:userFileType>xci</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>ip_4/pcie2_fifo_generator_tgt_brdg.xml</spirit:name>
|
|
<spirit:userFileType>xml</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/pciedmacoredefines.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/xdma_axi4mm_axi_bridge.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_soft_defines.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_defines.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/pcie_dma_attr_defines.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/axidma_fifo.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_defines.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/axi_infrastructure_header.vh</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_axis_cc_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_axis_cq_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_axis_rc_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_axis_rq_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_c2h_crdt_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_dsc_in_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_dsc_out_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_fabric_input_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_fabric_output_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_gic_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_h2c_crdt_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_2Bx2048_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_64Bx128_32Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_64Bx512_32Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_dsc_cpld_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_mi_dsc_cpli_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_misc_input_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/verilog/dma_pcie_misc_output_if.svh</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/xdma_v4_1_vl_rfs.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:logicalName>xdma_v4_1_20</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_dma_cpl.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_dma_req.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_rx_destraddler.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_rx_demux.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_tgt_cpl.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_tgt_req.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_tx_mux.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_axi_stream_intf.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_cfg_sideband.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_pcie2_to_pcie3_wrapper.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>source/xdma_0_pcie3_7vx_ip.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>synth/xdma_0_ooc.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_dma_bram_wrap.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_dma_bram_wrap_1024.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_dma_bram_wrap_2048.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_v4_1/hdl/verilog/xdma_0_core_top.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:exportedName>xdma_0_core_top</spirit:exportedName>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>synth/xdma_0.sv</spirit:name>
|
|
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0_board.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0.dcp</spirit:name>
|
|
<spirit:userFileType>dcp</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0_stub.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0_stub.vhdl</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0_sim_netlist.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xdma_0_sim_netlist.vhdl</spirit:name>
|
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>The Xilinx PCI Express DMA</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xdma_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>functional_mode</spirit:name>
|
|
<spirit:displayName>Functional Mode</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.functional_mode" spirit:choiceRef="choice_list_1cafa9fb" spirit:order="2">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.functional_mode">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>mode_selection</spirit:name>
|
|
<spirit:displayName>Mode</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mode_selection" spirit:choiceRef="choice_list_24b724fb" spirit:order="1.5">Basic</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.mode_selection">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>device_port_type</spirit:name>
|
|
<spirit:displayName>Device Port Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.device_port_type" spirit:choiceRef="choice_list_ab8591cd" spirit:order="3">PCI_Express_Endpoint_device</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.device_port_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pcie_blk_locn</spirit:name>
|
|
<spirit:displayName>Pcie Blk Locn</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_blk_locn" spirit:choiceRef="choice_list_949abb3f" spirit:order="4">X0Y0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pcie_blk_locn">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pl_link_cap_max_link_width</spirit:name>
|
|
<spirit:displayName>Pl Link Cap Max Link Width</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pl_link_cap_max_link_width" spirit:choiceRef="choice_list_55451da8" spirit:order="5">X1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pl_link_cap_max_link_width">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pl_link_cap_max_link_speed</spirit:name>
|
|
<spirit:displayName>Pl Link Cap Max Link Speed</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pl_link_cap_max_link_speed" spirit:choiceRef="choice_list_65982d75" spirit:order="6">5.0_GT/s</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pl_link_cap_max_link_speed">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ref_clk_freq</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ref_clk_freq" spirit:choiceRef="choice_list_d53faa96" spirit:order="7" spirit:configGroups="1 UnGrouped">100_MHz</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.ref_clk_freq">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>drp_clk_sel</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.drp_clk_sel" spirit:choiceRef="choice_list_9aec9108" spirit:order="7.1" spirit:configGroups="1 UnGrouped">Internal</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.drp_clk_sel">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>free_run_freq</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.free_run_freq" spirit:choiceRef="choice_list_914704bd" spirit:order="7.2" spirit:configGroups="1 UnGrouped">100_MHz</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.free_run_freq">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_addr_width</spirit:name>
|
|
<spirit:displayName>AXI Address width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_addr_width" spirit:order="8" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_addr_width">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_data_width</spirit:name>
|
|
<spirit:displayName>AXI Data width</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_data_width" spirit:choiceRef="choice_list_e8b249aa" spirit:order="9">64_bit</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_data_width">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axisten_freq</spirit:name>
|
|
<spirit:displayName>AXIsten if freq</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_freq" spirit:choiceRef="choice_list_ce4d0c9f" spirit:order="10">62.5</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axisten_freq">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_axi_slave_if</spirit:name>
|
|
<spirit:displayName>Enable AXI Slave Interface</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_slave_if" spirit:order="11">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_slave_if">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_axi_master_if</spirit:name>
|
|
<spirit:displayName>Enable AXI Master Interface</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_master_if" spirit:order="12">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_master_if">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pipe_sim</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pipe_sim" spirit:order="13">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pipe_sim">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_ext_ch_gt_drp</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_ext_ch_gt_drp" spirit:order="14">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_ext_ch_gt_drp">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_pcie_drp</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_pcie_drp" spirit:order="15">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_pcie_drp">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dedicate_perst</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.dedicate_perst" spirit:order="16">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.dedicate_perst">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>sys_reset_polarity</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sys_reset_polarity" spirit:choiceRef="choice_list_6eff49bd" spirit:order="17">ACTIVE_LOW</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.sys_reset_polarity">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>mcap_enablement</spirit:name>
|
|
<spirit:displayName>MCAP Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_enablement" spirit:choiceRef="choice_list_afc413d3" spirit:order="18">None</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.mcap_enablement">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>mcap_fpga_bitstream_version</spirit:name>
|
|
<spirit:displayName>MCAP Bitstream Version Register Value</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.mcap_fpga_bitstream_version" spirit:order="18.1">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.mcap_fpga_bitstream_version">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ext_startup_primitive</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_startup_primitive" spirit:order="19">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.ext_startup_primitive">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_code</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_code" spirit:order="1.1">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vendor_id</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.vendor_id" spirit:order="20">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.vendor_id">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_device_id</spirit:name>
|
|
<spirit:displayName>PF0 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_device_id" spirit:order="21">7021</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_device_id">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_revision_id</spirit:name>
|
|
<spirit:displayName>PF0 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_revision_id" spirit:order="22">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_revision_id">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_subsystem_vendor_id</spirit:name>
|
|
<spirit:displayName>PF0 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_subsystem_vendor_id" spirit:order="23">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_subsystem_vendor_id">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_subsystem_id</spirit:name>
|
|
<spirit:displayName>PF0 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_subsystem_id" spirit:order="24">0007</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_subsystem_id">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_Use_Class_Code_Lookup_Assistant</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="25">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_Use_Class_Code_Lookup_Assistant">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_base_class_menu</spirit:name>
|
|
<spirit:displayName>Pf0 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_base_class_menu" spirit:choiceRef="choice_list_0d378f84" spirit:order="26">Simple_communication_controllers</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_base_class_menu">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_base</spirit:name>
|
|
<spirit:displayName>Pf0 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_base" spirit:order="27">05</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_base">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sub_class_interface_menu</spirit:name>
|
|
<spirit:displayName>Pf0 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sub_class_interface_menu" spirit:choiceRef="choice_list_3cee6ea1" spirit:order="28">Generic_XT_compatible_serial_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_sub_class_interface_menu">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_sub</spirit:name>
|
|
<spirit:displayName>pf0 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_sub" spirit:order="29">80</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_sub">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_interface</spirit:name>
|
|
<spirit:displayName>pf0 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_interface" spirit:order="30">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_interface">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code</spirit:name>
|
|
<spirit:displayName>pf0 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code" spirit:order="31">058000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axilite_master_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="32">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_en">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axilite_master_size</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="34">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axilite_master_scale</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axilite_master_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="35">Megabytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axilite_master_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="36">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_en">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_size</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="37">64</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_scale</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="38">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axist_bypass_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="39">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_en">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axist_bypass_size</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="40">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_size">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axist_bypass_scale</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axist_bypass_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="41">Megabytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axist_bypass_scale">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_axil_master</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_axil_master" spirit:order="42" spirit:configGroups="1 UnGrouped">0x00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_axil_master">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_xdma</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_xdma" spirit:order="43" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_xdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_axist_bypass</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_axist_bypass" spirit:order="44" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_axist_bypass">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_interrupt_pin</spirit:name>
|
|
<spirit:displayName>pf0 Interrupt Pin</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_interrupt_pin" spirit:choiceRef="choice_list_f1174048" spirit:order="45">NONE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_interrupt_pin">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msi_enabled</spirit:name>
|
|
<spirit:displayName>pf0 Msi Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="46">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_msi_enabled">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msi_cap_multimsgcap</spirit:name>
|
|
<spirit:displayName>pf0 Msi Cap Multimsgcap</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msi_cap_multimsgcap" spirit:choiceRef="choice_list_5e45706a" spirit:order="47">1_vector</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_msi_cap_multimsgcap">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>comp_timeout</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.comp_timeout" spirit:choiceRef="choice_list_5e150e6c" spirit:order="48" spirit:configGroups="1 UnGrouped">50ms</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.comp_timeout">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>timeout0_sel</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout0_sel" spirit:choiceRef="choice_list_91b49d0b" spirit:order="48.1" spirit:configGroups="1 UnGrouped">14</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout0_sel">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>timeout1_sel</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout1_sel" spirit:choiceRef="choice_list_91b49d0b" spirit:order="48.2" spirit:configGroups="1 UnGrouped">15</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout1_sel">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>timeout_mult</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.timeout_mult" spirit:choiceRef="choice_list_4665eb01" spirit:order="48.3" spirit:configGroups="1 UnGrouped">3</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.timeout_mult">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>old_bridge_timeout</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.old_bridge_timeout" spirit:order="48.4">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic" spirit:choiceRef="choice_pairs_53749dec" spirit:order="49">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.Shared_Logic">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Clk</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Clk" spirit:order="50">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Both</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Both" spirit:order="51">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Gtc</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Gtc" spirit:order="52">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Gtc_7xG2</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Gtc_7xG2" spirit:order="52.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Clk_7xG2</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Clk_7xG2" spirit:order="50.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Shared_Logic_Both_7xG2</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Shared_Logic_Both_7xG2" spirit:order="51.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_transceiver_status_ports</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_transceiver_status_ports" spirit:order="53">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_transceiver_status_ports">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_rnum_chnl</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_rnum_chnl" spirit:choiceRef="choice_list_8aad6ae4" spirit:order="54">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_rnum_chnl">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_wnum_chnl</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_wnum_chnl" spirit:choiceRef="choice_list_8aad6ae4" spirit:order="55">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_wnum_chnl">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_axilite_slave</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_axilite_slave" spirit:order="56">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_axilite_slave">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_num_usr_irq</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_num_usr_irq" spirit:choiceRef="choice_list_0be33969" spirit:order="57">16</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_num_usr_irq">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_rnum_rids</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_rnum_rids" spirit:order="58" spirit:minimum="2" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_wnum_rids</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_wnum_rids" spirit:order="59" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">16</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SYS_RST_N_BOARD_INTERFACE</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="60">Custom</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PCIE_BOARD_INTERFACE</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCIE_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="61">Custom</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>EGW_IS_PARENT_IP</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.EGW_IS_PARENT_IP" spirit:choiceRef="choice_list_6727dfa6" spirit:order="3.41">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_gt_selection</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_gt_selection" spirit:order="3.5">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>select_quad</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.select_quad" spirit:choiceRef="choice_list_c7cd959a" spirit:order="4.5">GTH_Quad_128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.select_quad">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_PPM_OFFSET</spirit:name>
|
|
<spirit:description>Specify the PPM offset between received data and transmitted data</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_PPM_OFFSET" spirit:order="62" spirit:minimum="0" spirit:maximum="1250" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>RX_SSC_PPM</spirit:name>
|
|
<spirit:description>Specify the spread spectrum clocking modulation in PPM</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.RX_SSC_PPM" spirit:order="63" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>INS_LOSS_NYQ</spirit:name>
|
|
<spirit:description>Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB</spirit:description>
|
|
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.INS_LOSS_NYQ" spirit:order="64">15</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PHY_LP_TXPRESET</spirit:name>
|
|
<spirit:displayName>Phy Lp Txpreset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHY_LP_TXPRESET" spirit:choiceRef="choice_list_8b5e4915" spirit:order="65">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PHY_LP_TXPRESET">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>coreclk_freq</spirit:name>
|
|
<spirit:displayName>CORE CLOCK FREQ</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.coreclk_freq" spirit:choiceRef="choice_list_007d0a61" spirit:order="66">500</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>plltype</spirit:name>
|
|
<spirit:displayName>PLL TYPE</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.plltype" spirit:choiceRef="choice_list_94684ae0" spirit:order="67">QPLL1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_axi_intf_mm</spirit:name>
|
|
<spirit:displayName>XDMA Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_axi_intf_mm" spirit:choiceRef="choice_list_a71f3969" spirit:order="68">AXI_Memory_Mapped</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xdma_axi_intf_mm">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_pcie_64bit_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_pcie_64bit_en" spirit:order="69">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>silicon_rev</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.silicon_rev" spirit:choiceRef="choice_list_9f5580fd" spirit:order="70">Pre-Production</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_dsc_bypass</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_dsc_bypass" spirit:order="71">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>performance</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.performance" spirit:order="72">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pcie_extended_tag</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_extended_tag" spirit:order="73">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>rx_detect</spirit:name>
|
|
<spirit:displayName>Receiver Detect</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.rx_detect" spirit:choiceRef="choice_list_4e419c85" spirit:order="74">Default</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_link_status_slot_clock_config</spirit:name>
|
|
<spirit:displayName>Pf0 Link Status Slot Clock Config</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_link_status_slot_clock_config" spirit:choiceRef="choice_list_7a7dde49" spirit:order="75">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dsc_bypass_rd</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_rd" spirit:choiceRef="choice_list_47140c0d" spirit:order="76">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dsc_bypass_wr</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_wr" spirit:choiceRef="choice_list_47140c0d" spirit:order="77">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_sts_ports</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_sts_ports" spirit:order="78">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_cap_table_size</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_size" spirit:order="80">01F</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_cap_table_offset</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_offset" spirit:order="81">00008000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_cap_table_bir</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_table_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="82">BAR_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_cap_pba_offset</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_pba_offset" spirit:order="83">00008FE0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_cap_pba_bir</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_cap_pba_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="84">BAR_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79.5">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_cap_table_size</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_size" spirit:order="80.5">000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_table_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_cap_table_offset</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_offset" spirit:order="81.5">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_table_offset">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_cap_table_bir</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_table_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="82.5">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_table_bir">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_cap_pba_offset</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_pba_offset" spirit:order="83.5">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_pba_offset">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_cap_pba_bir</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_cap_pba_bir" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="84.5">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_msix_cap_pba_bir">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>cfg_mgmt_if</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_mgmt_if" spirit:order="85">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.cfg_mgmt_if">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ins_loss_profile</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ins_loss_profile" spirit:choiceRef="choice_list_0f93492c" spirit:order="63.5">Add-in_Card</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axil_master_64bit_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axil_master_64bit_en" spirit:order="86">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axil_master_64bit_en">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_bypass_64bit_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_bypass_64bit_en" spirit:order="87">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axil_master_prefetchable</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axil_master_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axil_master_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_pcie_prefetchable</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_pcie_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="88">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.xdma_pcie_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_bypass_prefetchable</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_bypass_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="89">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axi_bypass_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>cfg_ext_if</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_ext_if" spirit:order="90">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.cfg_ext_if">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>legacy_cfg_ext_if</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.legacy_cfg_ext_if" spirit:order="90.1">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.legacy_cfg_ext_if">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>parity_settings</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.parity_settings" spirit:choiceRef="choice_list_2dba17cd" spirit:order="91">None</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.parity_settings">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ecc_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ecc_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="91.1">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.ecc_en">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_debug_ports</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_debug_ports" spirit:order="92">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_id_width</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axi_id_width" spirit:choiceRef="choice_list_110bd32e" spirit:order="93">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axi_id_width">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vu9p_board</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vu9p_board" spirit:order="93.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>type1_membase_memlimit_enable</spirit:name>
|
|
<spirit:displayName>Type1 Config MemBase and MemLimit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_membase_memlimit_enable" spirit:choiceRef="choice_list_fc3456a9" spirit:order="93.2">Disabled</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.type1_membase_memlimit_enable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>type1_prefetchable_membase_memlimit</spirit:name>
|
|
<spirit:displayName>Type1 Config Prefetchable MemBase and MemLimit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.type1_prefetchable_membase_memlimit" spirit:choiceRef="choice_list_e9cf6440" spirit:order="93.3">Disabled</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.type1_prefetchable_membase_memlimit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_jtag_dbg</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_jtag_dbg" spirit:order="94">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_jtag_dbg">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_ltssm_dbg</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ltssm_dbg" spirit:order="94.11">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_ltssm_dbg">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_ibert</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ibert" spirit:order="94.1">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.enable_ibert">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_num</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_num" spirit:order="95" spirit:configGroups="1 UnGrouped" spirit:minimum="1" spirit:maximum="6" spirit:rangeType="long">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_num">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_0" spirit:order="96" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_1" spirit:order="97" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_2" spirit:order="98" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_3" spirit:order="99" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_4" spirit:order="100" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_5" spirit:order="101" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_0" spirit:order="102" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_1" spirit:order="103" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_2" spirit:order="104" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_3" spirit:order="105" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_4" spirit:order="106" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar_highaddr_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar_highaddr_5" spirit:order="107" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar_highaddr_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_0" spirit:order="108" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_1" spirit:order="109" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_2" spirit:order="110" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_3" spirit:order="111" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_4" spirit:order="112" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axibar2pciebar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axibar2pciebar_5" spirit:order="113" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.axibar2pciebar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>include_baroffset_reg</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.include_baroffset_reg" spirit:choiceRef="choice_list_7a7dde49" spirit:order="116" spirit:configGroups="1 UnGrouped">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.include_baroffset_reg">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>BASEADDR</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.BASEADDR" spirit:order="117" spirit:configGroups="1 UnGrouped">0x00001000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.BASEADDR">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>HIGHADDR</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.HIGHADDR" spirit:order="118" spirit:configGroups="1 UnGrouped">0x00001FFF</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.HIGHADDR">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>s_axi_id_width</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.s_axi_id_width" spirit:choiceRef="choice_list_6a0870a7" spirit:order="119" spirit:configGroups="1 UnGrouped">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.s_axi_id_width">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_m_axi_num_write</spirit:name>
|
|
<spirit:displayName>AXI Master outstanding write Transactions Selection</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_write" spirit:choiceRef="choice_list_8112d406" spirit:order="120">8</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_m_axi_num_write">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_m_axi_num_read</spirit:name>
|
|
<spirit:displayName>AXI Master outstanding read Transactions Selection</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_read" spirit:choiceRef="choice_list_ca108395" spirit:order="121">8</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_m_axi_num_read">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_m_axi_num_readq</spirit:name>
|
|
<spirit:displayName>AXI Master outstanding read Transactions Selection</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_m_axi_num_readq" spirit:choiceRef="choice_list_110bd32e" spirit:order="121.1">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_s_axi_num_write</spirit:name>
|
|
<spirit:displayName>AXI Slave outstanding write Transactions Selection</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_num_write" spirit:choiceRef="choice_list_ca108395" spirit:order="122">8</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_s_axi_num_write">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_s_axi_num_read</spirit:name>
|
|
<spirit:displayName>AXI Slave outstanding read Transactions Selection</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_num_read" spirit:choiceRef="choice_list_ca108395" spirit:order="123">8</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.c_s_axi_num_read">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_impl_locn</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Implementation Location</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_impl_locn" spirit:choiceRef="choice_list_9aec9108" spirit:order="124">Internal</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_aclk_loopback</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_aclk_loopback" spirit:order="125">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="126">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_enabled">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="127">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_size" spirit:choiceRef="choice_list_08bf412c" spirit:order="128">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_size">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="129">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_scale">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="130">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_64bit">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="131">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_enabled">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="133">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="134">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="135">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="136">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="137">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="138">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="139">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="140">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="141">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="142">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="143">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="144">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="145">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="146">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="147">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="148">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="149">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="150">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="151">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="152">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="153">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="154">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="155">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="156">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="157">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="158">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="159">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="160">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="161">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_bar5_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_0" spirit:order="162" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_1" spirit:order="163" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_2" spirit:order="164" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_3" spirit:order="165" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_4" spirit:order="166" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_5" spirit:order="167" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pciebar2axibar_6</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pciebar2axibar_6" spirit:order="167.1" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pciebar2axibar_6">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar_indicator" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="168">BAR_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar0_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar0_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="169">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar0_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar1_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar1_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="170">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar1_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar2_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar2_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="171">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar2_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar3_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar3_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="172">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar3_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar4_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar4_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="173">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar4_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bar5_indicator</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bar5_indicator" spirit:choiceRef="choice_list_6727dfa6" spirit:order="174">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.bar5_indicator">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>barlite2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.barlite2" spirit:choiceRef="choice_list_b0ffef10" spirit:order="174.5">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_dbg_descramble</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_dbg_descramble" spirit:order="175">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.en_dbg_descramble">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vcu118_board</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vcu118_board" spirit:order="176">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>tl_pf_enable_reg</spirit:name>
|
|
<spirit:displayName>NUM PF Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.tl_pf_enable_reg" spirit:choiceRef="choice_list_ae9f88f6" spirit:order="177">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_vendor_id</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_vendor_id" spirit:order="178">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_device_id</spirit:name>
|
|
<spirit:displayName>PF1 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_device_id" spirit:order="179">1041</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code" spirit:order="190">070001</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_REVISION_ID" spirit:order="181">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SUBSYSTEM_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID" spirit:order="182">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_ID" spirit:order="183">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_Use_Class_Code_Lookup_Assistant</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="184">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PF1_Use_Class_Code_Lookup_Assistant">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_base_class_menu</spirit:name>
|
|
<spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_base_class_menu" spirit:choiceRef="choice_list_0d378f84" spirit:order="185">Simple_communication_controllers</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_base</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_base" spirit:order="186">07</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_base">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_sub</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_sub" spirit:order="187">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_sub">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sub_class_interface_menu</spirit:name>
|
|
<spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sub_class_interface_menu" spirit:choiceRef="choice_list_3cee6ea1" spirit:order="188">16450_compatible_serial_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_sub_class_interface_menu">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_interface</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_interface" spirit:order="189">01</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_interface">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_INTERRUPT_PIN</spirit:name>
|
|
<spirit:displayName>Pf1 Interrupt Pin</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="191">NONE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msi_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Msi Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="192">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSI_CAP_MULTIMSGCAP</spirit:name>
|
|
<spirit:displayName>Pf1 Msi Cap Multimsgcap</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="193">1_vector</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="194">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="195">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar0_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="196">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="197">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf1 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="198">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="199">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="200">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="201">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="202">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="203">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf1 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="204">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="205">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="206">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="207">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="208">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="209">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf1 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="210">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="211">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="212">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="213">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="214">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="215">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf1 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="216">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="217">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="218">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="219.5">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="220">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="221">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf1 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="222">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="223">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf1 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="224">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="225">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf1 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_size" spirit:choiceRef="choice_list_f94ec5c4" spirit:order="226">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf1 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="227">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf1 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="228">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_device_id</spirit:name>
|
|
<spirit:displayName>PF2 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_device_id" spirit:order="229">1040</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code</spirit:name>
|
|
<spirit:displayName>pf2 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code" spirit:order="240">058000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_REVISION_ID</spirit:name>
|
|
<spirit:displayName>pf2 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_REVISION_ID" spirit:order="231">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SUBSYSTEM_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>pf2 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID" spirit:order="232">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>pf2 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_ID" spirit:order="233">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_Use_Class_Code_Lookup_Assistant</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="234">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_base_class_menu</spirit:name>
|
|
<spirit:displayName>pf2 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="235">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_base</spirit:name>
|
|
<spirit:displayName>pf2 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_base" spirit:order="236">05</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_sub</spirit:name>
|
|
<spirit:displayName>pf2 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_sub" spirit:order="237">80</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sub_class_interface_menu</spirit:name>
|
|
<spirit:displayName>pf2 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="238">Other_memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_interface</spirit:name>
|
|
<spirit:displayName>pf2 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_interface" spirit:order="239">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_INTERRUPT_PIN</spirit:name>
|
|
<spirit:displayName>pf2 Interrupt Pin</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="241">NONE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_msi_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Msi Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="242">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSI_CAP_MULTIMSGCAP</spirit:name>
|
|
<spirit:displayName>pf2 Msi Cap Multimsgcap</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="243">1_vector</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="244">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="245">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar0_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="246">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="247">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_64bit</spirit:name>
|
|
<spirit:displayName>pf2 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="248">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="249">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="250">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="251">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar1_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="252">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="253">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_64bit</spirit:name>
|
|
<spirit:displayName>pf2 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="254">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="255">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="256">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="257">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar2_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="258">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="259">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_64bit</spirit:name>
|
|
<spirit:displayName>pf2 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="260">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="261">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="262">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="263">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar3_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="264">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="265">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_64bit</spirit:name>
|
|
<spirit:displayName>pf2 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="266">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="267">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="268">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="269">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar4_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="270">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="271">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_64bit</spirit:name>
|
|
<spirit:displayName>pf2 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="272">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="273">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_enabled</spirit:name>
|
|
<spirit:displayName>pf2 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="274">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="275">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_bar5_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_size</spirit:name>
|
|
<spirit:displayName>pf2 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="276">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_scale</spirit:name>
|
|
<spirit:displayName>pf2 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="277">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>pf2 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="278">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_device_id</spirit:name>
|
|
<spirit:displayName>PF3 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_device_id" spirit:order="279">1039</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code</spirit:name>
|
|
<spirit:displayName>Pf3 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code" spirit:order="290">058000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_REVISION_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_REVISION_ID" spirit:order="281">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SUBSYSTEM_VENDOR_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID" spirit:order="282">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SUBSYSTEM_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_ID" spirit:order="283">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_Use_Class_Code_Lookup_Assistant</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_Use_Class_Code_Lookup_Assistant" spirit:choiceRef="choice_list_7a7dde49" spirit:order="284">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_base_class_menu</spirit:name>
|
|
<spirit:displayName>Pf3 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_base_class_menu" spirit:choiceRef="choice_list_dff1a45d" spirit:order="285">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_base</spirit:name>
|
|
<spirit:displayName>Pf3 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_base" spirit:order="286.1">05</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_sub</spirit:name>
|
|
<spirit:displayName>Pf3 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_sub" spirit:order="287">80</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sub_class_interface_menu</spirit:name>
|
|
<spirit:displayName>Pf3 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sub_class_interface_menu" spirit:choiceRef="choice_list_589df8e9" spirit:order="288">Other_memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_interface</spirit:name>
|
|
<spirit:displayName>Pf3 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_interface" spirit:order="289">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_INTERRUPT_PIN</spirit:name>
|
|
<spirit:displayName>Pf3 Interrupt Pin</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_INTERRUPT_PIN" spirit:choiceRef="choice_list_f1174048" spirit:order="291">NONE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_msi_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Msi Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msi_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="292">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSI_CAP_MULTIMSGCAP</spirit:name>
|
|
<spirit:displayName>Pf3 Msi Cap Multimsgcap</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSI_CAP_MULTIMSGCAP" spirit:choiceRef="choice_list_5e45706a" spirit:order="293">1_vector</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="294">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="295">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar0_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="296">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="297">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf3 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="298">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="299">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="300">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="301">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar1_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="302">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="303">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf3 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="304">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="305">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="306">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="307">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar2_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="308">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="309">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf3 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="310">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="311">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="312">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="313">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar3_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="314">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="315">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf3 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="316">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="317">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="318">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="319">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar4_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="320">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="321">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf3 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="322">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="323">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf3 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="324">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_type" spirit:choiceRef="choice_list_c3d223d9" spirit:order="325">Memory</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_bar5_type">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf3 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="326">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf3 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_scale" spirit:choiceRef="choice_list_d1e1a340" spirit:order="327">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf3 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="328">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>split_dma</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.split_dma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.split_dma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>split_dma_single_pf</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.split_dma_single_pf" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>mult_pf_des</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.mult_pf_des" spirit:order="329.5">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf_swap</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pf_swap" spirit:order="329.6">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>prog_usr_irq_vec_map</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.prog_usr_irq_vec_map" spirit:order="329.61">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>rcfg_nph_fix_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rcfg_nph_fix_en" spirit:order="329.62">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>post_synth_sim_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.post_synth_sim_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.7">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>user_pf_two_axilite_bar_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.user_pf_two_axilite_bar_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.75">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>two_bypass_bar</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.two_bypass_bar" spirit:choiceRef="choice_list_7a7dde49" spirit:order="329.8">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xlnx_ref_board</spirit:name>
|
|
<spirit:displayName>Xlnx Ref Board</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.xlnx_ref_board" spirit:choiceRef="choice_list_a2753f1e" spirit:order="330">None</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.xlnx_ref_board">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_l23_entry</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_l23_entry" spirit:order="331">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_0" spirit:order="332" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_1" spirit:order="333" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_2" spirit:order="334" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_3" spirit:order="335" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_4" spirit:order="336" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_5" spirit:order="337" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_pciebar2axibar_6</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_pciebar2axibar_6" spirit:order="337.1" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_pciebar2axibar_6">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_0" spirit:order="338" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_1" spirit:order="339" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_2" spirit:order="340" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_3" spirit:order="341" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_4" spirit:order="342" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_pciebar2axibar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_pciebar2axibar_5" spirit:order="343" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_pciebar2axibar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_0" spirit:order="344" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_1</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_1" spirit:order="345" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_1">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_2</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_2" spirit:order="346" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_2">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_3</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_3" spirit:order="347" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_3">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_4</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_4" spirit:order="348" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_4">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_pciebar2axibar_5</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_pciebar2axibar_5" spirit:order="349" spirit:configGroups="1 UnGrouped">0x0000000000000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_pciebar2axibar_5">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gtwiz_in_core_us</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtwiz_in_core_us" spirit:choiceRef="choice_pairs_3c87fcdb" spirit:order="350">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gtwiz_in_core_usp</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtwiz_in_core_usp" spirit:choiceRef="choice_pairs_3c87fcdb" spirit:order="351.1">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dma_reset_source_sel</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dma_reset_source_sel" spirit:choiceRef="choice_list_8f346c48" spirit:order="352">User_Reset</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.dma_reset_source_sel">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_dma_and_bridge</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_dma_and_bridge" spirit:order="353">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_coreclk_es1</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_coreclk_es1" spirit:order="354">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pipe_line_stage</spirit:name>
|
|
<spirit:displayName>number of Pipe Line Stages</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pipe_line_stage" spirit:choiceRef="choice_list_c63ab5b1" spirit:order="355">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pipe_line_stage">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axis_pipe_line_stage</spirit:name>
|
|
<spirit:displayName>number of Pipe Line Stages on PCIe axis interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axis_pipe_line_stage" spirit:choiceRef="choice_list_c63ab5b1" spirit:order="355">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.axis_pipe_line_stage">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vu9p_tul_ex</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vu9p_tul_ex" spirit:order="356">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vcu1525_ddr_ex</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vcu1525_ddr_ex" spirit:order="356.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_bridge</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_bridge" spirit:order="357">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_ccix</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ccix" spirit:choiceRef="choice_list_e7c484ae" spirit:order="358">FALSE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_dvsec</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_dvsec" spirit:choiceRef="choice_list_e7c484ae" spirit:order="358.1">FALSE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ext_sys_clk_bufg</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ext_sys_clk_bufg" spirit:order="359">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>usr_irq_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.usr_irq_exdes" spirit:order="360">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axi_vip_in_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axi_vip_in_exdes" spirit:order="360">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_non_incremental_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_non_incremental_exdes" spirit:order="360.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>xdma_st_infinite_desc_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.xdma_st_infinite_desc_exdes" spirit:order="360.2">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gtcom_in_core_usp</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gtcom_in_core_usp" spirit:choiceRef="choice_pairs_6f00a734" spirit:order="361">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_mqdma</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_mqdma" spirit:order="361">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SRIOV_CAP_ENABLE</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_CAP_ENABLE" spirit:order="362">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.SRIOV_CAP_ENABLE">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ext_xvc_vsec_enable</spirit:name>
|
|
<spirit:displayName>Enable to add the PCIe XVC-VSEC to the Examlpe Design</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.ext_xvc_vsec_enable" spirit:order="397.1">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.ext_xvc_vsec_enable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>acs_ext_cap_enable</spirit:name>
|
|
<spirit:displayName>ACS Ext Capability</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.acs_ext_cap_enable" spirit:order="397.2">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="398">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_type_mqdma" spirit:choiceRef="choice_list_8a9e69a3" spirit:order="399">DMA</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="400">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="401">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="402">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="403">128</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="404">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="405">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="406">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="407">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="408">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="409">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar1_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="410">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="411">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="412">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="413">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="414">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="415">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar2_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="416">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="417">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="418">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="419">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="420">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="421">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar3_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="422">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="423">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="424">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="425">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="426">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="427">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar4_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="428">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="429">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="430">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_scale_mqdma" spirit:choiceRef="choice_list_52d29139" spirit:order="431">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_size_mqdma" spirit:choiceRef="choice_list_c15e8c67" spirit:order="432">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_bar5_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="433">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="434">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="435">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="436">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="437">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="438">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar0_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="439">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="440">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="441">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="442">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="443">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="444">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar1_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="445">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="446">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="447">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="448">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="449">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="450">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar2_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="451">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="452">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="453">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="454">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="455">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="456">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar3_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="457">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="458">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="459">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="460">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="461">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="462">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar4_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="463">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="464">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="465">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="466">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="467">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_bar5_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="468">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="469">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="470">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="471">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="472">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="473">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar0_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="474">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="475">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="371">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="372">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="373">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="374">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar1_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="375">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="376">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="377">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="378">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="379">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="380">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar2_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="381">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="381">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="382">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="383">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="384">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="385">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar3_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="386">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="387">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="388">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="389">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="390">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="391">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar4_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="392">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="393">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="394">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="395">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="396">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_bar5_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="363">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_type_mqdma" spirit:choiceRef="choice_list_57749bc8" spirit:order="364">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="365">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="366">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="367">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="368">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar0_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="369">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="370">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="371">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="372">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="373">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar1 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="374">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar1_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="375">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="376">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="377">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="378">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="379">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar2 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="380">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar2_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="381">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="381">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="382">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="383">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="384">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar3 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="385">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar3_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="386">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="387">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_64bit_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_64bit_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="388">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_64bit_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="389">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_prefetchable_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="390">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar4 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="391">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar4_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="392">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_enabled_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_type_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_type_mqdma" spirit:choiceRef="choice_list_ec64e624" spirit:order="393">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_type_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_prefetchable_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_prefetchable_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="394">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_scale_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_scale_mqdma" spirit:choiceRef="choice_list_5e2921cd" spirit:order="395">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_scale_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_size_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Bar5 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_size_mqdma" spirit:choiceRef="choice_list_34d65ff4" spirit:order="396">128</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_bar5_size_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>copy_pf0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>copy_sriov_pf0</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.copy_sriov_pf0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="6.5">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_expansion_rom_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_expansion_rom_type</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_expansion_rom_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_scale" spirit:choiceRef="choice_list_fde36331" spirit:order="80">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_expansion_rom_size</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_expansion_rom_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_expansion_rom_type</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_expansion_rom_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_expansion_rom_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_scale" spirit:choiceRef="choice_list_fde36331" spirit:order="80">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_expansion_rom_size</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_expansion_rom_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_expansion_rom_type</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_expansion_rom_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_expansion_rom_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_scale" spirit:choiceRef="choice_list_fde36331" spirit:order="80">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_expansion_rom_size</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_expansion_rom_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_expansion_rom_type</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="79">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_expansion_rom_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="79">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_expansion_rom_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_scale" spirit:choiceRef="choice_list_fde36331" spirit:order="80">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_expansion_rom_size</spirit:name>
|
|
<spirit:displayName>Pf0 Expansion Rom Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_expansion_rom_size" spirit:choiceRef="choice_list_e7f13338" spirit:order="81">4</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_expansion_rom_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_type" spirit:choiceRef="choice_list_8a9e69a3" spirit:order="133">DMA</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar0_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar1_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar2_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar3_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar4_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_size" spirit:choiceRef="choice_list_c15e8c67" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_bar5_scale" spirit:choiceRef="choice_list_52d29139" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf0_sriov_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar0_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sriov_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_sriov_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar0_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sriov_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_sriov_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_type" spirit:choiceRef="choice_list_57749bc8" spirit:order="133">DMA</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar0_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar0_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar0_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar1_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar1_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar1_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar2_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar2_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar2_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar3_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar3_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar3_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_64bit">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_prefetchable">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar4_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar4_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar4_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="132">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_enabled">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_type</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_type" spirit:choiceRef="choice_list_ec64e624" spirit:order="133">N/A</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_type">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_64bit</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 64bit</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_64bit" spirit:choiceRef="choice_list_7a7dde49" spirit:order="134">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_prefetchable</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Prefetchable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_prefetchable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="135">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_size</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Size</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_size" spirit:choiceRef="choice_list_35d06715" spirit:order="137">2</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_size">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sriov_bar5_scale</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Bar0 Scale</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sriov_bar5_scale" spirit:choiceRef="choice_list_5e2921cd" spirit:order="136">Kilobytes</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_sriov_bar5_scale">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pcie_id_if</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pcie_id_if" spirit:order="24.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_vendor_id_mqdma</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_vendor_id_mqdma</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf1_vendor_id_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_vendor_id_mqdma</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_vendor_id_mqdma" spirit:order="24.2">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf2_vendor_id_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_vendor_id_mqdma</spirit:name>
|
|
<spirit:displayName>Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_vendor_id_mqdma" spirit:order="24.3">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.pf3_vendor_id_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_DEVICE_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_DEVICE_ID_mqdma" spirit:order="25.2">9021</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_DEVICE_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_DEVICE_ID_mqdma" spirit:order="25.2">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_DEVICE_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_DEVICE_ID_mqdma" spirit:order="25.2">9021</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_DEVICE_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_DEVICE_ID_mqdma" spirit:order="25.3">9021</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_REVISION_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_REVISION_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_REVISION_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_REVISION_ID_mqdma" spirit:order="26.2">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_REVISION_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Revision Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_REVISION_ID_mqdma" spirit:order="26.3">00</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SUBSYSTEM_VENDOR_ID_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.2">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SUBSYSTEM_VENDOR_ID_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SUBSYSTEM_VENDOR_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Vendor Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID_mqdma" spirit:order="27.3">10EE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SUBSYSTEM_VENDOR_ID_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SUBSYSTEM_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SUBSYSTEM_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SUBSYSTEM_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SUBSYSTEM_ID_mqdma" spirit:order="28.2">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SUBSYSTEM_ID_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Subsystem Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SUBSYSTEM_ID_mqdma" spirit:order="28.3">0007</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.6">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_Use_Class_Code_Lookup_Assistant_mqdma</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_Use_Class_Code_Lookup_Assistant_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="37.7">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_base_class_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_base_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_base_mqdma" spirit:order="186">05</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_base_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_sub_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_sub_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sub_class_interface_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_interface_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_interface_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_class_code_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_class_code_mqdma" spirit:order="190">058000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf0_class_code_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_base_class_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_base_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_base_mqdma" spirit:order="186">05</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_base_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_sub_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_sub_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_sub_class_interface_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_interface_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_interface_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_class_code_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_class_code_mqdma" spirit:order="190">058000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf1_class_code_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_base_class_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_base_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_base_mqdma" spirit:order="186">05</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_base_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_sub_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_sub_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_sub_class_interface_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_interface_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_interface_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_class_code_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_class_code_mqdma" spirit:order="190">058000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf2_class_code_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_base_class_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Base Class Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_base_class_menu_mqdma" spirit:choiceRef="choice_list_96d6a000" spirit:order="185">Memory_controller</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_base_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Base</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_base_mqdma" spirit:order="186">05</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_base_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_sub_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Sub</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_sub_mqdma" spirit:order="187">80</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_sub_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_sub_class_interface_menu_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Sub Class Interface Menu</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_sub_class_interface_menu_mqdma" spirit:choiceRef="choice_list_df7cde9e" spirit:order="188">Other_memory_controller</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_sub_class_interface_menu_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_interface_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code Interface</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_interface_mqdma" spirit:order="189">00</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_interface_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_class_code_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Class Code</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_class_code_mqdma" spirit:order="190">058000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.pf3_class_code_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SRIOV_FIRST_VF_OFFSET</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SRIOV_FIRST_VF_OFFSET" spirit:choiceRef="choice_list_ae9f88f6" spirit:order="122.5">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_sriov_cap_ver</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Cap Ver</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_sriov_cap_ver" spirit:order="120">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SRIOV_CAP_INITIAL_VF</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_fe1fb7c4" spirit:order="121">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SRIOV_FUNC_DEP_LINK</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Func Dep Link</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK" spirit:order="122">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SRIOV_FIRST_VF_OFFSET</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov First Vf Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET" spirit:order="123">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SRIOV_VF_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Vf Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID" spirit:order="124">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Supported Page Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125">00000553</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_CAP_VER</spirit:name>
|
|
<spirit:displayName>Pf1 Sriov Cap Ver</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_VER" spirit:order="126">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_CAP_VER">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_CAP_INITIAL_VF</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_FIRST_VF_OFFSET</spirit:name>
|
|
<spirit:displayName>Pf1 Sriov First Vf Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET" spirit:order="123.11">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_FUNC_DEP_LINK</spirit:name>
|
|
<spirit:displayName>Pf1 Sriov Func Dep Link</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK" spirit:order="128">0001</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf1 Sriov Supported Page Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="131">00000553</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_SRIOV_VF_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf1 Sriov Vf Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID" spirit:order="130">A131</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_CAP_VER</spirit:name>
|
|
<spirit:displayName>Pf2 Sriov Cap Ver</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_VER" spirit:order="126.2">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_CAP_VER">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_CAP_INITIAL_VF</spirit:name>
|
|
<spirit:displayName>Pf0 Sriov Cap Initial Vf</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_FIRST_VF_OFFSET</spirit:name>
|
|
<spirit:displayName>Pf2 Sriov First Vf Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FIRST_VF_OFFSET" spirit:order="123.2">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_FUNC_DEP_LINK</spirit:name>
|
|
<spirit:displayName>Pf2 Sriov Func Dep Link</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_FUNC_DEP_LINK" spirit:order="122.2">0002</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf2 Sriov Supported Page Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.2">00000553</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_SRIOV_VF_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf2 Sriov Vf Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID" spirit:order="124.2">A231</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_CAP_INITIAL_VF</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov Cap Initial Vf</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_INITIAL_VF" spirit:choiceRef="choice_list_d85ad257" spirit:order="121.3">0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_CAP_INITIAL_VF">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_CAP_VER</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov Cap Ver</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_CAP_VER" spirit:order="126.3">1</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_CAP_VER">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_FIRST_VF_OFFSET</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov First Vf Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FIRST_VF_OFFSET" spirit:order="123.3">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_FUNC_DEP_LINK</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov Func Dep Link</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_FUNC_DEP_LINK" spirit:order="122.3">0003</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_FUNC_DEP_LINK">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_SUPPORTED_PAGE_SIZE</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov Supported Page Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_SUPPORTED_PAGE_SIZE" spirit:order="125.3">00000553</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_SRIOV_VF_DEVICE_ID</spirit:name>
|
|
<spirit:displayName>Pf3 Sriov Vf Device Id</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID" spirit:order="124.3">A331</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_SRIOV_VF_DEVICE_ID">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_ari_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Ari Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_ari_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="277">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_msix_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="214">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_msix_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="220">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_msix_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.2">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_msix_enabled_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Msix Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_msix_enabled_mqdma" spirit:choiceRef="choice_list_7a7dde49" spirit:order="215.3">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="215">000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="221">000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="220.2">000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSIX_CAP_TABLE_SIZE_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Msix Cap Table Size</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_SIZE_mqdma" spirit:order="220.3">000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_SIZE_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="222">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216.2">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSIX_CAP_TABLE_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Msix Cap Table Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_OFFSET_mqdma" spirit:order="216.3">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSIX_CAP_TABLE_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Table Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_TABLE_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="217">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_TABLE_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="218">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="224">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="224.2">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSIX_CAP_PBA_OFFSET_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Msix Cap Pba Offset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_OFFSET_mqdma" spirit:order="218.3">00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_OFFSET_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF0_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf0 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF0_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF1_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf1 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="225">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF1_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF2_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf2 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF2_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.2">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF2_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PF3_MSIX_CAP_PBA_BIR_mqdma</spirit:name>
|
|
<spirit:displayName>Pf3 Msix Cap Pba Bir</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PF3_MSIX_CAP_PBA_BIR_mqdma" spirit:choiceRef="choice_list_3ca2cbc7" spirit:order="219.3">BAR_0</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PF3_MSIX_CAP_PBA_BIR_mqdma">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MSI_X_OPTIONS</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MSI_X_OPTIONS" spirit:choiceRef="choice_list_bea500ca" spirit:order="200.1">None</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.MSI_X_OPTIONS">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dsc_bypass_rd_out</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_rd_out" spirit:choiceRef="choice_list_47140c0d" spirit:order="76">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dsc_bypass_wr_out</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dsc_bypass_wr_out" spirit:choiceRef="choice_list_47140c0d" spirit:order="77">0000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>num_queues</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.num_queues" spirit:order="59" spirit:minimum="1" spirit:maximum="2048" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_auto_rxeq</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_auto_rxeq" spirit:choiceRef="choice_list_bdd7203f" spirit:order="476">False</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_pcie_debug_ports</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_pcie_debug_ports" spirit:choiceRef="choice_list_bdd7203f" spirit:order="477">False</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_pcie_debug</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_pcie_debug" spirit:choiceRef="choice_list_bdd7203f" spirit:order="477.001">False</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_pcie_debug_axi4_st</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_pcie_debug_axi4_st" spirit:choiceRef="choice_list_bdd7203f" spirit:order="477.002">False</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axisten_if_enable_msg_route</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.axisten_if_enable_msg_route" spirit:order="478">27FFF</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_axi_mm_mqdma</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_mm_mqdma" spirit:order="479">true</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_mm_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_axi_st_mqdma</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_axi_st_mqdma" spirit:order="480">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.en_axi_st_mqdma">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_more_clk</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_more_clk" spirit:order="479">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>tl_credits_cd</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_cd" spirit:order="480">15</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>tl_credits_ch</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_credits_ch" spirit:order="481">15</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>set_finite_credit</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.set_finite_credit" spirit:order="482">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>disable_bram_pipeline</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_bram_pipeline" spirit:order="483">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>disable_eq_synchronizer</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_eq_synchronizer" spirit:order="484">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_resource_reduction</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_resource_reduction" spirit:order="485">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_ats_enable</spirit:name>
|
|
<spirit:displayName>ATS Extended Capability Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_ats_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="486">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_pri_enable</spirit:name>
|
|
<spirit:displayName>Page Request Extended Capability Enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_pri_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="487">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>usplus_es1_seqnum_bypass</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.usplus_es1_seqnum_bypass" spirit:choiceRef="choice_list_7a7dde49" spirit:order="488">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bridge_registers_offset_enable</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bridge_registers_offset_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="489">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_gen4</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_gen4" spirit:order="490">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>tandem_enable_rfsoc</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.tandem_enable_rfsoc" spirit:order="490.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>local_test</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.local_test" spirit:order="490.2">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gen4_eieos_0s7</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.gen4_eieos_0s7" spirit:order="491">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_s_axi_supports_narrow_burst</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.c_s_axi_supports_narrow_burst" spirit:order="492">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_ats_switch</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_ats_switch" spirit:choiceRef="choice_list_e7c484ae" spirit:order="493">FALSE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_ats_switch_unique_bdf</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_ats_switch_unique_bdf" spirit:choiceRef="choice_list_8af5a703" spirit:order="493.1">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ctrl_skip_mask</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ctrl_skip_mask" spirit:order="494">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_ats_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Ats Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_ats_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="458">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_pri_enabled</spirit:name>
|
|
<spirit:displayName>Pf0 Pri Enabled</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pri_enabled" spirit:choiceRef="choice_list_7a7dde49" spirit:order="459">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>aspm_support</spirit:name>
|
|
<spirit:displayName>ASPM Support</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.aspm_support" spirit:choiceRef="choice_list_04670499" spirit:order="460">No_ASPM</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_aer_cap_ecrc_gen_and_check_capable</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_aer_cap_ecrc_gen_and_check_capable" spirit:order="461">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gen_pipe_debug</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gen_pipe_debug" spirit:choiceRef="choice_list_7a7dde49" spirit:order="462">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>soft_reset_en</spirit:name>
|
|
<spirit:displayName>DMA Bridge Reset</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.soft_reset_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="463">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>msi_rx_pin_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msi_rx_pin_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464">FALSE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>msix_rx_pin_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_rx_pin_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464.1">TRUE</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>msix_rx_decode_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_rx_decode_en" spirit:choiceRef="choice_list_e7c484ae" spirit:order="464.2">FALSE</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.msix_rx_decode_en">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>intx_rx_pin_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.intx_rx_pin_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="464.3">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>msix_type</spirit:name>
|
|
<spirit:displayName>MSI-X Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.msix_type" spirit:choiceRef="choice_list_38306dd1" spirit:order="465">HARD</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>cfg_space_enable</spirit:name>
|
|
<spirit:displayName>config space enable</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.cfg_space_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="461">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>runbit_fix</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.runbit_fix" spirit:order="495">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>axsize_byte_access_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.axsize_byte_access_en" spirit:order="495.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_lane_reversal</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_lane_reversal" spirit:order="496">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_mark_debug</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_mark_debug" spirit:choiceRef="choice_list_7a7dde49" spirit:order="497">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>master_cal_only</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.master_cal_only" spirit:choiceRef="choice_list_7a7dde49" spirit:order="498">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_multi_pcie</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.enable_multi_pcie" spirit:choiceRef="choice_list_7a7dde49" spirit:order="499">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>rbar_enable</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.rbar_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="500">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_num</spirit:name>
|
|
<spirit:displayName>Number of Resizable BARs for PF0</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="501">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_num</spirit:name>
|
|
<spirit:displayName>Number of Resizable BARs for PF1</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="502">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_num</spirit:name>
|
|
<spirit:displayName>Number of Resizable BARs for PF2</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="503">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_num</spirit:name>
|
|
<spirit:displayName>Number of Resizable BARs for PF3</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_num" spirit:choiceRef="choice_list_847d868a" spirit:order="504">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar0_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR0 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar0_index" spirit:order="505">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar1_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR1 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar1_index" spirit:order="506">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar2_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR2 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar2_index" spirit:order="507">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar3_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR3 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar3_index" spirit:order="508">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar4_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR4 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar4_index" spirit:order="509">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_bar5_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR5 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_bar5_index" spirit:order="510">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar0_index</spirit:name>
|
|
<spirit:displayName>PF0 BAR0 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar0_index" spirit:order="511">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar1_index</spirit:name>
|
|
<spirit:displayName>PF1 BAR1 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar1_index" spirit:order="512">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar2_index</spirit:name>
|
|
<spirit:displayName>PF1 BAR2 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar2_index" spirit:order="513">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar3_index</spirit:name>
|
|
<spirit:displayName>PF1 BAR3 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar3_index" spirit:order="514">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar4_index</spirit:name>
|
|
<spirit:displayName>PF1 BAR4 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar4_index" spirit:order="515">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_bar5_index</spirit:name>
|
|
<spirit:displayName>PF1 BAR5 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_bar5_index" spirit:order="516">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar0_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR0 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar0_index" spirit:order="517">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar1_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR1 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar1_index" spirit:order="518">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar2_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR2 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar2_index" spirit:order="519">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar3_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR3 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar3_index" spirit:order="520">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar4_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR4 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar4_index" spirit:order="521">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_bar5_index</spirit:name>
|
|
<spirit:displayName>PF2 BAR5 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_bar5_index" spirit:order="522">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar0_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR0 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar0_index" spirit:order="523">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar1_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR1 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar1_index" spirit:order="524">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar2_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR2 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar2_index" spirit:order="525">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar3_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR3 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar3_index" spirit:order="526">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar4_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR4 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar4_index" spirit:order="527">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_bar5_index</spirit:name>
|
|
<spirit:displayName>PF3 BAR5 index</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_bar5_index" spirit:order="528">7</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar0</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR0</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar0" spirit:order="529">0xffffffffffff</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar1</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR1</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar1" spirit:order="530">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar2</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR2</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar2" spirit:order="531">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar3</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR3</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar3" spirit:order="532">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar4</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR4</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar4" spirit:order="533">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_rbar_cap_bar5</spirit:name>
|
|
<spirit:displayName>PF0 RBAR CAP BAR5</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_rbar_cap_bar5" spirit:order="534">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar0</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR0</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar0" spirit:order="535">0xffffffffffff</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar1</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR1</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar1" spirit:order="536">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar2</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR2</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar2" spirit:order="537">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar3</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR3</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar3" spirit:order="538">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar4</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR4</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar4" spirit:order="539">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf1_rbar_cap_bar5</spirit:name>
|
|
<spirit:displayName>PF1 RBAR CAP BAR5</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf1_rbar_cap_bar5" spirit:order="540">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar0</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR0</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar0" spirit:order="541">0xffffffffffff</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar1</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR1</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar1" spirit:order="542">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar2</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR2</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar2" spirit:order="543">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar3</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR3</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar3" spirit:order="544">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar4</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR4</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar4" spirit:order="545">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf2_rbar_cap_bar5</spirit:name>
|
|
<spirit:displayName>PF2 RBAR CAP BAR5</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf2_rbar_cap_bar5" spirit:order="546">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar0</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR0</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar0" spirit:order="547">0xffffffffffff</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar1</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR1</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar1" spirit:order="548">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar2</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR2</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar2" spirit:order="549">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar3</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR3</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar3" spirit:order="550">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar4</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR4</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar4" spirit:order="551">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf3_rbar_cap_bar5</spirit:name>
|
|
<spirit:displayName>PF3 RBAR CAP BAR5</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf3_rbar_cap_bar5" spirit:order="552">0x000000000000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>mpsoc_pl_rp_enable</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.mpsoc_pl_rp_enable" spirit:choiceRef="choice_list_7a7dde49" spirit:order="553">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>c_smmu_en</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.c_smmu_en" spirit:choiceRef="choice_list_8af5a703" spirit:order="555">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_slave_read_64os</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_slave_read_64os" spirit:choiceRef="choice_list_7a7dde49" spirit:order="556">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>m_axib_num_write_scale</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.m_axib_num_write_scale" spirit:choiceRef="choice_list_8aad6ae4" spirit:order="556.1">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>disable_gt_loc</spirit:name>
|
|
<spirit:displayName>Disable GT loc constraint delivery</spirit:displayName>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_gt_loc" spirit:choiceRef="choice_list_7a7dde49" spirit:order="557">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>use_standard_interfaces</spirit:name>
|
|
<spirit:displayName>use standard interfaces for IPI design</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.use_standard_interfaces" spirit:choiceRef="choice_list_7a7dde49" spirit:order="558">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>dma_2rp</spirit:name>
|
|
<spirit:displayName>Truncate ports for 2RP DMA design</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.dma_2rp" spirit:choiceRef="choice_list_7a7dde49" spirit:order="559">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>disable_user_clock_root</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.disable_user_clock_root" spirit:order="560">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>flr_enable</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.flr_enable" spirit:order="561">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_epyc_chipset_fix</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_epyc_chipset_fix" spirit:order="562">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>usrint_expn</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.usrint_expn" spirit:order="563">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>shell_bridge</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.shell_bridge" spirit:order="564">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>msix_pcie_internal</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.msix_pcie_internal" spirit:order="565">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>warm_reboot_sbr_fix</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.warm_reboot_sbr_fix" spirit:order="566">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>tl_tx_mux_strict_priority</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.tl_tx_mux_strict_priority" spirit:order="567">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_slot_cap_reg</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_slot_cap_reg" spirit:order="568">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.en_slot_cap_reg">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>slot_cap_reg</spirit:name>
|
|
<spirit:displayName>SLOT CAP REG</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.slot_cap_reg" spirit:order="569">00000040</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.slot_cap_reg">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>sim_model</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.sim_model" spirit:choiceRef="choice_list_ef28ef63" spirit:order="570">NO</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>versal</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.versal" spirit:choiceRef="choice_list_7a7dde49" spirit:order="571">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.versal">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>lane_order</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.lane_order" spirit:choiceRef="choice_list_2d4b70a0" spirit:order="572.1">Bottom</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>gt_loc_num</spirit:name>
|
|
<spirit:displayName>Gt Loc Num</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.gt_loc_num" spirit:choiceRef="choice_list_d82124da" spirit:order="573">X99Y99</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>example_design_type</spirit:name>
|
|
<spirit:displayName>Example Design Type</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.example_design_type" spirit:choiceRef="choice_list_cd8829a5" spirit:order="574">RTL</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_error_injection</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_error_injection" spirit:choiceRef="choice_list_7a7dde49" spirit:order="575">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>performance_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.performance_exdes" spirit:choiceRef="choice_list_7a7dde49" spirit:order="576">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>descriptor_bypass_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.descriptor_bypass_exdes" spirit:choiceRef="choice_list_7a7dde49" spirit:order="577">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>vdm_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.vdm_en" spirit:choiceRef="choice_list_7a7dde49" spirit:order="578">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>virtio_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.virtio_exdes" spirit:choiceRef="choice_list_7a7dde49" spirit:order="579">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>virtio_perf_exdes</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.virtio_perf_exdes" spirit:choiceRef="choice_list_7a7dde49" spirit:order="580">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>bridge_burst</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.bridge_burst" spirit:choiceRef="choice_list_7a7dde49" spirit:order="581">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>insert_cips</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.insert_cips" spirit:choiceRef="choice_list_7a7dde49" spirit:order="582">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>en_bridge_slv</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.en_bridge_slv" spirit:order="583">false</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.en_bridge_slv">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>enable_clock_delay_grp</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.enable_clock_delay_grp" spirit:order="584">true</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>replace_uram_with_bram</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.replace_uram_with_bram" spirit:order="585">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>errc_dec_en</spirit:name>
|
|
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.errc_dec_en" spirit:order="586">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>all_speeds_all_sides</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.all_speeds_all_sides" spirit:choiceRef="choice_list_ef28ef63" spirit:order="587">NO</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_pm_cap_pmesupport_d0</spirit:name>
|
|
<spirit:displayName>Pf0 Pm Cap Pmesupport D0</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pm_cap_pmesupport_d0" spirit:choiceRef="choice_list_7a7dde49" spirit:order="588">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_pm_cap_pmesupport_d1</spirit:name>
|
|
<spirit:displayName>Pf0 Pm Cap Pmesupport D1</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pm_cap_pmesupport_d1" spirit:choiceRef="choice_list_7a7dde49" spirit:order="588.1">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_pm_cap_pmesupport_d3hot</spirit:name>
|
|
<spirit:displayName>Pf0 Pm Cap Pmesupport D3hot</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pm_cap_pmesupport_d3hot" spirit:choiceRef="choice_list_7a7dde49" spirit:order="588.2">false</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>pf0_pm_cap_supp_d1_state</spirit:name>
|
|
<spirit:displayName>Pf0 Pm Cap Supp D1 State</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.pf0_pm_cap_supp_d1_state" spirit:choiceRef="choice_list_7a7dde49" spirit:order="588.3">false</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:displayName>DMA/Bridge Subsystem for PCI Express</xilinx:displayName>
|
|
<xilinx:xpmLibraries>
|
|
<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
|
|
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
|
|
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
|
</xilinx:xpmLibraries>
|
|
<xilinx:coreRevision>20</xilinx:coreRevision>
|
|
<xilinx:configElementInfos>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ATSPRI_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_0.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_1.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_2.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_H2C_3.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.ID_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_B.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_BYPASS.ID_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_PROT" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TLAST" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC0_ATS_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_CQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_M_AXIS_RC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SC1_ATS_S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_0.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_1.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_2.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_C2H_3.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CC.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TREADY" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.HAS_TSTRB" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TDEST_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RQ.TID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_BURST" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_CACHE" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_LOCK" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_PROT" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_REGION" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_RRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.HAS_WSTRB" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_B.PROTOCOL" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF2_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF3_DEVICE_ID_mqdma" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axi_data_width" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axi_id_width" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axilite_master_en" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axist_bypass_en" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cfg_ext_if" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cfg_mgmt_if" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.copy_pf0" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.dedicate_perst" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.enable_gen4" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_blk_locn" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_extended_tag" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pcie_id_if" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pciebar2axibar_axil_master" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_base" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_interface" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_class_code_sub" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_device_id" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_interrupt_pin" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_link_status_slot_clock_config" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msi_enabled" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_pba_bir" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_pba_offset" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_table_bir" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_table_offset" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_table_size" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_enabled" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_scale" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar0_size" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar1_enabled" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar2_64bit" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar2_enabled" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar4_64bit" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_bar4_enabled" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_msix_cap_pba_offset" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_msix_cap_table_offset" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_msix_cap_table_size" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pipe_sim" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_speed" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pl_link_cap_max_link_width" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.plltype" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.runbit_fix" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_axi_intf_mm" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_axilite_slave" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_num_usr_irq" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_rnum_chnl" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_sts_ports" xilinx:valueSource="user"/>
|
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.xdma_wnum_rids" xilinx:valueSource="user"/>
|
|
</xilinx:configElementInfos>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="fda9d408"/>
|
|
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="3b0b31fa"/>
|
|
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="87cd4491"/>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="51c4e1d3"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="81ffd16f"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="84005c4c"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d2077e97"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|